TW200522164A - Planarization method of semiconductor deposition layer - Google Patents
Planarization method of semiconductor deposition layer Download PDFInfo
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- TW200522164A TW200522164A TW92137532A TW92137532A TW200522164A TW 200522164 A TW200522164 A TW 200522164A TW 92137532 A TW92137532 A TW 92137532A TW 92137532 A TW92137532 A TW 92137532A TW 200522164 A TW200522164 A TW 200522164A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 72
- 230000008021 deposition Effects 0.000 title claims abstract description 55
- 238000000034 method Methods 0.000 title claims abstract description 53
- 238000000151 deposition Methods 0.000 claims abstract description 55
- 238000005498 polishing Methods 0.000 claims abstract description 29
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 23
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 23
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 238000005229 chemical vapour deposition Methods 0.000 claims abstract description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 39
- 235000012239 silicon dioxide Nutrition 0.000 claims description 18
- 239000000377 silicon dioxide Substances 0.000 claims description 18
- 239000000126 substance Substances 0.000 claims description 18
- GQPLMRYTRLFLPF-UHFFFAOYSA-N nitrous oxide Inorganic materials [O-][N+]#N GQPLMRYTRLFLPF-UHFFFAOYSA-N 0.000 claims description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 5
- 229910000422 cerium(IV) oxide Inorganic materials 0.000 claims description 5
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- 239000001307 helium Substances 0.000 claims description 4
- 229910052734 helium Inorganic materials 0.000 claims description 4
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 claims description 4
- 239000007788 liquid Substances 0.000 claims description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 2
- 239000001272 nitrous oxide Substances 0.000 claims description 2
- 229910052760 oxygen Inorganic materials 0.000 claims description 2
- 239000001301 oxygen Substances 0.000 claims description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims 3
- CETPSERCERDGAM-UHFFFAOYSA-N ceric oxide Chemical compound O=[Ce]=O CETPSERCERDGAM-UHFFFAOYSA-N 0.000 claims 2
- 239000012530 fluid Substances 0.000 claims 2
- 229910000077 silane Inorganic materials 0.000 claims 2
- 238000002161 passivation Methods 0.000 abstract 2
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 238000002955 isolation Methods 0.000 description 3
- 230000006870 function Effects 0.000 description 2
- UGFAIRIUMAVXCW-UHFFFAOYSA-N Carbon monoxide Chemical compound [O+]#[C-] UGFAIRIUMAVXCW-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 229910000420 cerium oxide Inorganic materials 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- BMMGVYCKOGBVEV-UHFFFAOYSA-N oxo(oxoceriooxy)cerium Chemical compound [Ce]=O.O=[Ce]=O BMMGVYCKOGBVEV-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
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Abstract
Description
200522164 五、發明說明（1) 【發明所屬之技術領域】 本發明是有關於一種半導體沈積層之平坦化方法，且 特別是有關於一種於淺溝渠隔離（ST I)製程中增進半導體 沈積層表面平坦化的方法。 【先前技術】 在科技日新月異的現代社會中，各種電子產品已成為 現代人曰常生活中不可或缺部分。一般而言，電子產品皆 配置有不同之相對應之積體電路（lntegrated Circuit，200522164 V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to a method for planarizing a semiconductor deposition layer, and more particularly to a method for improving the surface of a semiconductor deposition layer in a shallow trench isolation (ST I) process. Flattening method. [Previous technology] In the modern society with rapid technological changes, various electronic products have become an indispensable part of the daily life of modern people. Generally speaking, electronic products are configured with different corresponding integrated circuits (lntegrated Circuit,
IC)，而i c係經由半導體製程將數以千萬計的電晶體、二 極體、電阻器及電容器等電路元件聚集於一單位體積僅數 平方公分大小之晶片（die)上，形成一完整之邏輯電路， 以達到控制、計算或記憶等功能，讓電子產品得以發揮其 功用並加以處理現代人之各種事務。 、IC), and IC is a semiconductor process that gathers tens of millions of circuit elements such as transistors, diodes, resistors, and capacitors on a die with a unit volume of only a few square centimeters. Logic circuit to achieve the functions of control, calculation or memory, so that electronic products can perform their functions and deal with various tasks of modern people. ,
一 請參照第1 A〜1 E圖，其繪示乃傳統之半導體製程中之 半導體沈積層之平坦化方法的流程剖面圖。首先，在第工A 圖中，提供一基材，基材例如是一晶圓（wafer)12，並形 成一墊氧化層於晶圓1 2上，墊氧化層例如是二氧化矽 (SiOO層14，如第1A圖所示。接著，形成一氮化矽（δίΛ) 層16於二氧化矽層14上，並形成一圖案化光阻層ΐ8於氮4化 矽層1 6上，如第丨β圖所示。然後，去除所暴露之氮化矽層 16及其下方之部分的二氧化矽層14，並接著去除部分之晶 圓1 2以形成數個淺溝渠（sha 11 ow trench) 1 9於晶圓1 2 中，如第1C圖所示。1. Please refer to FIGS. 1A to 1E, which are cross-sectional views showing the flow of a method for planarizing a semiconductor deposition layer in a conventional semiconductor process. First, in FIG. A, a substrate is provided. The substrate is, for example, a wafer 12, and a pad oxide layer is formed on the wafer 12. The pad oxide layer is, for example, a silicon dioxide (SiOO layer). 14, as shown in FIG. 1A. Next, a silicon nitride (δίΛ) layer 16 is formed on the silicon dioxide layer 14 and a patterned photoresist layer ΐ8 is formed on the silicon nitride layer 16 as shown in FIG.丨 β. Then, the exposed silicon nitride layer 16 and a portion of the silicon dioxide layer 14 below it are removed, and then a portion of the wafer 12 is removed to form several shallow trenches (sha 11 ow trench). 19 is in wafer 1 2 as shown in FIG. 1C.
200522164 五、發明說明（2) 待圖案化光阻層1 8被去除後，以一高密度電漿化學氣 相沈積法（High Density Plasma Chemical Vapor Deposition，HDP CVD)形成一半導體沈積層22於晶圓12之 上，如第1D圖所示。半導體沈積層2 2係覆蓋氮化矽層1 6， 並填滿此些淺溝渠20，半導體沈積層22例如是二氧化矽 (Si02)層。接著’以一化學機械研磨法（Chemical Mechanical Polishing，CMP)平坦化半導體沈積層22之表 面’即使用化學機械研磨機台研磨半導體沈積層22之表 面，使得半導體沈積層22之表面更加平整，如第1E圖所 示。 需要注意的是，由於第1D圖之半導體沈積層22上於覆 蓋氮化矽層16之處較覆蓋淺溝渠19處為高，且最高點及最 低點之間具有一高度差（step height)H，造成半導體沈積 層22之表面的不平整性报大。因此，為了提升化學機械研 磨製程的研磨均勻性（uniformity)，通常會採用研磨塾 (polish pad)，來進行化學機械研磨。不過，如此一來， 於ST I寬度較大的隔離地區，化學機械研磨機台容易對於 半導體沈積層22過度研磨，造成如第1E圖中所示的下凹、 17，產生盤凹（dishing)現象，影響半導體製程甚鉅。 以、，如何於淺溝渠隔離製程中增進半導體沈積層表面平坦 化並避免盤凹之現象，將是一個急需解決的技術課題。 【發明内容】 有鑑於此，本發明的目的就是在提供一種半導體沈積 200522164 五、發明說明（3) 層之平坦化方法，其形成一覆蓋層於該半導體沈積層表面 的設計，可以改善後續之化學機械研磨機台對於此半導體 沈積層的過度研磨。 根據本發明的目的，提出一種半導體沈積層之平坦化 方法。在此方法中，首先，提供基材。形成墊氧化層於基 材上，接著，形成氮化矽（Si3N4)層於墊氧化層上。然後， 形成多個淺溝渠（shal low trench)於基材中，再以高密度 電漿化學氣相沈積法（High Density Plasma Chemical Vapor Deposition，HDP CVD)形成半導體沈積層於基材之 上’半導體沈積層係覆蓋氮化石夕層，並填滿淺溝渠。之 後’形成覆蓋層於半導體沈積層之表面。再以化學機械研 磨法（Chemical Mechanical Polishing，CMP)平坦化半導 體沈積層之表面。 根據本發明的再一目的，提出一種半導體沈積層之平 坦化方法。在此方法中，首先，提供一晶圓。接著，形成 二氧化石夕層於該晶圓上。然後，形成氮化矽層於二氧化石夕 層上。接著，形成數個淺溝渠於晶圓中。接著，以高密度 電漿化學氣相沈積法形成半導體沈積層於晶圓之上，半導 體沈積層係覆蓋氮化矽層，並填滿此些淺溝渠。接著，形 成一南石夕氧化物（silicon-rich oxide，SR0)層於該半導 體沈積層之表面。然後，以化學機械研磨法平坦化半導體 沈積層之表面。 為讓本發明之上述目的、特徵、和優點能更明顯易 懂’下文特舉一較佳實施例，並配合所附圖式，作詳細說200522164 V. Description of the invention (2) After the patterned photoresist layer 18 is removed, a high density plasma chemical vapor deposition method (High Density Plasma Chemical Vapor Deposition, HDP CVD) is used to form a semiconductor deposition layer 22 on the crystal. Above circle 12, as shown in Figure 1D. The semiconductor deposition layer 22 covers a silicon nitride layer 16 and fills these shallow trenches 20. The semiconductor deposition layer 22 is, for example, a silicon dioxide (SiO2) layer. Then, 'the surface of the semiconductor deposition layer 22 is planarized by a chemical mechanical polishing (CMP)', that is, the surface of the semiconductor deposition layer 22 is polished using a chemical mechanical polishing machine, so that the surface of the semiconductor deposition layer 22 is more flat, such as Figure 1E. It should be noted that since the semiconductor deposition layer 22 shown in FIG. 1D is higher than the shallow trench 19 covering the silicon nitride layer 16, there is a step height H between the highest point and the lowest point. As a result, the unevenness of the surface of the semiconductor deposition layer 22 is increased. Therefore, in order to improve the polishing uniformity of the chemical mechanical grinding process, a polishing pad is usually used for chemical mechanical polishing. However, in this way, in the isolation area with a wide ST I width, the chemical mechanical polishing machine is prone to excessively grind the semiconductor deposition layer 22, causing depressions 17 and 17 as shown in FIG. 1E, resulting in dishing. This phenomenon has a huge impact on semiconductor processes. Therefore, how to improve the flatness of the surface of the semiconductor deposition layer and avoid the phenomenon of dishing in the shallow trench isolation process will be a technical problem that needs to be solved urgently. [Summary of the Invention] In view of this, the object of the present invention is to provide a semiconductor deposition method 200522164 V. Description of the Invention (3) A method for planarizing a layer, which forms a design of a cover layer on the surface of the semiconductor deposition layer, which can improve subsequent The CMP machine grinds the semiconductor deposited layer excessively. According to the object of the present invention, a method for planarizing a semiconductor deposited layer is proposed. In this method, first, a substrate is provided. A pad oxide layer is formed on the substrate, and then a silicon nitride (Si3N4) layer is formed on the pad oxide layer. Then, a plurality of shallow low trenches are formed in the substrate, and then a high density plasma chemical vapor deposition method (High Density Plasma Chemical Vapor Deposition (HDP CVD)) is used to form a semiconductor deposition layer on the substrate. The sedimentary layer covers the nitrided layer and fills shallow trenches. Thereafter, a cover layer is formed on the surface of the semiconductor deposition layer. Then the surface of the semiconductor deposited layer was planarized by chemical mechanical polishing (CMP). According to still another object of the present invention, a flattening method for a semiconductor deposited layer is proposed. In this method, first, a wafer is provided. Next, a SiO2 layer is formed on the wafer. Then, a silicon nitride layer is formed on the SiO2 layer. Then, several shallow trenches are formed in the wafer. Next, a high-density plasma chemical vapor deposition method is used to form a semiconductor deposition layer on the wafer. The semiconductor deposition layer is covered with a silicon nitride layer and fills these shallow trenches. Next, a silicon-rich oxide (SR0) layer is formed on the surface of the semiconductor deposition layer. Then, the surface of the semiconductor deposited layer is planarized by a chemical mechanical polishing method. In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible ', a preferred embodiment is given below in conjunction with the accompanying drawings for detailed description
200522164 五、發明說明（4) 明如下： 【實施方式】 本發明特別設計一半導體沈積層之平坦化方法，其形 成一覆蓋層於該半導體沈積層之表面的步驟，可以改善後 續之化學機械研磨機台對於此半導體沈積層的過度研磨。200522164 V. Description of the invention (4) The description is as follows: [Embodiment] The present invention specifically designs a method for planarizing a semiconductor deposition layer. The step of forming a cover layer on the surface of the semiconductor deposition layer can improve subsequent chemical mechanical polishing. The machine grinds the semiconductor deposited layer too much.
請同時參照第2圖及第3A〜3F圖，其中，第2圖繪示乃 依照本發明之較佳實施例之半導體沈積層的平坦化方法的 流程圖，而第3A〜3F圖繪示乃依照本發明之較佳實施例之 半導體沈積層的平坦化方法的流程剖面圖。首先，如步驟 202所述’提供一基材，基材例如是晶圓（wafer)312。接 著，如步驟204所述，形成一墊氧化層於晶圓312上，塾氧 化層例如是二氧化矽（S i 02 )層3 1 4，如第3 A圖所示。 然後’如步驟206所述，形成氮化矽（si3N4)層31 6於二 氧化矽層314上，並再形成一圖案化光阻層318於氮化矽層 316上’如第3B圖所示。 之後，如步驟208所述，去除所暴露之氮化矽層316及 其下方之部分的二氧化矽層314，並去除部分之晶圓312，Please refer to FIG. 2 and FIGS. 3A to 3F at the same time, wherein FIG. 2 shows a flowchart of a method for planarizing a semiconductor deposition layer according to a preferred embodiment of the present invention, and FIGS. 3A to 3F show A flow cross-sectional view of a method for planarizing a semiconductor deposition layer according to a preferred embodiment of the present invention. First, as described in step 202, a substrate is provided. The substrate is, for example, a wafer 312. Next, as described in step 204, a pad oxide layer is formed on the wafer 312. The hafnium oxide layer is, for example, a silicon dioxide (Si02) layer 3 1 4 as shown in FIG. 3A. Then, as described in step 206, a silicon nitride (si3N4) layer 316 is formed on the silicon dioxide layer 314, and a patterned photoresist layer 318 is formed on the silicon nitride layer 316, as shown in FIG. 3B. . After that, as described in step 208, the exposed silicon nitride layer 316 and a portion of the silicon dioxide layer 314 below it are removed, and a portion of the wafer 312 is removed.
以形成數個淺溝渠（shallow trench)319於晶圓312中，如 第3 C圖所示。 一接著’如步驟210所述，去除圖案化光阻層318，並以 一南密度電漿化學氣相沈積法（HDp CVD)形成一半導體沈 積層32 2於晶圓312上，半導體沈積層322係覆蓋氮化矽声 31 6，並填滿淺溝渠31 9，如第3D圖所示。其中，半導體沈A plurality of shallow trenches 319 are formed in the wafer 312, as shown in FIG. 3C. Next, as described in step 210, the patterned photoresist layer 318 is removed, and a semiconductor deposition layer 32 is formed on the wafer 312 by a South Density Plasma Chemical Vapor Deposition (HDp CVD) method, and the semiconductor deposition layer 322 is formed. It covers the silicon nitride sound 31 6 and fills the shallow trench 31 9, as shown in Figure 3D. Among them, the semiconductor sink
200522164 五、發明說明（5) 積層32 2例如是二氧化矽（Si02)層。在第3D圖中，半導體沈 積層32 2上於覆蓋氮化矽層316之處較覆蓋淺溝渠319處為 高，且最高點及最低點之間具有一高度差（step height) Η 〇 然後，如步驟212所述，形成覆蓋層324於半導體沈積 層322之表面，如第3Ε圖所示。覆蓋層324係由高矽氧化物 (silicon-rich oxide，SR0)所組成，而形成覆蓋層32 4之 方法較佳地使用包括石夕曱院（s i 1 ane，S i H4 )、氧化亞氮 (nitrous oxygen，N20)與氦（he 1 ium，He)等氣體，以高密 度電漿化學氣相沈積法（HDP CVD)形成此覆蓋層324於半導 體沈積層322上。 最後，如步驟214所述，以化學機械研磨法（Chemi cal200522164 V. Description of the invention (5) The laminated layer 32 2 is, for example, a silicon dioxide (Si02) layer. In the 3D diagram, the semiconductor deposition layer 32 2 is higher in the place where the silicon nitride layer 316 is covered than in the place where the shallow trenches 319 are covered, and there is a step height between the highest point and the lowest point. Then, As described in step 212, a cover layer 324 is formed on the surface of the semiconductor deposition layer 322, as shown in FIG. 3E. The cover layer 324 is composed of silicon-rich oxide (SR0), and the method for forming the cover layer 32 4 preferably includes si 1 ane, Si H 4, and nitrous oxide. (Nitrous oxygen, N20) and helium (he 1 ium, He) and other gases are formed on the semiconductor deposition layer 322 by a high-density plasma chemical vapor deposition (HDP CVD) method. Finally, as described in step 214, the chemical mechanical polishing method (Chemi cal
Mechanical Polishing，CMP)平坦化半導體沈積層322的 表面。在使用化學機械研磨機台研磨的同時，注入一研磨 液’研磨液中包括例如是二氧化鈽（Ceriuin dioxide，Mechanical Polishing (CMP) planarizes the surface of the semiconductor deposition layer 322. While using a chemical mechanical polishing machine to grind, a polishing liquid is injected. The polishing liquid includes, for example, cerium oxide (Ceriuin dioxide,
Ce〇2 ) ’以增進研磨的效果。當使用化學機械研磨機台研磨 時’等平面地依序去除覆蓋層324及部分半導體沈積層 322 ’直到暴露出氮化石夕層316的表面，便停止研磨，如第 3F圖所示。 在此’由覆蓋層324與氮化矽層316構成之多層構造之 研磨終止層（polish stop layer)，由於覆蓋層324之材質 係較二氧化矽還堅硬之高矽氧化物（SR〇 )，在相同的化學 機械研磨時間下’SR0之移除速率（rem〇vai『ate，R.R·) 會比一氧化石夕之移除速率要小。因此，本發明採用具有多Ce〇2) 'to improve the effect of polishing. When using a chemical mechanical polishing machine, the cover layer 324 and a part of the semiconductor deposition layer 322 ′ are sequentially removed in equal plane until the surface of the nitrided layer 316 is exposed, as shown in FIG. 3F. Here, the polishing stop layer of a multilayer structure composed of a cover layer 324 and a silicon nitride layer 316, because the material of the cover layer 324 is a high silicon oxide (SR0), which is harder than silicon dioxide, Under the same CMP time, the removal rate of SR0 (removai'ate, RR ·) will be lower than the removal rate of monoxide. Therefore, the present invention uses
TW1272F(旺宏）.ptd 第10頁 200522164 五、發明說明（6) 本發明上述實施例所揭露 法，其形成一覆蓋層於該半導 有效減少盤凹現象，有利於改 對於此半導體沈積層的過度研 層構造之研磨終止層，對於控制化學機械研磨之時間長短 與決定何時停止研磨之時間點，會比習知之使用單一氮化 石夕層來作為研磨終止層時，可具有較佳的掌握性。 綜上所述，雖然本發明 然其並非用以限定本發明， 本發明之精神和範圍内，當 本發明之保護範圍當視後附 準。 之半導體沈積層的平坦化方 體沈積層表面的設計，可以 善後續之化學機械研磨機台 磨之現象。 Ό 已以一較佳實施例揭露如上， 任何熟習此技藝者，在不脫離 可作各種之更動與潤飾，因此 之申請專利範圍所界定者為TW1272F (Wang Hong) .ptd Page 10 200522164 V. Description of the invention (6) The method disclosed in the above embodiment of the present invention, which forms a cover layer on the semiconductor to effectively reduce the dishing phenomenon, and is beneficial to the semiconductor deposition layer. The polishing termination layer of the over-layered layer structure has a better grasp of controlling the length of chemical mechanical polishing and the time point when deciding when to stop polishing, compared to the conventional use of a single nitrided layer as the polishing termination layer. Sex. In summary, although the present invention is not intended to limit the present invention, within the spirit and scope of the present invention, the scope of protection of the present invention shall be deemed to be approved after being considered. The design of the surface of the planarized semiconductor deposition layer of the semiconductor deposition layer can improve the subsequent grinding of the CMP machine. Ό It has been disclosed above with a preferred embodiment. Any person skilled in this art can make various modifications and retouching without departing. Therefore, the scope of the patent application is defined as
200522164__ 圖式簡單說明 【圖式簡單說明】 第1A〜1E圖繪示乃傳統之半導體製程中之半導體沈積 層之平坦化方法的流程剖面圖。 第2圖繪示乃依照本發明之較佳實施例之半導體沈積 層的平坦化方法的流程圖。 第3 A〜3 F圖繪示乃依照本發明之較佳實施例之半導體 沈積層的平坦化方法的流程剖面圖。 圖式標號說明 1 2、31 2 :晶圓 1 4、3 1 4 :二氧化矽層 1 6、31 6 :氮化矽層 1 7、31 7 ··下凹 18、318 :圖案化光阻層 1 9、31 9 :淺溝渠 22、322 :半導體沈積層 324 :覆蓋層200522164__ Brief description of the drawings [Simplified description of the drawings] Figures 1A to 1E show cross-sectional views of a process for planarizing a semiconductor deposition layer in a conventional semiconductor process. FIG. 2 shows a flowchart of a method for planarizing a semiconductor deposited layer according to a preferred embodiment of the present invention. Figures 3A to 3F are cross-sectional views showing the flow of a method for planarizing a semiconductor deposition layer according to a preferred embodiment of the present invention. Description of figure numbers 1 2 and 31 2: Wafer 1 4 and 3 1 4: Silicon dioxide layer 1 6 and 31 6: Silicon nitride layer 1 7 and 31 7 · Down 18 and 318: Patterned photoresist Layers 19, 31 9: Shallow trenches 22, 322: Semiconductor deposition layer 324: Cover layer
TW1272F(旺宏）.ptd 第12頁TW1272F (Wanghong) .ptd Page 12
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| TWI755313B (en) * | 2020-04-17 | 2022-02-11 | 大陸商北京北方華創微電子裝備有限公司 | Graphics chip, semiconductor intermediate product and hole etching method |
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| TWI755313B (en) * | 2020-04-17 | 2022-02-11 | 大陸商北京北方華創微電子裝備有限公司 | Graphics chip, semiconductor intermediate product and hole etching method |
| US12106970B2 (en) | 2020-04-17 | 2024-10-01 | Beijing Naura Microelectronics Equipment Co., Ltd. | Pattern sheet, semiconductor intermediate product, and hole etching method |
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