200529389 五、發明說明（1) 發明所屬之技術領域 本發明是有關於一種晶片封裝結構，且特別是有關 於一種具有散熱片之晶片封裝結構。 先前技術 就常見之打線接合（w i r e b 〇 n d i n g )型態之晶片封 裝結構而言，導線架（lead frame) —直是低腳位（low pin count)半導體元件常用的構裝元件。由於導線架具 有成本低，加工容易等特性，也是消費性電子產品常用 之晶片封裝類型，例如手機、電腦、視聽產品所使用之 半導體元件。為了因應南功率之半導體元件的散熱需 求，習知技術通常是利用大面積之散熱片來增加晶片之 散熱效能，使得晶片於運作時所產生的熱能，能夠很快 地傳導到高導熱之散熱片，並散逸至外界之大氣環境 中，以確保晶片能在正常之工作溫度下運作。 請參考第1圖，其繪示習知一種晶片封裝結構的剖面 示意圖。就打線接合型態之晶片封裝結構1 0 0而言，晶片 封裝結構100主要係由一晶片座（die pad ) 110、多數個 引腳1 1 6、一晶片1 2 0 、多條導線1 2 8、一散熱片1 3 0以及 一封膠1 4 0所構成。晶片1 2 0具有一主動表面1 2 2及對應之 一背面1 2 4 ，且晶片1 2 0之背面1 2 4經由一膠料層1 4 2而貼 附至晶片座1 1 0之承載表面1 1 2上。晶片1 2 0更具有多數個 銲塾（ponding pad) 126，其配置於晶片120之主動表面 1 2 2。此外，這些導線1 2 8則分別電性連接銲墊1 2 6之一至 其所對應之引腳1 1 6之一。散熱片1 3 0例如為導熱性佳之200529389 V. Description of the invention (1) Field of the invention The present invention relates to a chip packaging structure, and more particularly to a chip packaging structure with a heat sink. In the prior art, in terms of a common wafer packaging structure of a wire bonding type, a lead frame is a structural component commonly used for low pin count semiconductor components. Due to the characteristics of low cost and easy processing, lead frames are also commonly used in consumer electronics products, such as semiconductor components used in mobile phones, computers, and audiovisual products. In order to respond to the heat dissipation requirements of semiconductor components of South Power, the conventional technology usually uses a large area heat sink to increase the heat dissipation efficiency of the chip, so that the heat generated by the chip during operation can be quickly transferred to the high heat dissipation heat sink And dissipate to the outside atmosphere to ensure that the chip can operate at normal operating temperature. Please refer to FIG. 1, which is a schematic cross-sectional view showing a conventional chip package structure. As far as the wire bonding type chip packaging structure 100 is concerned, the chip packaging structure 100 is mainly composed of a die pad 110, a plurality of pins 1 1 6, a chip 1 2 0, and a plurality of wires 1 2 8. A heat sink 1300 and a glue 1400. The wafer 1 2 0 has an active surface 1 2 2 and a corresponding back surface 1 2 4, and the back surface 1 2 4 of the wafer 1 2 0 is attached to the bearing surface of the wafer holder 1 1 0 through a glue layer 1 4 2 1 1 2 on. The wafer 1 2 0 further has a plurality of bonding pads 126, which are arranged on the active surface 1 2 2 of the wafer 120. In addition, these wires 1 2 8 are respectively electrically connected to one of the solder pads 1 2 6 to one of its corresponding pins 1 1 6. The heat sink 1 3 0 is, for example, a material having good thermal conductivity.
12310TWF.PTD 第8頁 200529389 五、發明說明（2) 金屬塊，而散熱片130具有一接合面132，且散熱塊130之 接合面132可經由另一膠料層144，而貼附至晶片座110之 底面1 1 4。最後，封膠1 6 0則包覆晶片座1 1 0、引腳1 1 6之 内部、晶片1 2 0 、導線1 2 8以及散熱片1 3 0 。其中，引腳 1 1 6之外側可經由剪切成形而外露於封膠1 4 0之外，且散 熱片130之底面134還可選擇性暴露於封膠之外。 值得注意的是，散熱片1 3 0之接合面1 3 2與晶片座1 1 0 之底面1 1 4未直接接觸，而是間接藉由膠材層1 4 4而彼此 貼合。然而，膠材層1 4 4會增加晶片座1 1 0傳導至散熱片 1 3 0之熱阻抗，使得晶片1 2 0所產生的熱能無法快速地經 由散熱片1 3 0而散逸到外界大氣中，導致晶片封裝結構 1 0 0的熱能居高不下。 解決上述膠料層144之導熱不佳的方法之一，即是直 接將散熱片1 3 0之接合面1 3 2接觸晶片座1 1 0之底面1 1 4， 並以封膠1 4 0加以包覆。在理想狀態下，散熱片1 3 0之接 合面1 3 2與晶片座1 1 0之底面1 1 4可緊密接合，但是由於散 熱片1 3 0與晶片座1 1 0之間缺少膠料層1 4 4之貼合效果，受 熱而膨脹的封膠1 4 0會加大晶片座1 1 0與散熱片1 3 0之間的 間隙。此外，在材質上，封膠140之熱膨脹係數（CTE ) 與散熱片130之熱膨脹係數（CTE)不匹配（dismatch )，兩者受到反覆熱涨冷縮的作用而產生脫層，進而加 大晶片座1 1 0與散熱片1 3 0之間的間隙。因此，如何在不 使用膠料層1 4 4之情況下，能增加散熱片1 3 0與晶片座1 1 0 之間的接觸緊密度，乃本發明之重點。12310TWF.PTD Page 8 200529389 V. Description of the invention (2) Metal block, and the heat sink 130 has a joint surface 132, and the joint surface 132 of the heat sink block 130 can be attached to the wafer holder through another glue layer 144. The bottom surface of 110 1 1 4. Finally, the sealing compound 160 covers the inside of the chip holder 110, the pins 1 16, the chip 1 2 0, the wires 1 2 8 and the heat sink 1 3 0. The outer side of the pins 1 1 6 can be exposed to the outside of the sealant 140 through cutting and forming, and the bottom surface 134 of the heat sink 130 can be selectively exposed to the outside of the sealant. It is worth noting that the bonding surface 1 32 of the heat sink 130 and the bottom surface 1 1 4 of the wafer holder 1 10 are not in direct contact, but are indirectly attached to each other by the adhesive material layer 1 4 4. However, the adhesive layer 1 4 4 will increase the thermal resistance of the chip holder 1 10 to the heat sink 130, so that the thermal energy generated by the chip 120 cannot be quickly dissipated to the outside atmosphere through the heat sink 130. As a result, the thermal energy of the chip package structure 100 remains high. One of the methods to solve the poor thermal conductivity of the rubber layer 144 is to directly contact the joint surface 1 3 2 of the heat sink 1 3 0 with the bottom surface 1 1 4 of the chip holder 1 1 and apply the sealant 1 4 0 Wrapped. In an ideal state, the joint surface 1 3 2 of the heat sink 1 3 0 and the bottom surface 1 1 4 of the wafer holder 1 1 4 can be tightly connected, but because of the lack of a rubber layer between the heat sink 1 3 0 and the wafer holder 1 1 0 For the bonding effect of 1 4 4, the heat-swelling sealant 1 4 0 will increase the gap between the chip holder 1 1 0 and the heat sink 1 3 0. In addition, in terms of material, the coefficient of thermal expansion (CTE) of the sealant 140 and the coefficient of thermal expansion (CTE) of the heat sink 130 do not match, and the two are delaminated due to repeated thermal expansion and contraction, which increases the chip. The gap between the base 1 1 0 and the heat sink 1 3 0. Therefore, how to increase the contact tightness between the heat sink 130 and the wafer holder 110 without using the rubber layer 1 44 is the focus of the present invention.
12310TWF.PTD 第9頁 200529389 五、發明說明（3) 發明内容 因此，本發明的目的就是在提供一種晶片封裝結 構，在不使用膠料層之情況下，能增加晶片座與散熱片 之間的接觸緊密度。 為達本發明之上述目的，本發明提出一種晶片封裝 結構，主要係由一導線架、一晶片、多數個導線、一散 熱片、一封膠以及一膨脹體所構成。導線架具有一晶片 座以及多數個引腳，而晶片配置於晶片座上，且導線電 性連接晶片之銲墊與對應之引腳。此外，散熱片配置於 導線架之底面，而封膠包覆晶片座、引腳内側、晶片、 導線以及散熱片，且封膠具有一開口 ，其暴露出散熱片 之局部底面。另外，膨脹體配置於散熱片之底面，並容 納於開口中。 依照本發明的較佳實施例所述，上述之膨脹體之熱 膨脹係數較佳係大於散熱片之熱膨脹係數，並且還大於 封膠之熱膨脹係數，而膨脹體之材質例如為環氧樹脂， 而受熱膨脹之環氧樹脂能改善晶片座與散熱片之間接觸 緊密度，以提高晶片封裝結構之散熱效能。 由於本發明採用熱膨脹係數高的環氧樹脂作為膨脹 體，而膨脹體受熱膨脹之後可推擠散熱片，以使散熱片 與晶片座緊密接觸。因此在未使用膠料層之情況下，膨 脹體可減少晶片座與散熱片之間的間隙，進而提高晶片 座與散熱片之間的接觸緊密度。 為讓本發明之上述和其他目的、特徵、和優點能更12310TWF.PTD Page 9 200529389 V. Description of the invention (3) Summary of the invention Therefore, the object of the present invention is to provide a chip packaging structure that can increase the distance between the chip holder and the heat sink without using a rubber layer. Contact tightness. In order to achieve the above object of the present invention, the present invention proposes a chip package structure, which is mainly composed of a lead frame, a chip, a plurality of wires, a heat sink, an adhesive, and an expanded body. The lead frame has a chip holder and a plurality of pins, and the chip is arranged on the chip holder, and the wires are electrically connected to the pads of the chip and the corresponding pins. In addition, the heat sink is disposed on the bottom surface of the lead frame, and the sealant covers the chip holder, the inside of the pins, the chip, the wires, and the heat sink, and the sealant has an opening that exposes a partial bottom surface of the heat sink. In addition, the expansion body is disposed on the bottom surface of the heat sink and is accommodated in the opening. According to a preferred embodiment of the present invention, the thermal expansion coefficient of the above-mentioned expansion body is preferably larger than the thermal expansion coefficient of the heat sink, and also larger than the thermal expansion coefficient of the sealant, and the material of the expansion body is, for example, epoxy resin, and is subject to Thermal expansion epoxy can improve the contact tightness between the chip holder and the heat sink to improve the heat dissipation performance of the chip package structure. Because the present invention uses an epoxy resin with a high thermal expansion coefficient as the expansion body, the thermal expansion fin can be pushed after the expansion body is heated to make the thermal fin contact the wafer holder closely. Therefore, without using a rubber layer, the expansion body can reduce the gap between the wafer holder and the heat sink, thereby improving the contact tightness between the wafer holder and the heat sink. In order to make the above and other objects, features, and advantages of the present invention more comprehensible
12310TWF.PTD 第10頁 200529389 五、發明說明（4) 明顯易懂，下文特舉一較佳實施例，#耐人〜^丄 4 亚配合所附圖式， 作詳細說明如下： 實施方式 · 請參考第2圖’其繪示本發明一較佳實施例之一種晶 片封裝結構的剖面示意圖。就打線接合型熊之曰 結構2 0 0而言，晶片封裝結構2 0 0主要係由二晶 多數個引腳216 、一晶片2 2 0 、多條導線228、一 ^孰 2 3 0、一封膠2 4 0以及一膨脹體2 5 0所構成。晶片=〇、、'/ 一主動表面2 2 2及對應之一背面2 2 4，而晶片22〇之背面 224經由一膠料層2 4 2而貼附至晶片座22〇之承載表面21 2 上’且晶片220之主動表面222配置有多數個銲塾Mg，分 別對應於這些引腳216。另外，導線228電性連接晶片22〇 之銲塾2 2 6與對應之引腳216，而導線228之材質例如為 金。再者’散熱片230配置於晶片座21〇之底面214，且散 熱片2 3 0係為熱傳導能力佳的金屬，例如銅或鋁。 同樣請參考第2圖，封膠2 4 0例如以模六（cavi ty ) 充填的方式而將晶片座210、引腳216内側、晶片220、導 線2 2 8以及散熱片2 3 0加以包覆，以保護晶片2 2 0，並避免 外界之濕度影響與雜塵污染，而引腳2 1 6外側可經由剪切 成形而外露於封膠1 4 0之外。在本實施例中，封膠2 4 0具 有一開口 244，其暴露出散熱片230之局部底面232，而膨 脹體2 5 0容納於開口244中。由於晶片座210之底面214與 散熱片2 3 0直接接觸，以使晶片2 2 0所產生之熱能能傳導 至大面積之散熱片2 3 0，以加快晶片2 2 0散熱之效能。12310TWF.PTD Page 10 200529389 V. Description of the invention (4) Obviously easy to understand. The following gives a preferred embodiment, # 耐人 〜 ^ 丄 4 sub-matching with the attached drawings, detailed description is as follows: Implementation mode · Please Referring to FIG. 2, a schematic cross-sectional view of a chip packaging structure according to a preferred embodiment of the present invention is shown. As far as the wire-bonding type bear structure 2 0 is concerned, the chip package structure 2 0 is mainly composed of a plurality of pins 216 of the two crystals, a chip 2 2 0, a plurality of wires 228, a ^ 孰 2 3 0, a The sealant 2 4 0 and an expanded body 2 50 are formed. Wafer = 0,, / 'an active surface 2 2 2 and a corresponding one of the back surface 2 2 4, and the back surface 224 of the wafer 22 0 is attached to the bearing surface 21 2 of the wafer holder 22 0 through a glue layer 2 4 2. And the active surface 222 of the chip 220 is configured with a plurality of solder pads Mg, corresponding to the pins 216, respectively. In addition, the wire 228 is electrically connected to the solder pad 2 2 6 of the chip 22 and the corresponding pin 216, and the material of the wire 228 is, for example, gold. In addition, the heat sink 230 is disposed on the bottom surface 214 of the wafer holder 21, and the heat sink 230 is a metal having a high thermal conductivity, such as copper or aluminum. Please also refer to FIG. 2. The sealing compound 2 4 0 covers the chip holder 210, the inside of the pins 216, the chip 220, the wires 2 2 8, and the heat sink 2 3 0 in a mold filling manner, for example. In order to protect the chip 2 2 0 and avoid the influence of external humidity and dust pollution, the outside of the pin 2 1 6 can be exposed to the outside of the sealant 1 4 0 through shear forming. In this embodiment, the sealant 240 has an opening 244 that exposes a partial bottom surface 232 of the heat sink 230, and the expanded body 250 is received in the opening 244. Since the bottom surface 214 of the chip holder 210 is in direct contact with the heat sink 230, the heat energy generated by the chip 220 is transferred to the large-area heat sink 230, so as to accelerate the heat dissipation performance of the chip 220.
12310TWF.PTD 第11頁 200529389 五、發明說明（5) 值得注意的是，晶片座210之底面214與散熱片230之 間並未藉由習知之膠材層而貼合，以減少習知膠材層所 產生之熱阻抗。然而，在未使用膠材層之情況下，本實 施例係將膨脹體2 4 4配置於散熱片2 3 0之底面2 3 2，並容納 於封膠2 4 0所預留之開口 2 4 4中，其中膨脹體2 5 0之材質例 如為膨脹係數高之環氧樹脂（e ρ ο X y r e s i η )，其熱膨脹 係數較佳係大於散熱片2 3 0之熱膨脹係數。舉例而言，散 熱片2 3 0之材質例如為鋁，其熱膨脹係數約為23· 2ppm/ °C。膨脹體2 5 0之材質例如為熱膨脹係數高之環氧樹脂， 其熱膨脹係數可在82〜171ppm/°C範圍中，約為散熱片 2 3 0之熱膨脹係數的四倍或更高。此外，封膠2 4 0之熱膨 脹係數約在9〜34ppm/ °C範圍中，亦小於膨脹體2 5 0之熱 膨脹係數。 請同時參考第2及3圖，其中第3圖繪示晶片座與散熱 片之間的間隙（以負值表示）與相對位置的比較關係 圖。經由模擬分析實驗得知的比較關係圖可知，圖中之 實線S 1繪示在未使用膠料層之情況下，晶片座2 1 0與散 熱片2 3 0之間的間隙G 1受到封膠2 4 0熱膨脹的作用以及散 熱片2 3 0與封膠2 4 0之熱膨脹係數不匹配的影響，其最大 間隙值將大於2 0微米。另外，圖中之實線S 2繪示當配置 膨脹體250於散熱片230之底面232時，膨脹體250受熱膨 脹之後，膨脹體2 5 0的變形量大於散熱片2 3 0之變形量， 故膨脹體2 5 0可推擠散熱片2 3 0，以減少晶片座2 1 0與散熱 片2 3 0之間的間隙G 2 ，其最大值約為2微米左右。12310TWF.PTD Page 11 200529389 V. Description of the invention (5) It is worth noting that the bottom surface 214 of the chip holder 210 and the heat sink 230 are not bonded by the conventional adhesive material layer to reduce the conventional adhesive material. The thermal impedance generated by the layer. However, in the case where no glue layer is used, the present embodiment is that the expansion body 2 4 4 is arranged on the bottom surface 2 3 2 of the heat sink 2 3 0 and accommodated in the opening 2 4 reserved by the sealant 2 4 0 In 4, the material of the expansion body 250 is, for example, an epoxy resin with a high expansion coefficient (e ρ ο X yresi η), and the thermal expansion coefficient thereof is preferably larger than the thermal expansion coefficient of the heat sink 2 300. For example, the material of the heat sink 2 30 is, for example, aluminum, and its thermal expansion coefficient is about 23.2 ppm / ° C. The material of the expansion body 250 is, for example, an epoxy resin having a high thermal expansion coefficient, and its thermal expansion coefficient can be in the range of 82 to 171 ppm / ° C, which is about four times or more than the thermal expansion coefficient of the heat sink 2 300. In addition, the thermal expansion coefficient of the sealant 24 is in the range of 9 to 34 ppm / ° C, which is also smaller than the thermal expansion coefficient of the expansion body 250. Please refer to Figures 2 and 3 at the same time. Figure 3 shows the relationship between the gap between the wafer holder and the heat sink (represented by a negative value) and the relative position. The comparison relationship graph obtained through simulation analysis experiments shows that the solid line S 1 in the figure shows that the gap G 1 between the chip holder 2 1 0 and the heat sink 2 3 0 is sealed without using a rubber layer. The effect of the thermal expansion of the glue 2 40 and the mismatch of the thermal expansion coefficients of the heat sink 2 300 and the sealing glue 2 40 will have a maximum gap value greater than 20 microns. In addition, the solid line S 2 in the figure shows that when the expansion body 250 is disposed on the bottom surface 232 of the heat sink 230, the expansion body 250 has a larger deformation amount than the heat sink 280 after the expansion body 250 expands due to heat. Therefore, the expansion body 250 can push the heat sink 2 30 to reduce the gap G 2 between the chip holder 2 10 and the heat sink 2 3 0, and the maximum value is about 2 microns.
12310TWF.PTD 第12頁 200529389 五、發明說明（6) 由以上的比較關係圖可知，在未使用膠料層之情況 下，利用膨脹體2 5 0可減少晶片座2 1 0與散熱片2 3 0之間的 間隙，進而提高晶片座2 1 0與散熱片2 3 0之間的接觸緊密 度。因此，晶片2 2 0所產生之熱能，能快速地經由晶片座 210傳導至散熱片230 ，以提高晶片220之散熱效能。 綜上所述，本發明之晶片封裝結構，係採用熱膨脹 係數高的膠體作為膨脹體，例如為環氧樹脂等膠體，而 膨脹體之熱膨脹係數大於散熱片之熱膨脹係數，且膨脹 體係配置於散熱片之底面，並容納於封膠所預留之開口 中。當膨脹體受熱膨脹之後可推擠散熱片，以使散熱片 與晶片座緊密接觸。因此，在未使用膠料層之情況下， 膨脹體可減少晶片座與散熱片之間的間隙，進而提高晶 片座與散熱片之間的接觸緊密度。 雖然本發明已以一較佳實施例揭露如上，然其並非 用以限定本發明，任何熟習此技藝者，在不脫離本發明 之精神和範圍内，當可作些許之更動與潤飾，因此本發 明之保護範圍當視後附之申請專利範圍所界定者為準。12310TWF.PTD Page 12 200529389 V. Explanation of the invention (6) From the above comparison diagram, it can be seen that the use of the expansion body 2 5 0 can reduce the chip holder 2 1 0 and the heat sink 2 3 without using a rubber layer. The gap between 0 further improves the contact tightness between the wafer holder 2 1 0 and the heat sink 2 3 0. Therefore, the thermal energy generated by the wafer 220 can be quickly conducted to the heat sink 230 through the wafer holder 210 to improve the heat radiation performance of the wafer 220. In summary, the chip packaging structure of the present invention uses a colloid with a high thermal expansion coefficient as an expansion body, such as an epoxy resin, and the thermal expansion coefficient of the expansion body is greater than the thermal expansion coefficient of the heat sink, and the expansion system is configured for heat dissipation The bottom surface of the sheet is accommodated in the opening reserved by the sealant. When the expansion body is heated and expanded, the heat sink can be pushed to bring the heat sink into close contact with the wafer holder. Therefore, without using a rubber layer, the expanded body can reduce the gap between the wafer holder and the heat sink, thereby improving the contact tightness between the wafer holder and the heat sink. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make some changes and retouch without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application.
12310TWF.PTD 第13頁 200529389 圖式簡單說明 第1圖繪示習知一種晶片封裝結構的剖面示意圖。 第2圖繪示本發明一較佳實施例之一種晶片封裝結構 的剖面示意圖。 第3圖繪示晶片座與散熱片之間的間隙與相對位置的 比較關係圖。 【圖式標示說明】 1 0 0、2 0 0 :晶片封裝結構 1 1 0 、2 1 0 :晶片座 1 1 2、2 1 2 :承載表面 1 14、214 :底面 116、216 :引腳 120 、2 2 0 ：晶片 122、222 :主動表面 1 2 4 、2 2 4 :背面 1 2 6、2 2 6 :銲墊 1 2 8、2 2 8 :導線 1 3 0 、2 3 0 :散熱片 1 3 2 :接合面 1 34、2 3 2 :底面 1 4 0、2 4 0 :封膠 1 4 2、1 4 4 :膠料層 2 4 2 :膠料層 244 ：開口 2 5 0 :膨脹體12310TWF.PTD Page 13 200529389 Brief Description of Drawings Figure 1 shows a schematic cross-sectional view of a conventional chip package structure. FIG. 2 is a schematic cross-sectional view of a chip packaging structure according to a preferred embodiment of the present invention. Fig. 3 is a diagram showing a comparison relationship between a gap and a relative position between a wafer holder and a heat sink. [Illustration of Graphical Symbols] 1 0 0, 2 0 0: Chip package structure 1 1 0, 2 1 0: Chip holder 1 1 2, 2 1 2: Carrying surface 1 14, 214: Bottom surface 116, 216: Pin 120 , 2 2 0: Wafers 122, 222: Active surface 1 2 4, 2 2 4: Back surface 1 2 6, 2 2 6: Pads 1 2 8, 2 2 8: Wires 1 3 0, 2 3 0: Heat sink 1 3 2: Joint surface 1 34, 2 3 2: Bottom surface 1 4 0, 2 4 0: Sealant 1 4 2, 1 4 4: Rubber layer 2 4 2: Rubber layer 244: Opening 2 5 0: Swell body
12310TWF.PTD 第14頁12310TWF.PTD Page 14