TW200416984A - Substrate with embedded passive components and method for fabricating the same - Google Patents

Abstract

A substrate with embedded passive components and a method for fabricating the substrate are proposed. At least a first unit circuit board is formed with circuit layers on upper and lower surfaces thereof. Conductive metal layers with a capacitor film and a resistor film separated from the first united circuit board by an insulating layer are mounted on the circuit layers of the first unit circuit board. After patterning the conductive metal layer and resistor film formed thereon, at least an opening is formed to penetrate the first unit circuit board. At least a second unit circuit board is formed with circuit layers separated from one to another by an insulating layer and electrically connected to each other via a plurality of conductive vias and blind vias formed in the second unit circuit board. The first and second unit circuit boards are integrated to form at least an indentation via the opening of the first unit circuit board which was covered by the second unit circuit board. A plurality of PTH was formed to penetrate the unit circuit boards in order to electrically connect at least one of the circuit layers formed on the surface of the capacitor film and the resistor film.

Description

-----.-- V. Description of the invention (1) [Technical field to which the invention belongs] The Qiming system is related to _ 绿 主 墓 Ｍ 壮 #, especially a kind of base plate and its manufacturing method Said chip and other + +: a semiconductor package substrate with passive components and semiconductors embedded in the layered circuit board structure and a manufacturing method thereof. • L-first technology] Energy, ϊ Ξ :: the booming development of the industry, 胄 products are gradually moving into multi-function (丨 this, research and development direction. To meet the needs of semiconductor packaging high accumulation degree, ΓΓ ^ Γ) and micro Miniaturization package / printed circuit board (Printed ard) for β and Xi number lines has also gradually evolved from a single-layer board to a multi-layer board connection (^ ΓΓ Board), in a limited space, By interlayer layer + nte ^ ayei · Connection) to expand the area of the private circuit on the printed circuit board to match the high-density integrated circuit components on the tCU (seven) required *. On the same day, the semiconductor package also needs to have resistors (Resistors), capacitors (Capacitors), and tellurium nd +, 口 口-# 次 σσ Unductors (PasSlVe corap: r⑽) Refined, relatively lifted or stabilized. No. Most passive components 12 are placed on the US board. | The 'f' board can be the meaning of ordinary printed circuit boards or semiconductor wafers, but to avoid such passive The component i 2 is electrically connected to the ground plane, and the passive component M is placed at the corner of the substrate i. Traditionally, the pure amount outside these areas is often connected.

17098. ptd Page 8 200416984 V. Description of the invention (2) We need to consider the position of the solder pads, which leads to the limitation of the number of these passive components 12. The development trend of the integration of semiconductors southward is not favorable; The number of component 12 layouts has increased relatively with the high performance requirements of semiconductor packages. For example, the surface of substrate 1 must accommodate most semiconductor wafers 11 and a large number of passive components 12 at the same time, forcing the volume of the package to increase. Large, does not meet the development trend of thin and light semiconductor packages. As shown in FIG. 2, based on the above-mentioned problems, it is conceived to integrate the majority of the passive elements into a region between the semiconductor wafer 21 and the soldering region on the substrate 2. However, as the number of output / input connections per unit area in a semiconductor device increases, the number of bonding wires 2 3 also increases; further, the height of the passive component 22 (about 0.8 mm) is generally higher than that of the semiconductor wafer 2 1 height (approximately 0.55 mm), if you want to prevent the welding wire 2 3 from touching the passive component 2 2 to cause a short circuit, make the welding wire 23 need to be pulled up and cross the passive component 22 directly above it to increase the welding difficulty , Which also increases the length of the line arc (Wire 1 00p). Moreover, the welding wire 2 3 itself has weight. If the high welding wire 2 3 lacks support, it is easy to cause a short circuit due to its own gravity collapse to touch the passive components, and the welding wire 2 3 itself is made of gold and aluminum. The length will significantly increase the cost of the welding wire. / Furthermore, the passive component 2 2 is fixed to the substrate 2 with a soldering adhesive (S ο 1 derpaste) using a conventional surface bonding technology (Surface-m ountingtech η o 1 ogy, S M T). After the preset soldering position, when the colloidal packaging process of the semiconductor device is performed, the molten packaging resin 2 4 is injected under a high temperature environment. At this time, the operating temperature (175 ° C) and the soldering adhesive used for the passive component 2 2 are fixedly connected. The melting temperature (183t :) is close, the solder is in a semi-melted softened state, and Gu Yi causes the passive components 22 to be subjected to the molten encapsulating resin 24 after the injection.

17098.ptd Page 9 200416984 V. Description of the invention (3) Mo 1 d f 1 ow stress impact, which causes the passive components 22 to deviate from the preset welding position, lowering the conductive quality and even causing a short circuit. In addition, in the current trend of electronic products requiring thinness, shortness, versatility, and high electrical properties, relatively speaking, the semiconductor packaging units placed within them are bound to follow the requirements of lightness, shortness, and miniaturization. Therefore, how to provide an effective number of passive components and semiconductors Electronic components such as wafers are used in semiconductor packaging substrates to improve the electrical functions of electronic products without affecting the layout of the semiconductor packaging substrate and the increase in the overall thickness of the semiconductor package. This is a problem that needs to be solved at present. _Summary of the Invention In view of the shortcomings of the conventional technologies described above, the main purpose of the present invention is to provide a semiconductor package substrate with embedded passive components and a method for manufacturing the same, to increase the number of passive components in a semiconductor device and increase the substrate. Line layout flexibility. Another object of the present invention is to provide a semiconductor package substrate with embedded passive components and a method for manufacturing the same, which can reduce the surface area of the substrate and the thickness of the semiconductor package to achieve the goal of lightness, thinness and shortness of the semiconductor device. ~, Another object of the present invention is to provide a semiconductor package substrate with embedded passive components and a manufacturing method thereof, so as to avoid the passive components from being biased due to the high temperature and the mold flow φ, and at the same time reduce the welding difficulty, avoid direct contact with the welding wire and The short circuit caused by the passive component can also shorten the solitary length of the bonding wire and save the welding cost. In order to achieve the disclosure and other purposes, the semiconductor package substrate with the passive component embedded in the present invention and the manufacturing method thereof include:

Page 10 17098. ptd 5. Description of the invention

Catch t, plural singles— +: electricity on both sides of the board :: road board; then '☆ at least—the first gold and-on the interval i, do n’t press together—carrying a capacitor film—ί electricity 4 :: ;: A conductive metal surface with a resistive film: gate " pole, and the second ί: conductive metal layer to form a resistance space ...:; At the same time, another "early 7" pen circuit board is formed at least-throughout the first Spaced insulation stacking ^: two circuit layers with at least one second formed in the interior, 彳 the first: after the circuit board is formed, standing in is a number of conductive , I yuan; :: Bu yuan connected to each circuit layer; f is formed on the electrical two plated plated through holes (PTT), which can be used by the imperial maker of the aforementioned 3 ::: 至 者 — the circuit on the surface of the present invention The film-like: the obtained packaging substrate, η? Semiconductor packaging substrates made of 于 τ in the substrate r-plane electrical conventional technology needs to be: the dynamic components are very different:% components and bow to reduce the difficulty of fresh connection Property: = and the cost. In addition, the "^" route can also reduce the length of the welding wire solitary production ... and the grid plate m? By combining the first unit circuit board Kth; the gate D ~ Κ 弟 —Early yuan circuit board can be closed to the side of _early electricity 丨 ”to form a meat mountain + coffee π &; Fruit circuit board m and the table at least have a resistance skin inside Passive components such as capacitor films have multilayer circuit boards with recesses, such as semiconductors 2

200416984 V. Description of the invention (5) Only the dedicated electronic components are housed and electrically connected to the multilayer circuit, so as to shorten the overall thickness of the semiconductor package and achieve the purpose of thin and short read semiconductors and high electrical properties. The following examples are provided to further illustrate the present invention in detail, and are not limited by these examples. Moreover, the drawings of the present invention are only illustrative, and are not drawn according to actual dimensions, that is, the actual dimensions of each layer in a plurality are not reflected, and are described in advance. [Embodiment] Refer to Figs. 3A to 31, which are schematic diagrams of a method for manufacturing an embedded package package of the present invention. As shown in FIG. 3A, first, at least one first circuit board (Unit circuit board) 3a is provided, and the first unit circuit board copper foil substrate (Copper Coated Laminate (CCL) (Resin Coated Copper, RCC)) or FR- 4Resin, epoxy, silicon (sili.con), poly (polyesters), glass fiber and other insulating materials on the surface (Copper Foi 1) of copper resin on the surface. The copper foil substrate is used as a unit circuit board material, that is, the upper surface 30a and the lower surface 30b of the resin layer 30 are each attached with a conductive metal layer 31 and a second conductive metal layer 32. As shown in FIG. 3B, the sublayer 31 and the second conductive metal layer 3 2 of the first divided circuit board 3 a and the second conductive metal layer 3 2 are more than 3 to form a circuit (Development)-u U + ^ is etched into the recess of the first circuit ^ of the conventional circuit _ pattern circuit (Pattern Clrcuit), and the body package is light, but the present invention is simply a half-element circuit board with a multilayer substrate structure. 3 The a series can be selected from the group of self-adhesive copper box grease and FR-5 resin resin-coated copper foil layer. The first conductive gold lithography process of an insulating copper foil layer can be used to form the 3 1 a and second

17098. ptd

Page 12

ZUU41by84 V. Description of the invention (6) --- circuit layer 3 2 a, with: |: even + right mang + green di constitutes a double-layer circuit board, where the first + di has the right trunk line area is a brother% Road layer 31 3 1b. Of course, the "_" is a multilayer circuit board with parallel circuits such as the following capacitor element and 3a can also be a multilayer with multiple layers? There are many well-known process technologies, such as fiJ circuit patterning technology, but it is not the same as the technical characteristics of this case, & the road layer 31a is no longer pressed together; there is a section of the surface of the circuit board 3a The first—the third conductive layer carrying the capacitor film 41—the second conductive circuit π ^ In the second circuit Lu—to the layer 33, and the interval 32 is separated by an insulating layer 40 to press together # 古 + 朕 4 2 The younger brother of the four conductive metal _ _ ^ halberd has resistance > eight + Shu layer 34. The capacitive film 41 is selected from the 咼 dielectric layer of 介 a 本, the bean system is composed of 古 molecules and their analogs filled with a large number of 吊 丄, 八 1 powder, Ό.. The early temples can be, for example, barium titanate (Barium-titanate), cinnamic acid (Lead-Zirconate-tltanate), amorphous hydrogenated carbon (AmOrph hydropnated carbon), or powder dispersed in the binder (Bi In s, such as resin, glass powder, etc., it can also be formed by sputtering, printing, or roller coating. ^ The material of the insulating layer 40 may be an insulating organic material or a ceramic material, such as ^ 袠 y resin (Epoxy resin), polyimide, biscis butyric acid imide / triazine (Bismaleimide triazme) -based ^^^ or a composite material of glass fiber (G 1 assfibei ·), of course, the insulating layer 40 is not limited to being formed of only a single organic material, but may also be formed by stacking different insulating material layers The resistive film 42 includes a thick film (Thick fi lm) and a thin film (Thin Π lm) resistive material. The thick film resistive material is, for example, silver powder or carbon particles (CarboI1).

17098. ptd Page 13 200416984 V. Description of the invention (7) _-- a partlcie) is dispersed in the resin, and oxide (Ru〇2) and glass powder are dispersed in a binder (Binder) and then cured to form ; The thin film resistance material is such as nickel chromium (Nl-Ci ·), nickel phosphorus (Nl-P), nickel tin (Nl_Sn), chromium aluminum (Cr-Al), and titanium nitride (TaN) alloy, etc., which It can be formed by sputtering, electroless plating, or the like. As shown in FIG. 3D, the resistive film 42 and the Nongsi conductive metal layer 34 are patterned to form a fourth circuit layer 34a and electricity and electricity. The resistive element 42a is embedded in the substrate structure, and:耆 = 3a forms at least one opening 50 penetrating the surface, and the second electronic device storage space is provided. At first glance, as shown in FIG. 3E, at least one conductive hole 43 is formed at the same time as at least one flute and one σο, and is formed by electrical connection; y! The first five five of the plate 3b & Six circuit layers 36a. Wonderful, younger brother-early = circuit board can also meet the actual design needs ;: distance ^ and the sixth circuit layer ^, the interval === five circuits ^ two:] 37a and the eighth circuit layer 3δ " the seventh Electricity is twenty-seventh: the circuit layer 38a is electrically connected to the fifth circuit layer 35a and the sixth circuit layer through the conductive iodine eighth '4 formed on the insulating layer 40;: n "ia) As shown in FIG. 3G, the first unit aa is combined.?! The circuit board 3b, so that the first unit circuit board opening 50-2: The second unit ^ is closed with the road board outline as soon as possible to form an accommodation recess. = The eighth circuit layer of the first-early circuit board 仏 on the side is separated by an insulation

200416984 V. Description of the invention (8) A ninth conductive metal layer 39 is formed. When it is absent, the first 50 may also be formed in the second unit circuit board 3b: == the opening unit circuit board 3a of the circuit board and the second unit circuit having the opening ^ to join the first second unit circuit board When the opening-side of 3b is the -M, the opening can be closed to form a storage space. The recessed portion 50a can be used to seal the junction circuit board 3a and connect electronic components such as semiconductor wafers to the substrate, and the thickness of the semiconductor device is only connected and electrically connected. '俾 Effectively reduce as shown in Figure 3H, a plurality of boats are formed at predetermined locations on the substrate * The plated-through holes (PTH) 45 on the substrate surface are provided, and these electroplated shells are electrically connected to the capacitor film 4 丨糸 σ circuit layer with the resistance film 4 2 ^ 1. The electrical mine vias 45 can be mechanically or mechanically (drilled, millimeter) to form the vias 45a, and form a metal conductive sound such as a nickel-plated layer or a copper-plated layer on the outside of the package substrate and the surface of the vias 45a. = Filling material 45c ', such as epoxy 3 (Epoxy), insulation 3 material or tin

A conductive material such as Paste) is used to fill the through hole 45a to form a plated through hole 45. As shown in FIG. 31, the ninth conductive metal i 3 9 and the third conductive metal layer 33 carrying the capacitor film 4 are patterned on the surface of the substrate to form a ninth circuit layer 39 a and a third circuit layer. 33 a and one parallel plate 3 3b of at least one capacitor element, cooperate with another parallel plate 3 1 b in the first patterned first circuit layer 3 丨 8 to complete the capacitor element 4 1 a embedded in the package substrate 1 And the ninth circuit layer 39a can be electrically connected to the circuit layer inside the package substrate through the blind hole 44. And the substrate] [0 0 can be applied to a flip-chip type (F 丨 i pCh 丨 p) coating substrate 'or a general wire-type (W i r e b ο n d i n g) packaging substrate.

Page 15 17098 · Ptd 2UU416984 V. Description of the invention (9) With the above-mentioned embedded passive component of the present invention;-^ ^., 〇〇, ^ ^ ^ " Circuit board 3a and second unit circuit board 3b, and The brackets include: the younger one has at least one opening through the surface, the first t: the circuit board 3 is connected, and the first-single S circuit board _ σ 5 () side, ς G-receiving recess 5 a; Plural patterned circuit layers y 43L ^ 2 ^ 3 * Γ3, 35a, 36 " 3? A > 383 > 39 ^ ^ ^ ^ 4〇 It is placed inside the full-fledged second unit circuit board; at least one or two Six at least one resistive film 42 are formed in the first unit, and are electrically conductive blind holes a44 connected to the circuit layer of the second unit circuit board 3b] zi, a plated through through the package substrate 100 Hole (ρτΗ), which can be electrically connected to the circuit formed on at least one of the capacitor film 41 and the resistor film 42. The younger brother: Γ circuit board 3a or the second unit circuit board 3b may be selected from copper

St 'or copper foil resin layer 辇 M + on the surface of FR-4 resin, FR-5 resin, epoxy resin ^ β η ~ 22 3 ^, glass fiber and other insulating materials, copper-clad pig layer And other conductive metal layers, and pattern the circuit with copper on the surface and multiple circuit layers of multiple layers of electricity :: a double-layer circuit board, which can also be formed-stacked, with the layer M3,32,338,343,358,368,373,383,3 · 1 being 1; The steel layer 'is formed on the insulating layer 40, and the insulating material is made of an electric 0-fiber reinforced organic material or a particle reinforced organic Hobesixun I bayan material. The eye-opening holes 44 are formed in the insulating layer 40, which can be drilled with a mechanical drill.

17098.ptd Page 16 200416984 V. Description of the invention (ίο) Holes or laser drilling are formed, and at least one conductive metal layer is formed on the insulating layer 40 by electroplating, electroless plating or sputtering, etc. The conductive metal layer can be wholly or partially covered to the conductive blind hole 44, and the conductive blind layer 44 and the conductive hole 43 can be electrically connected to the circuit layers on both sides of the insulating layer. The capacitor film 41 is selected from a high-dielectric layer having a large dielectric constant, and is made of a polymer material such as a polymer material, a ceramic material, a ceramic powder, and the like. Generally, the dielectric constant is greater than 5; Applicable. Of course, the higher the dielectric constant value, the better. The material can be, for example, barium titanate, lead hafnium titanate, amorphous hydrogenated carbon, or a powder thereof dispersed in a binder such as resin, glass powder, etc. Can be formed by sputtering, printing or roller spin coating. And the capacitance value required for the semiconductor package substrate can be based on the material of the capacitor film 4 1 used and the capacitor element 4 sandwiched between the parallel plates 3 1 b and 3 3 b formed on the opposite surface of the capacitor film 41. 1 a size plus decision. The resistive film 42 includes thick film (Thick fi lm) and thin film (Thin fi 1 m) resistive passive elements, and the thick film resistive material is such as silver powder or carbon particles dispersed in resin, and ruthenium oxide and glass powder are dispersed in An adhesive is formed by coating and then curing. In contrast, the thin film resistance material is formed by means of coin plating, electroplating, or electroless plating, such as recording, recording, tin recording, chromium inscription, and titanium nitride alloy. The choice of using a thick film resistor or a thin film resistor is determined by the manufacturing cost of the multilayer circuit board and the electrical accuracy of the passive components. And the magnitude of the required resistance value of the semiconductor package substrate can be determined by the size of the resistance element 42a of the used resistance film 42 and the distance between the electrodes 34b formed on the resistance film 42. Passive component-embedded semiconductor package substrate manufacturing method of the present invention

17098. ptd Page 17 200416984 V. Description of the invention (11)-Method-Result = board 'Built i less one film piece in the substrate' to enhance the semiconductor element and at least one capacitor element and electrical function '@ 时 Increase the number of printed circuit board components < Avoid passive components from high sides and mold flow shadow :: Live:' In addition, the phenomenon to reduce welding _ difficult to produce, g-direction deviation, and even short circuit caused The short circuit can also be retracted, avoiding the direct contact of the welding wire and the passive components, and then 'saving the welding cost by combining the first to the second single length. To make the second unit circuit board = the board and the second unit circuit board, to form a built-in imperial pedal, to hold the opening of the first unit circuit board _ at least one recessed part] capacitors and other passive components And the military component storage and electrical connection two :, such as semiconductor crystal -... ΐ :: in the recessed part of the circuit board, thereby shortening the overall semiconductor package ^ The recessed parts of the circuit board are thin, short and high The purpose of electrical properties: to achieve the degree of the semiconductor package. In the previous drawings, only the resistance film, the capacitive film, and the capacitive film are used. In fact, it is necessary to set two = number and relative position in the current process, which is based on the unit circuit. The opening of the board ^ ^ between the laminates of the substrate, and the second unit circuit board is connected to the second unit circuit board. When the second unit circuit board is opened, the two unit circuit boards are formed. —Introduction space: The first unit circuit board is only used to illustrate the features of the present invention and the specific embodiments described above, and < implementation materials, without deviating from the present invention and using the present invention. Reveal the inner c god and technology fan mouth, decorated ' Please t should remain below the equivalent patent change and repair

200416984 Brief description of the drawings [Simplified description of the drawings]: Figure 1 is a schematic diagram of the conventional layout of passive components placed outside the semiconductor wafer receiving area on the additional layout area of the substrate, and Figure 2 is a conventional method of integrating passive components The schematic cross-sections between the semiconductor wafer and the soldering area and Figures 3A to 3: I are schematic diagrams of the method for manufacturing a semiconductor package substrate with embedded passive components of the present invention. 1,2, 100 substrates 11, 21 semiconductor wafers 12, 22 passive Component 23 Welding wire 24 Encapsulation resin 3a First-Unit circuit board 3b First-Early circuit board 30 Insulating resin layer 3 0a Upper surface 30b Lower surface 31 First conductive metal layer 32 Second conductive metal layer 33 First-conductive metal Layer 34 fourth conductive metal layer 39 ninth conductive metal layer 31a first circuit layer 32a second circuit layer 33a second circuit layer 34a fourth circuit layer 3 5a fifth circuit Layer 36a, circuit layer 37a, seventh circuit layer 3 8a, eighth circuit layer 3 9a, ninth circuit layer 31b, 33b parallel plate 34b, resistive electrode 40, insulating layer 41, capacitive film 42, resistive film 41a, capacitive element 42a, resistive element 43, via hole

17098.ptd Page 19 200416984 Brief description of the diagram 4 4 * Blind L 45 Electroplated Conductor L 45a Passive L 45b Metallic Conductive Layer 45c Filling Material 50 Open V 5 0a Recess

17098.ptd Page 20

Claims (1)

200416984 VI. Application for Patent Scope 1. A method for manufacturing a semiconductor package substrate with embedded passive components, comprising: providing at least a first unit circuit board, and respectively laminating a conductive film carrying a capacitor film on a circuit layer on the surface thereof; A metal layer and a conductive metal layer carrying a resistance film through an insulation layer spaced from the unit circuit board; patterning the resistance film of the first unit circuit board and a conductive metal layer on the surface thereof; providing at least one second unit circuit board Is formed by a plurality of circuit layers with spaced insulation and stacking, and the circuit layers are electrically connected by a plurality of conductive holes and blind holes formed in the interior, and are placed on any one of the first unit circuit board and the second unit circuit board. One is formed with at least one opening penetrating the circuit board; and the first unit circuit board and the second unit circuit board are combined so that one side of the opening of the one unit circuit board is closed and recessed by the other unit circuit board. Shao Wei to Fan Licheng become a special form, please apply, such as 2 β, Likou: the compound method to make the plate base package guide half of the line, Houyuan Banrong Road is a two-layer electric element with a single-layer sheet that is conductive to the gold plate circuit. It has a membrane that allows the battery to be closed. The case is shown in Figure 4 at the rear panel item. Dedicated electricity. Please make a plate application like the three methods to make the plate base package package guide. The plate base = = ° has a large number of penetrations. Forming resistance and film capacitance should be formed to the ground. The layered circuit can be supplied with electricity, and the surface of the hole can be connected to the membrane by M. 17098.ptd Page 21 200416984 6. Scope of patent application 4 The method for manufacturing a semiconductor package substrate according to item 3 of the patent application scope, wherein the conductive metal layer on the surface of the patterned resistive film can be formed as an electrode of a resistive element. 5. If the method for manufacturing a semiconductor package substrate according to item 4 of the patent application scope, after the conductive metal layer on the surface of the patterned resistive film is completed, at least one insulating layer and a conductive blind hole can be formed, and the conductive blind hole can be connected with the resistive element. The electrodes are turned on. 6. The method for manufacturing a semiconductor package substrate according to item 1 of the scope of patent application, wherein the unit circuit board is any one of a double-layer circuit board and a multilayer circuit board. The method for manufacturing a semiconductor package substrate according to item 1 of the application, wherein the resistive film is any of a thick film (Thick f 1 lm) and a thin film (Thin f i lm) resistive material. 8. The method for manufacturing a semiconductor package substrate according to item 7 of the scope of patent application, wherein the thick film resistor material is silver powder (S i 1 ver ρ ωwder), carbon particles (Carbon particles) are dispersed in the resin, and ruthenium oxide (R u〇 2) and glass powder are dispersed in a binder (B inder) and coated with solid gasification. 9. The method for manufacturing a semiconductor package substrate according to item 7 of the scope of patent application, wherein in φ, the thin film resistance material is nickel chromium (N i-C r), nickel phosphorus (N i-P), and tin (Ni- Sn), chromium is (Cr-Al), and a titanium nitride (TaN) alloy. 10. The method for manufacturing a semiconductor package substrate according to item 1 of the scope of patent application, wherein the capacitor film is made of a polymer material, a ceramic material, and a ceramic powder. 17098.ptd Page 22 200416984 6. Scope of patent application Composed of a mixture of filled polymers and their analogs. 1 1. The method for manufacturing a semiconductor package substrate according to item 1 of the scope of patent application, wherein the capacitor film is barium titanate, lead — zirconate — titanate, amorphous Nitrogen 4 Amorphous hydrogenated carbon (Amorphous hydrogenated carbon)? And its powder is dispersed in the binder (B inder). 1 2. A semiconductor package substrate with embedded passive components, at least including: at least a first unit circuit board and a second unit circuit board, and at least one through circuit board is formed in any one of the two unit circuit boards. The opening is such that one side of the opening of the unit circuit board is closed by another unit circuit board to form at least one recess; a plurality of layers of patterned conductive metal layers form a circuit layer, which are spaced apart from each other by an insulating layer to be stacked on Each unit circuit board; at least one patterned resistance film and at least one capacitor film are formed on the first unit circuit board; and a plurality of plated through-holes are formed in the substrate to provide power-supply conductive patterning. Conductive metal layer, resistance film and capacitor film. ~ 1 3. The semiconductor package substrate according to item 12 of the patent application scope, wherein the surface of the patterned resistive film has a patterned conductive metal layer, which can be an electrode of a resistive element. 14. The semiconductor package substrate according to item 12 of the scope of patent application, wherein the surface of the capacitor film has a patterned conductive metal layer, which can be a parallel plate of a capacitor element. 15. The semiconductor package substrate according to item 13 of the scope of patent application, wherein 17098.ptd Page 23 200416984 6. Scope of patent application 'The surface of the conductive metal layer patterned on the surface of the resist film can form at least an insulating layer and a conductive blind hole, and the conductive blind hole can be connected to the electrode of the resistive element. 16. The semiconductor package substrate according to item 14 of the scope of patent application, wherein at least one insulating layer and a conductive blind hole can be formed on the surface of the conductive metal layer patterned on the surface of the capacitor film, and the conductive blind hole can be used with a capacitor. The parallel plates of the components are turned on. 17. The semiconductor package substrate according to item 12 of the patent application scope, wherein at least one conductive metal layer can be added on the surface of the substrate. g. The semiconductor package substrate of item 12 in the scope of patent application, wherein the 'unit circuit board is any one of a double-layer circuit board and a multilayer circuit board. 0 1 9 The semiconductor package substrate according to item 3, wherein the resistive film is any one of a thick film and a thin film resistive material. 2 〇. The semiconductor package substrate according to item 19 of the scope of patent application, wherein the * ^ thick film resistor material is silver powder (S i 1 ver ρ ωwder), carbon particles, (Carbon particle) dispersed in the resin, And ruthenium oxide (Ru 2) and glass powder are dispersed and spread on a binder (B inder) to form a coating. 2 1. The semiconductor package substrate according to item 19 of the patent application scope, wherein the thin film resistor material is nickel-chromium (Ni-Cr), nickel-phosphorus (Ni-P), nickel-tin (Ni-Sn), chromium-aluminum (Cr-A1), and titanium nitride (TaN) alloys. 17098.ptd p. 24 200416984 17098.ptd Page 25