200931458 - 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種電容元件及其製法，尤指一種尺寸 小、厚度薄，且尺寸、厚度、電極尺寸及容值變異性小之 5 電容元件及其製法。 【先前技術】 Q 隨著電子產業的蓬勃發展，電子產品亦逐漸邁入具有 多功能、高性能之發展趨勢。為滿足半導體封裝件高積集 10 度（integration)及微型化（miniaturization)的封裝需求，以供 更多主被動元件及線路載接，半導體封裝基板亦逐漸由雙 層演變成多層（multi-layer)，俾在有限的空間下運用層間連 接技術（interlayer connection)以擴大半導體封裝基板上可 供利用的線路佈局面積，藉此配合高線路密度之積體電路 15 (integrated circuit)需要，降低封裝基板的厚度，以在相同 基板單位體積中容納更多數量的線路及電子元件。 然而，半導體裝置積集化之同時，封裝構造之接腳數 目亦隨著增加，常由於接腳數目與線路佈設之增多，導致 雜訊亦隨之增大。因此，通常於半導體封裝結構中增加被 20 動元件，如電阻元件、電容材料與電感元件，以消除雜訊 或作電性補償與穩定電路，藉此使得所封裝之半導體晶片 能符合所需之電性特性。 習知方法中，通常利用表面黏著技術（Surface Mount Technology ; SMT)，將多數被動元件整合至基板表面上。 200931458 而此時所使用之電容元件一般採用陶瓷材料’經過高溫燒 結而形成。而此種方式所形成之陶瓷電容元件，常具有尺 寸大及厚度厚等缺點，又所製作之電容元件，其尺寸、厚 度、電極尺寸及容值變異性大，不利於高頻或高階電子產 5 ❹ 10 15 ❹ 品系統的應用，亦不符合於現今電子裝置輕薄短小的需求。 因此，製作尺寸小、厚度薄，且其尺寸、厚度、電極 尺寸及容值均一性佳（變異性小）之電容元件，已為現今業界 亟需達成之目標。 〃 1 【發明内容】 鑑於上述問題，本發明提供一種電容元件，包括·一 高介電材料層，·-外線路層，係設於該高介電材料層之相 對兩表面，俾成為一電容設置層，其中該外線路層具有至 少y對以該高介電材料層間隔且互相平行對應之外電極 板’複數導電結構’係貫穿該高介電材料層且分別電性 連接該高介電材料層相對兩表面之該外線路層；以及一絕 緣保護層，係覆蓋該電容設置層之相對兩表面，且該絕緣 保護層具有至少-成對開孔以顯露部份該外線路層作為電 性連接塾。 ''' 上述電容元件中，該至少一成對之開孔較佳可選擇分 料於該電容設置層相對的兩表面上，或者是—起設於該 ，今汉置層同一侧表面。而上述之導電結構不受限制，= 能要能電性連接該高介電材料層相對兩表面之該外線路層、 即可，較佳可科電盲孔、導電通孔、或前述兩者之組合。 20 200931458 上述電容元件還可句杯5+ 带a T包括至）一内線路層嵌埋於該高介 電材料層内，且每—Ηη a A. a 母内線路層與該外線路層係以該高介電 材料層間隔，其中，号內始敗 ^ T r該内線路層係具有至少一内電極板， 係平打對應於該至少一對外電極板。 5 Ο 10 15 ❹ 本發明亦提供—種上述電容元件之製法，其包含：提 供-電容設置層’係具有—高介電材料層及分別設於其相 對兩表面之-線路層，該線路層具有至少_對以該高介電 材料制隔且互相平行對應之電極板；形成複數導電結 構，係貫穿該高介電材料層，且該些導電結構分別電性連 接該電容設置層相對S表面之該些線路層；以及形成一絕 緣保護層’係覆蓋該電容設置層之相對兩表面且該絕緣 保邊層具有至少-成對之開孔以顯露部份該線路層作為複 數電性連接墊。 另外，上述製法復可包括把該電容設置層及其表面覆 蓋之絕緣保護層一起進行分割以形成複數電容單元。 本發明另提供一種上述電容元件之製法，包含：提供 至少二電容設置層，每一電容設置層具有一第一高介電材 料層及分別设於其相對兩表面之一線路層，且該些線路層 具有至少一對以第一高介電材料層間隔且互相平行對應之 電極板，然後將每一電容設置層間隔一第二高介電材料層 進行壓合，其中，至少一對電極板係以第二高介電材料層 間隔且互相平行對應；形成複數導電結構，係貫穿該些高 介電材料層，且該些導電結構分別電性連接該些線路層； 以及形成一絕緣保護層’係覆蓋最外面二電容設置層之表 20 200931458 面，且該絕緣保護層具有至少一成對之開孔以顯露部份該 線路層作為複數電性連接墊。 上述製法中，而上述之導電結構不受限制，只能要能 電性連接該高介電材料層相對兩表面之該外線路層即可， 5 ❺ 10 15 ❹ 20 較佳可為導電盲孔、導電通孔、或前述兩者之組合。該至 少一成對之開孔較佳係分別設於最外面二電容設置層之一 表面，或者是一起設於最外面一電容設置層之表面。 另外，上述製法復可包括把該些電容設置層及最外面 二電容設置層表面覆蓋之絕緣保護層一起進行分割以形成 複數電容單元。 由上述可知，透過本發明製法係利用金屬薄板壓合高 介電材料所形成之高介電金屬薄板，進行加工及線路製 程，因此，可輕易製作任意形狀、尺寸小、厚度薄，且尺 寸、厚度、電極尺寸及容值之均一性佳（變異性小）之電容元 件，以符合現今電子裝置輕薄短小之要求。並且，本發明 所提供的電容元件製法，並沒有習知電容元件因採用陶瓷 高溫加工，而致容值等變異性大的缺點。此外，本發明提 供之電容7L件，於同一電容元件上可輕易配置多對電極， 電極對可依所需而設計於同侧或相對側，並利用易於開孔 之防谭層（如綠漆）能同時滿足絕緣保護與電性區隔之需 要。 【實施方式】 以下係藉由特定的具體實施例說明本發明之實施方 8 200931458 • 式，熟習此技藝之人士可由本說明書所揭示之内容輕易地 了解本發明之其他優點與功效。本發明亦可藉由其他不同 的具體實施例加以施行或應用，本說明書中的各項細節亦 可基於不同觀點與應用，在不悖離本發明之精神下進行各 5 種修飾與變更。 實施例1 請參考圖1A至圖1D，係為本實施例電容元件製法之流 ® 程剖示圖。 10 首先，如圖1A所示，提供兩銅箔層21’，22’及一第一高 介電材料層23。此處所提供之銅箔層2Γ,22’，其相對兩表 面可先透過粗糙化製程如刷磨或研磨，以增加其與介電材 料層23之結合力。而後，如圖1B所示，將兩銅箔層2Γ,22’ 與第一高介電材料層23進行壓合以形成一電容設置層2。 15 針對圖1B所示電容設置層2之A區放大來看，如圖1C所 示，利用電鍍與蝕刻，將電容設置層2兩表面之銅箔層 _ 21’，22’形成一線路層21,22，該線路層21，22具有一對以第一 高介電材料層23間隔且互相平行對應之電極板213,223。並 且，利用鑽孔（如雷射鑽孔或機械鑽孔）結合電鍍等技術， 2〇 於電容設置層2中形成一導電通孔54,該導電通孔54是用來 電性連接電容設置層2兩相對表面之線路層21，22。 接著，如圖1D所示，形成一絕緣保護層61，62覆蓋電容 設置層2之相對兩表面並填充該導電通孔54。該絕緣保護層 61,62可使用作為介電層之材料，例如感光或非感光有機樹 25 脂，例如 ABF (Ajinomoto Build-up Film)·、.聯二苯環 丁二浠 200931458 • ( benzocylobutene，BCB )、液晶聚合物（liquid crystal polymer，LCP )、聚亞醯胺（polyimide，PI)、聚乙烯醚 (poly(phenylene ether)，PPE )、聚四氟乙烯 (poly(tetra-fluoroethylene) » PTFE)、FR4、FR5、雙順丁 5 醯二酸醯亞胺/三氮牌（bismaleimide triazine，BT )、芳香 尼龍（aramide)等，或亦可為混合環氧樹脂與玻璃纖維等材 質；或者該絕緣保護層61，62也可使用作為防焊層之材料， 例如綠漆等》接著，在絕緣保護層61同侧開設一成對之開 ^ 孔611，612，以顯露部分線路層21作為複數電性連接墊 10 214,215。復可在顯露出來的電性連接墊214,215表面，形成 一表面處理層711，712，該表面處理層711，712可選自鎳/ 金、有機保焊膜、化鎳浸金、鎳/鈀/金、錫、焊錫、無鉛 焊錫、或銀。 如此，便可完成本發明所提供電容元件。參考圖1D， 15 該電容元件包括：一高介電材料層（即第一高介電材料層 23)、一外線路層（即線路層21，22)、複數導電結構（即 〇 導電通孔54)、及一絕緣保護層61，62。其中，外線路層21，22 設於該高介電材料層23之相對兩表面，俾成為一電容設置 層2。外線路層21，22具有至少一對以該高介電材料層23間隔 20 丘互相平行對應之外電極板（即電極板213,223 )。導電結 構（即導電通孔54)貫穿該高介電材料層23 ’且電性連接 該些外線路層21，22。絕緣保護層61，62覆蓋電容設置層2之 相對兩表面，且該絕緣保護層61具有一成對開孔611,612， 以顯露部份外線路層21作為電性連接整214,215。圊1D’所 200931458 - 示為本實施例之另一態樣，其與圖ID不同處在於絕緣保護 層61，62之成對開孔611,622並非設於同側，而是設於對侧， 亦即分別顯露部分線路層21,22以作為電性連接塾 214,224’此外’其係以導電盲孔54,貫穿該高介電材料層23 5 以電性連接電容設置層2兩相對表面之線路層21，22。 實施例2 請參考圖2A至圖2D ’係為本實施例電容元件製法之流 ❹ 程剖示圖。 10 首先，提供兩電容設置層2與3。如圖2A所示，該兩電 容設置層2與3兩相對表面已先利用電鍍與蝕刻分別形成線 路層21，22與31，32於一第一高介電材料層23與33之兩侧，且 線路層21，22與31，32具有成對以第一高介電材料層23與33 間隔且互相平行對應之電極板213,223與313,323。 15 然後，如圖2B所示’於兩電容設置層2與3之間，置放 一第二高介電材料層43後進行壓合，使兩電容設置層2與3 〇 間線路層22,32之電極板223,323係以第二高介電材料層43 間隔且互相平行對應。 如圖2C所示，利用鑽孔結合電鍍技術，形成導電通孔 20 54貫穿第一高介電材料層23與33及第二高介電材料層43， 使導電通孔54分別電性連接線路層21，22,31，32。接著，如 圖2D所示’填充導電通孔54並形成一絕緣保護層61，62，該 絕緣保護層61，62覆蓋二電容設置層2與3之表面。並且，該 絕緣保護層61,62同樣具有成對之開孔611,612與621，622以 25 顯露部份線路層21與31作為複數電性連接墊214,215與 11 200931458 314,315 °在顯露出來的電性連接墊214,215與314,315表 面’復可形成一表面處理層711，712與721，722，其可選用實 施例1所述之材質。 如此’便可完成本發明所提供電容元件。參考圖2D， 5該電谷元件包括：第一高介電材料層23,33、第二高介電材 料層43、外線路層（即線路層21，31)、内線路層（即線路 層22,32)、複數導電結構（即導電通孔54)、及絕緣保護 層61，62。其中，外線路層21，31設於第一高介電材料層23,33 之表面，且具有至少一對以第一高介電材料層23,33間隔且 10互相平行對應之外電極板213,313。内線路層22,32設於第二 高介電材料層43之兩侧，且嵌埋於第一高介電材料層23與 33之間，且内線路層22 32與外線路層2131係以第一高介電 材料層23與33間隔，又内線路層22,32具有内電極板 223,323，平行對應於外電極板213313。導電結構54貫穿第 15 一南介電材料層23,33、第二高介電材料層43 ,且電性連接 該些外線路層21,31、内線路層22,32 »絕緣保護層61，62分 別覆蓋電容設置層2與3之表面，且該絕緣保護層61，62具有 成對開孔611，612與621，622，以顯露部份外線路層21，3旧 為電性連接墊214,215與314,315。圖2D，所示為本實施例之 20 另一態樣’其與圖2D不同處在僅於一侧之絕緣保護層6 i具 有一成對開孔611，622，而另一側之絕緣保護層62則未具成 對開孔。 八 另外，參考圖2E-1，其為利用本發明製法所製作之電 容元件整版面（panel)的上視圖。如圖2E-1所示，本發明可 12 200931458 製作複數電容單元。其中，每一個電容單元皆可被切割為 電容凡件°因此’如圖2E-2所示，係於該電容元件整版面， 將其電容設置層2與3連同絕緣保護層61，62經過切割後，即 可形成複數電容單元。 5 ❹ 10 15 ❹ 20 由上述可知’透過本發明製法係利用金屬薄板壓合高 介電材料所形成之高介電金屬薄板，進行加工及線路製 程，因此，可輕易製作任意形狀、尺寸小、厚度薄，且尺 寸、厚度、電極尺寸及容值之均一性佳（變異性小）之電容元 件，以符合現今電子裝置輕薄短小之要求。並且，本發明 所提供的電容το件製法，並沒有習知電容元件因採用陶瓷 高溫加工，而致容值等變異性大的缺點。此外，本發明提 供之電容元件，於同一電容元件上可輕易配置多對電極， 電極對可依所需而設計於同侧或相對侧，並利用易於開孔 之防焊層（如綠漆）能同時滿足絕緣保護與電性區隔之 要。 上述實施例僅係為了方便說明而舉例而已，本發明所 主張之權利範圍自應以申料利㈣所述為帛，而非僅限 於上述實施例。 【圖式簡單說明】 圖1A至圖1D’係本發明實施例1製法之流程剖示圖。 圖2A至圖2D’係本發明實施例2製法之流程剖示圖。 圖2E-1係本發明實施例2電容元件整版面之上視圖。 圖2E-2係本發明實施例2電容元件之電容單元上視圖。 13 200931458 【主要元件符號說明】200931458 - IX. Description of the Invention: [Technical Field] The present invention relates to a capacitor element and a method of manufacturing the same, and more particularly to a capacitor having a small size, a small thickness, and small variations in size, thickness, electrode size, and capacitance value. Components and their methods of manufacture. [Prior Art] Q With the rapid development of the electronics industry, electronic products have gradually entered a trend of multi-functionality and high performance. In order to meet the requirements of high integration and miniaturization of semiconductor packages for more active and passive components and lines, semiconductor package substrates have gradually evolved from double layers to multiple layers (multi-layer).俾Using an interlayer connection in a limited space to expand the available circuit layout area on the semiconductor package substrate, thereby reducing the package substrate with the need for a high circuit density integrated circuit 15 (integrated circuit) The thickness is such that a larger number of lines and electronic components are accommodated in the same substrate unit volume. However, as semiconductor devices are integrated, the number of pins in the package structure increases, and the number of pins and the number of lines are often increased, resulting in an increase in noise. Therefore, generally 20 semiconductor components, such as resistive components, capacitive materials and inductive components, are added to the semiconductor package structure to eliminate noise or electrical compensation and stabilization circuits, thereby enabling the packaged semiconductor wafer to meet the required requirements. Electrical properties. In conventional methods, most of the passive components are typically integrated onto the surface of the substrate using Surface Mount Technology (SMT). 200931458 The capacitor element used at this time is generally formed by firing a ceramic material at a high temperature. The ceramic capacitor component formed by such a method often has the disadvantages of large size and thick thickness, and the capacitor element produced has large size, thickness, electrode size and capacitance variability, which is disadvantageous for high frequency or high-order electronic products. 5 ❹ 10 15 The application of the product system is not in line with the demand for light and thin electronic devices. Therefore, it is an urgent need in the industry to produce a capacitor element which is small in size, thin in thickness, and excellent in size, thickness, electrode size, and uniformity of capacitance (small variability). 〃 1 SUMMARY OF THE INVENTION In view of the above problems, the present invention provides a capacitor element comprising a layer of high dielectric material, an outer circuit layer disposed on opposite surfaces of the high dielectric material layer, and a capacitor Providing a layer, wherein the outer circuit layer has at least y pairs spaced apart by the high dielectric material layer and corresponding to each other; the outer electrode plate 'plural conductive structure' penetrates the high dielectric material layer and electrically connects the high dielectric respectively The outer circuit layer of the material layer opposite to the two surfaces; and an insulating protective layer covering the opposite surfaces of the capacitor setting layer, and the insulating protective layer has at least a pair of openings to expose a portion of the outer circuit layer as electrical Connection 塾. In the above capacitive element, the at least one pair of openings may preferably be selectively disposed on opposite surfaces of the capacitor setting layer, or may be disposed on the same side surface of the current layer. The above-mentioned conductive structure is not limited, and the external circuit layer capable of electrically connecting the opposite surfaces of the high dielectric material layer can be electrically connected, preferably a conductive blind hole, a conductive via, or both. The combination. 20 200931458 The above capacitive element may also include a cup 5+ tape a T including) an inner circuit layer embedded in the high dielectric material layer, and each - a a A. a mother inner circuit layer and the outer circuit layer The high dielectric material layer is spaced apart, wherein the inner circuit layer has at least one inner electrode plate, and the flat circuit corresponds to the at least one outer electrode plate. 5 Ο 10 15 ❹ The present invention also provides a method for manufacturing the above capacitor element, comprising: providing a capacitor-setting layer having a layer of high dielectric material and a circuit layer respectively disposed on opposite surfaces thereof, the circuit layer Having at least _ an electrode plate separated by the high dielectric material and corresponding to each other; forming a plurality of conductive structures extending through the high dielectric material layer, and the conductive structures are electrically connected to the S surface of the capacitor layer The circuit layers are formed; and an insulating protective layer is formed to cover opposite surfaces of the capacitor layer and the insulating layer has at least a pair of openings to expose a portion of the circuit layer as a plurality of electrical connection pads . In addition, the above method may include dividing the capacitor-setting layer and the surface-covered insulating protective layer thereof to form a plurality of capacitor units. The invention further provides a method for manufacturing the capacitor element, comprising: providing at least two capacitor setting layers, each capacitor setting layer having a first high dielectric material layer and a circuit layer respectively disposed on one of opposite surfaces thereof, and The circuit layer has at least one pair of electrode plates spaced apart from each other by a first layer of high dielectric material and correspondingly parallel to each other, and then each of the capacitor layers is laminated by a second layer of high dielectric material, wherein at least one pair of electrode plates The second high-dielectric material layer is spaced apart from each other and parallel to each other; a plurality of conductive structures are formed through the high-dielectric material layers, and the conductive structures are electrically connected to the circuit layers respectively; and an insulating protective layer is formed The system covers the outermost two capacitor setting layers of Table 20 200931458, and the insulating protective layer has at least one pair of openings to expose a portion of the circuit layer as a plurality of electrical connection pads. In the above method, the conductive structure is not limited, and the external circuit layer of the opposite surfaces of the high dielectric material layer can be electrically connected. 5 ❺ 10 15 ❹ 20 is preferably a conductive blind hole. , conductive vias, or a combination of the two. Preferably, the at least one pair of openings are respectively disposed on one surface of the outermost two capacitor setting layers, or are disposed on the surface of the outermost capacitor setting layer. In addition, the above method may include dividing the capacitor-setting layer and the insulating protective layer covered by the surface of the outermost two capacitor-setting layers to form a plurality of capacitor units. It can be seen from the above that the high dielectric metal thin plate formed by pressing a high dielectric material by a metal thin plate is processed and processed by a metal thin plate, so that it can be easily fabricated into any shape, small size, thin thickness, and size. Capacitance components with good uniformity (small variability) in thickness, electrode size and capacitance to meet the requirements of today's electronic devices. Further, in the method of manufacturing a capacitor element provided by the present invention, there is no known disadvantage that the capacitance element has a high variability in capacitance or the like due to the high-temperature processing of the ceramic. In addition, the capacitor 7L provided by the invention can easily configure a plurality of pairs of electrodes on the same capacitor element, and the electrode pairs can be designed on the same side or opposite sides as needed, and the layer of anti-tank (such as green paint) which is easy to open is utilized. ) can meet the needs of insulation protection and electrical separation. [Embodiment] The following describes the embodiments of the present invention by way of specific embodiments 8 200931458. Those skilled in the art can readily understand other advantages and effects of the present invention from the disclosure of the present specification. The present invention may be embodied or applied in various other specific embodiments, and various modifications and changes can be made without departing from the spirit and scope of the invention. Embodiment 1 Please refer to FIG. 1A to FIG. 1D , which are cross-sectional views of a flow of a capacitor element manufacturing method of the present embodiment. 10 First, as shown in Fig. 1A, two copper foil layers 21', 22' and a first high dielectric material layer 23 are provided. The copper foil layers 2, 22' provided herein may be firstly passed through a roughening process such as brushing or grinding to increase the bonding force with the dielectric material layer 23. Then, as shown in Fig. 1B, the two copper foil layers 2, 22' are pressed together with the first high dielectric material layer 23 to form a capacitor-setting layer 2. 15 For the enlargement of the A region of the capacitor setting layer 2 shown in FIG. 1B, as shown in FIG. 1C, the copper foil layers _ 21', 22' on both surfaces of the capacitor setting layer 2 are formed into a wiring layer 21 by electroplating and etching. 22, the circuit layers 21, 22 have a pair of electrode plates 213, 223 spaced apart from each other by a first layer of high dielectric material 23 and corresponding to each other in parallel. Moreover, a conductive via 54 is formed in the capacitor setting layer 2 by using a hole (such as laser drilling or mechanical drilling) in combination with plating, etc., and the conductive via 54 is used to electrically connect the capacitor layer 2 Two opposite surface circuit layers 21, 22. Next, as shown in Fig. 1D, an insulating protective layer 61, 62 is formed covering the opposite surfaces of the capacitor set layer 2 and filling the conductive vias 54. The insulating protective layers 61, 62 may be used as a dielectric layer material, such as a photosensitive or non-photosensitive organic tree 25 grease, such as ABF (Ajinomoto Build-up Film), .. diphenylcyclobutadiene 200931458 • (benzocylobutene, BCB), liquid crystal polymer (LCP), polyimide (PI), poly(phenylene ether, PPE), poly(tetra-fluoroethylene) PTFE ), FR4, FR5, bismaleimide triazine (BT), aramide, etc., or may be a mixture of epoxy resin and glass fiber; or The insulating protective layers 61, 62 may also be used as a material for the solder resist layer, such as green lacquer, etc. Next, a pair of opening holes 611, 612 are formed on the same side of the insulating protective layer 61 to expose a portion of the wiring layer 21 as a plurality Electrical connection pads 10 214, 215. A surface treatment layer 711, 712 may be formed on the surface of the exposed electrical connection pads 214, 215. The surface treatment layers 711, 712 may be selected from the group consisting of nickel/gold, organic solder mask, nickel immersion gold, nickel/palladium/ Gold, tin, solder, lead-free solder, or silver. Thus, the capacitive element provided by the present invention can be completed. Referring to FIG. 1D, 15 the capacitive element comprises: a high dielectric material layer (ie, a first high dielectric material layer 23), an outer circuit layer (ie, circuit layers 21, 22), and a plurality of conductive structures (ie, germanium conductive vias). 54), and an insulating protective layer 61, 62. The outer circuit layers 21, 22 are disposed on opposite surfaces of the high dielectric material layer 23, and become a capacitor layer 2. The outer wiring layers 21, 22 have at least one pair of outer electrode plates (i.e., electrode plates 213, 223) that are spaced apart from each other by the high dielectric material layer 23. A conductive structure (i.e., conductive vias 54) extends through the high dielectric material layer 23' and electrically connects the outer circuit layers 21,22. The insulating protective layers 61, 62 cover opposite surfaces of the capacitor setting layer 2, and the insulating protective layer 61 has a pair of openings 611, 612 to expose a portion of the outer wiring layer 21 as electrical connections 214, 215.圊1D'200931458 - is another aspect of the embodiment, which is different from the figure ID in that the pair of openings 611, 622 of the insulating protective layer 61, 62 are not disposed on the same side, but are disposed on the opposite side, that is, A portion of the circuit layers 21, 22 are respectively exposed as electrical connections 214, 224'. In addition, they are electrically conductive blind holes 54 extending through the high dielectric material layer 23 5 to electrically connect the circuit layers 21 of the opposite surfaces of the capacitor layer 2. ,twenty two. Embodiment 2 Please refer to Fig. 2A to Fig. 2D' for a flow chart of the method for manufacturing a capacitor element of the present embodiment. 10 First, provide two capacitors to set layers 2 and 3. As shown in FIG. 2A, the opposite surfaces of the two capacitor-disposing layers 2 and 3 have been first formed by plating and etching to form circuit layers 21, 22 and 31, 32 on both sides of a first layer of high dielectric material 23 and 33, The circuit layers 21, 22 and 31, 32 have electrode plates 213, 223 and 313, 323 which are paired with the first high dielectric material layers 23 and 33 and which correspond to each other in parallel. 15 then, as shown in FIG. 2B, between the two capacitor setting layers 2 and 3, a second high dielectric material layer 43 is placed and then pressed, so that the two capacitors are provided with layers 2 and 3 inter-turn circuit layers 22, The electrode plates 223, 323 of 32 are spaced apart by the second layer of high dielectric material 43 and correspond in parallel with each other. As shown in FIG. 2C, the conductive vias 2054 are formed through the first high dielectric material layers 23 and 33 and the second high dielectric material layer 43 by using a hole-bonding plating technique, so that the conductive vias 54 are electrically connected to the wires. Layers 21, 22, 31, 32. Next, the conductive vias 54 are filled and formed as an insulating protective layer 61, 62 as shown in Fig. 2D, and the insulating protective layers 61, 62 cover the surfaces of the two capacitor setting layers 2 and 3. Moreover, the insulating protective layers 61, 62 also have a pair of openings 611, 612 and 621, 622 to reveal a portion of the circuit layers 21 and 31 as a plurality of electrical connection pads 214, 215 and 11 200931458 314, 315 ° in the exposed electrical connection The surfaces of the pads 214, 215 and 314, 315 are formed to form a surface treatment layer 711, 712 and 721, 722, which may be selected from the materials described in Embodiment 1. Thus, the capacitive element provided by the present invention can be completed. Referring to FIG. 2D, the electric valley element includes: a first high dielectric material layer 23, 33, a second high dielectric material layer 43, an outer circuit layer (ie, circuit layer 21, 31), and an inner circuit layer (ie, a circuit layer). 22, 32), a plurality of conductive structures (ie, conductive vias 54), and insulating protective layers 61, 62. Wherein, the outer circuit layers 21, 31 are disposed on the surface of the first high dielectric material layers 23, 33, and have at least one pair of first high dielectric material layers 23, 33 spaced apart and 10 mutually parallel corresponding to the outer electrode plates 213, 313 . The inner circuit layers 22, 32 are disposed on both sides of the second high dielectric material layer 43, and are embedded between the first high dielectric material layers 23 and 33, and the inner circuit layer 2232 and the outer circuit layer 2131 are The first high dielectric material layers 23 and 33 are spaced apart, and the inner wiring layers 22, 32 have inner electrode plates 223, 323 which correspond in parallel to the outer electrode plates 213313. The conductive structure 54 extends through the 15th south dielectric material layer 23, 33, the second high dielectric material layer 43, and is electrically connected to the outer circuit layers 21, 31, the inner circuit layer 22, 32 » the insulating protective layer 61, 62 covers the surfaces of the capacitor setting layers 2 and 3, respectively, and the insulating protective layers 61, 62 have a pair of openings 611, 612 and 621, 622 to expose portions of the outer circuit layers 21, 3 which are electrically connected pads 214, 215 and 314,315. FIG. 2D shows another aspect of the embodiment 20, which differs from FIG. 2D in that only one side of the insulating protective layer 6 i has a pair of openings 611, 622, and the other side of the insulating protective layer 62 did not have pairs of openings. Further, reference is made to Fig. 2E-1, which is a top view of a panel of a capacitor element fabricated by the method of the present invention. As shown in Fig. 2E-1, the present invention can produce a plurality of capacitor units 12 200931458. Each of the capacitor units can be cut into capacitors. Therefore, as shown in FIG. 2E-2, the capacitor elements are formed on the entire surface of the capacitor, and the capacitor layers 2 and 3 are cut along with the insulating layers 61, 62. After that, a plurality of capacitor units can be formed. 5 ❹ 10 15 ❹ 20 From the above, it can be seen that the high dielectric metal sheet formed by pressing a high dielectric material by a thin metal plate is processed and processed by the method of the present invention, so that it can be easily fabricated into any shape and size. A capacitor element that is thin and has good uniformity (small variability) in size, thickness, electrode size, and capacitance to meet the requirements of today's electronic devices. Further, in the method for manufacturing a capacitor τ, which is provided by the present invention, there is no known disadvantage that the capacitance element has a high variability such as a capacitance value due to the use of ceramic high-temperature processing. In addition, the capacitor element provided by the invention can easily configure a plurality of pairs of electrodes on the same capacitor element, and the electrode pairs can be designed on the same side or opposite sides as needed, and a solder mask layer (such as green paint) which is easy to open is used. It can meet the requirements of insulation protection and electrical separation at the same time. The above-described embodiments are merely illustrative for the convenience of the description, and the scope of the claims of the present invention is intended to be based on the description of the application (4), and is not limited to the above embodiments. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1A to Fig. 1D are schematic cross-sectional views showing the process of the method of the first embodiment of the present invention. 2A to 2D are cross-sectional views showing the flow of the method of the second embodiment of the present invention. Fig. 2E-1 is a top view of the entire surface of the capacitor element of the second embodiment of the present invention. 2E-2 is a top view of a capacitor unit of a capacitor element according to Embodiment 2 of the present invention. 13 200931458 [Key component symbol description]
2,3 21,,22, 21.22.31.33 214,215,314,315 213,223,313,323 23.33 43 54 545 61,62 611,612,621,622 711,712,721,722 電容設置層 銅箔層 線路層 電性連接墊 電極板 第一高介電材料層 第二高介電材料層 導電通孔 導電盲孔 絕緣保護層 開孔 表面處理層2,3 21,,22,21.22.31.33 214,215,314,315 213,223,313,323 23.33 43 54 545 61,62 611,612,621,622 711,712,721,722 Capacitor-setting layer copper foil layer circuit layer electrical connection pad electrode plate first high dielectric material layer second high dielectric material layer Conductive Through Hole Conductive Blind Hole Insulation Protective Layer Opening Surface Treatment Layer