200402149 玖、發明說明： 【發明所屬之技術領域】 本發明係關於驅動 MOSFET(Metal-〇xide_Silic〇n Field Effect Transistor ;金屬氧化物矽場效電晶體）、IGBT (Insulated Gate Bipolar Transistor:絕緣閘雙極性電晶體） 等之閘極之閘極驅動電路。 【先前技術】 為了使MOSFET等半導體開關元件施行開關動作，需要使 用閘極驅動電路。圖5係表示以往之閘極驅動電路之例之電 路圖。圖5之閘極驅動電路係構成單片方式，如圖所示，例 如具有5個NPN型電晶體丨丨、12、13、14及15。電晶體^及 12採用達林頓式連接方式，電晶體14及15也採用達林頓式 連接方式。 ' 電晶體11係用於放大由未圖示之控制部供應之控制訊號 SC。電晶體12係依據電晶體丨丨所放大之控制訊號，使電源 知子T1契MOSFET1之閘極之間通電或斷電。又，電源電壓 係被供應至電源端子T1。 電晶體13係用於產生相當於使控制訊號8(：之相位反轉之 訊號之控制訊號SC/。 電晶體14係用於放大控制訊號SC/。電曰曰曰體15係依據電晶 體14所放大之控制訊號sc/，使接地端子與 之閘極之間通電或斷電。 、在圖5之閘極驅動電路中，控制部使控制訊號§〇成為高位 準（以下稱H”）時，可使基極被供應控制訊號sc之電晶體u 200402149 、13通電。集極連接於電源端子T1之電晶體11將控制訊號 SC放大而供應至電晶體12之基極。其結果，使電晶體12通 電，而將電源端子Τ1與MOSFET1之閘極電性連接。因此， MOSFET1之閘極被驅動成為’Ή”，而使MOSFET1通電。 在電晶體1 3通電之期間，電晶體1 3之集極電壓下降，使 控制訊號SC/成為低位準（以下稱”L")。使基極連接於電晶體 13之集極之電晶體14斷電，並使電晶體15也斷電。 控制部使控制訊號SC成為"L’1時，可使基極被供應控制訊 號SC之電晶體11、13斷電。利用電晶體11之斷電，使電晶 體12斷電，咬將以08?£丁1之閘極由電源端子Τ1電性切離。 相對地，利用電晶體1 3之斷電，電晶體1 3之集極電壓藉 電流源16而上升，使控制訊號SC/成為’’Η”。集極連接於 MOSFET1之閘極之電晶體14將控制訊號SC/放大而供應至 電晶體15之基極。被供應放大之控制訊號SC/之電晶體15通 電，將MOSFET1之閘極連接於接地端子，因此，MOSFET1 之閘極成為nL”，使MOSFET1斷電。 【發明所欲解決之問題】 但，在圖5之閘極驅動電路卻有如下之問題。即，有時被 認定在驅動對象之MOSFET1之閘極與源極之間，如圖所示 ，有寄生電容20，並連接著配線圖案等所形成之電感21。 在此情形下，MOSFET1斷電時，電感21會產生感應電壓， 而使電流以繞道方式經由寄生電容20而流通於MOSFET1之 閘極、源極之間。此電流會使MOSFET1之閘極電壓下降， 並使電晶體14之集極電位低於射極電位，而使寄生於電晶 200402149 體14之寄生電晶體23啟動。 圖6係寄生電晶體23之構成之說明圖。在半導體基板上形 成NPN型電晶體14時，例如在p型基板24之表面形成構成集 極之同雜貝/辰度之n +型之埋入層25，在基板以上形成之低 雜貝/辰度之n —型之磊晶層26，施行元件分離後，在磊晶層 26内形成P型之基極27、n+型之射極“、與連接於集極（= 入層25)之插塞29。寄生電晶體23係以電晶體14之基極”作 為射極，以構成電晶體14之集極之埋入層25作為基極，以 構成接地端子之基板24作為集極之PNp型電晶體。 寄生包晶體23通電時，使預備供應至電晶體14之基極之 控制戒唬sc/流通至接地端子。因此，電晶體14斷電而不再 將基極包/瓜供應至電晶體丨5之基極，故本來應通電之電晶 體15成為斷電狀態。而，在M〇SFET1之閘極電壓進一步低 於接地電壓時，以電晶體14及15之集極層作為射極之刪 型寄生電晶體30成為通電狀態。此寄生電晶體3〇之集極係 =一晶片上之磊晶層26,會導出其他PNP型電晶體之基極電 流及其他NPN型電晶體之集極電流等，因此，圖5之閘極驅 動電路引起錯誤動作之可能性相當大。 【發明内容】 本發明係為消除此種以往之問題而設計者，其目的在於 提供可充分防止錯誤動作之閘極驅動電路。 為了達成上述目的，本發明之第一觀點之閘極驅動電路 之特徵在於包含： 開關電路40,其係依據控制訊號，使驅動對象之電晶體 200402149 之間極契第_電遷源之間通電或斷電者； 驅動用雙極性雷a鲈 人外^ 电日日體51，其係形成於半導體基板上，包 含第一電極、筮 弟一笔極、及控制電極，依據前述控制訊號 放大供應至該控制兩搞 'ϋ 包極之訊唬而由該第二電極輸出者； 正“件53 ’其係連接於前述閘極與前述第一電極之間 、妨礙可生於月y述驅動用雙極性電晶體$ 1之寄生恭 通私，防止别述訊號繞道前述驅動用雙極性 允 制電極者；及 € Μ =關用雙極性電晶體52 ’其係形成於前述半導體基板上 \包含料於前述第二電極之控制電極、連接於前述閑極 =一电極、及連接於第二電麼源之第四電極，依據前述 被放=之訊號’與前述開關電路4〇互補地使該間極與該第 一電壓源之間通電或斷電者。 採用此種構成時’開關電路可使驅動對象之電晶體之閘 極與第-電壓源之間通電或斷電，開關用雙極性電晶體可 與開關電路互補地使第二電壓源與閑極之間通電或斷電。 在此’在開關電路切換閘極與第一電壓源之間通電或斷電 T 兀件也可妨礙寄生電晶體通電，故開關用雙極 t電晶體可使第二電壓源與閘極之間確實地通電或斷電， 藉以防止錯誤動作。 又，前述開關電路40也可形成於前述半導體基板上。 …又:前述驅動用雙極性電晶體51之周圍也可被形成於前 述半導體基板上之插塞69所包圍。 又，前述開關用雙極性電晶體52與前述整流元件53之周 200402149 圍也可被前述半導體基板上之磊晶生長層66所包圍，該磊 晶生長層66可被特定電壓所偏壓。 又，前述開關用雙極性電晶體52之周圍也可被形成於前 述半導體基板上之插塞89所包圍。 又，前述第一電壓源也可為供應電源電壓之電壓源，前 述第二電壓源也可為供應接地電壓之電壓源。 【實施方式】 以下’參照圖式說明有關本發明之實施形態之閘極驅動 電路。200402149 发明 Description of the invention: [Technical field to which the invention belongs] The present invention relates to driving MOSFET (Metal-〇xide_Silic〇n Field Effect Transistor; metal oxide silicon field effect transistor), IGBT (Insulated Gate Bipolar Transistor: insulated gate double Polarity transistor) and other gate drive circuits. [Prior Art] In order to perform switching operation of a semiconductor switching element such as a MOSFET, a gate driving circuit is required. Fig. 5 is a circuit diagram showing an example of a conventional gate driving circuit. The gate driving circuit of FIG. 5 is configured in a monolithic manner, as shown in the figure, for example, it has five NPN type transistors, 12, 13, 14, and 15. Transistors ^ and 12 use Darlington connection, and transistors 14 and 15 also use Darlington connection. 'Transistor 11 is used to amplify the control signal SC supplied by a control section (not shown). Transistor 12 is used to energize or de-energize the gates of power source T1 and MOSFET1 according to the control signal amplified by the transistor. The power supply voltage is supplied to the power supply terminal T1. The transistor 13 is used to generate a control signal SC / which is equivalent to a signal that reverses the phase of the control signal 8 (.) The transistor 14 is used to amplify the control signal SC /. The electric body 15 is based on the transistor 14 The amplified control signal sc / causes the ground terminal and its gate to be energized or de-energized. In the gate drive circuit of Fig. 5, when the control unit makes the control signal §〇 to a high level (hereinafter referred to as "H") The base can be energized by the transistor u 200402149,13 which supplies the control signal sc. The transistor 11 whose collector is connected to the power terminal T1 amplifies the control signal SC and supplies it to the base of the transistor 12. As a result, the The crystal 12 is energized, and the power terminal T1 is electrically connected to the gate of the MOSFET1. Therefore, the gate of the MOSFET1 is driven to 'Ή' and the MOSFET1 is energized. During the period when the transistor 13 is energized, the transistor 13 is The collector voltage drops to lower the control signal SC / (hereinafter referred to as "L"). The transistor 14 whose base is connected to the collector of the transistor 13 is turned off, and the transistor 15 is also turned off. When the control signal SC is " L'1, the base can be switched The transistors 11 and 13 of the supply control signal SC are de-energized. By using the de-energization of the transistor 11 to de-energize the transistor 12, the bite will be electrically cut off by the power terminal T1 with a gate of 08? 1. With the power off of transistor 13, the collector voltage of transistor 13 is increased by the current source 16, so that the control signal SC / becomes "Η". The transistor 14 whose collector is connected to the gate of MOSFET1 will control The signal SC / is amplified and supplied to the base of the transistor 15. The control signal SC / which is supplied with the amplified signal is energized, and the gate of the MOSFET1 is connected to the ground terminal. Therefore, the gate of the MOSFET1 becomes nL ", so that the MOSFET1 Power failure. [Problems to be Solved by the Invention] However, the gate driving circuit in FIG. 5 has the following problems. That is, it is sometimes identified between the gate and the source of the MOSFET 1 to be driven, as shown in the figure. It shows that there is a parasitic capacitor 20, and an inductor 21 formed by a wiring pattern, etc. is connected. In this case, when the MOSFET1 is powered off, the inductor 21 will generate an induced voltage, and the current will flow through the parasitic capacitor 20 through the parasitic capacitor 20 in a detour manner. Between the gate and source. This current will cause MOSFE The gate voltage of T1 drops, and the collector potential of transistor 14 is lower than the emitter potential, so that parasitic transistor 23 parasitic to transistor 200402149 body 14 starts. Figure 6 is an explanatory diagram of the structure of parasitic transistor 23 When forming an NPN type transistor 14 on a semiconductor substrate, for example, an n + type buried layer 25 constituting a homogeneous impurity / centigrade of the collector is formed on the surface of the p-type substrate 24, and a low impurity formed above the substrate The n-type epitaxial layer 26 is formed after the components are separated, and a P-type base 27 and an n + -type emitter are formed in the epitaxial layer 26 and connected to the collector (= layer 25). Of the plug 29. The parasitic transistor 23 is a PNp-type transistor with the base of the transistor 14 as the emitter, the buried layer 25 constituting the collector of the transistor 14 as the base, and the substrate 24 constituting the ground terminal as the collector. When the parasitic package crystal 23 is energized, the control of the base electrode to be supplied to the transistor 14 is controlled / scattered to the ground terminal. Therefore, the transistor 14 is powered off and no longer supplies the base package / melon to the transistor. 5 The base of the transistor, so the transistor 15 that should have been energized becomes a power-off state. When the gate voltage of MOSFET1 is lower than the ground voltage, the collector layer of the transistors 14 and 15 is used as the emitter. The parasitic transistor 30 is turned on. The collector of this parasitic transistor 30 = the epitaxial layer 26 on a wafer, which will lead to the base current of other PNP transistors and the collector current of other NPN transistors. Therefore, there is a high possibility that the gate driving circuit of FIG. 5 may cause erroneous operation. [Summary of the Invention] The present invention is designed to eliminate such a conventional problem, and an object thereof is to provide a gate driving that can sufficiently prevent the erroneous operation. To achieve this, The gate driving circuit of the first aspect of the present invention is characterized in that it includes: a switching circuit 40, which is based on a control signal, to switch on or off between the transistor 200402149 of the driving object and the power source The driving bipolar thunderbladder outer electric sun body 51, which is formed on a semiconductor substrate, includes a first electrode, a sibling pole, and a control electrode, and is amplified and supplied to the control two according to the aforementioned control signal. It is the second electrode that outputs the signal of the enclosing pole; the positive "piece 53 'is connected between the gate and the first electrode and prevents the bipolar transistor that can be born from driving. The $ 1 parasite respectfully communicates to prevent other signals from bypassing the aforementioned bipolar permitting electrode for driving; and € M = bipolar transistor 52 'which is formed on the aforementioned semiconductor substrate \ contains material on the aforementioned second electrode The control electrode, the fourth electrode connected to the above-mentioned free pole = an electrode, and the second electrode connected to the second electric source, make the intermediate electrode and the first electrode complementary to the first switching circuit 40 according to the signal “= Between a voltage source Or powered by. With this configuration, the 'switch circuit can be used to energize or de-energize the gate of the transistor to be driven and the first voltage source, and the bipolar transistor for switching can complement the switch circuit to make the second voltage source and the idler complementary. Power on or off. Here, when the switching circuit is switched on or off between the gate and the first voltage source, the T element can also prevent the parasitic transistor from being energized. Therefore, a bipolar t transistor for switching can be used to switch between the second voltage source and the gate. Make sure that the power is turned on or off to prevent malfunction. The switch circuit 40 may be formed on the semiconductor substrate. ... and the periphery of the driving bipolar transistor 51 may be surrounded by a plug 69 formed on the semiconductor substrate. In addition, the periphery of the switching bipolar transistor 52 and the rectifying element 53 may be surrounded by an epitaxial growth layer 66 on the semiconductor substrate, and the epitaxial growth layer 66 may be biased by a specific voltage. The periphery of the switching bipolar transistor 52 may be surrounded by a plug 89 formed on the semiconductor substrate. In addition, the first voltage source may be a voltage source that supplies a power supply voltage, and the second voltage source may also be a voltage source that supplies a ground voltage. [Embodiment] A gate driving circuit according to an embodiment of the present invention will be described below with reference to the drawings.
圖1係表示有關本發明之實施形態之閘極驅動電路之構 成圖。此閘極驅動電路係用於驅動圖1所示之MOSFET (Metal-Oxide-Silicon Field Effect Transistor)l之電路。 此閘極驅動電路係包含第一開關電路4〇、第二開關電路 50、及控制訊號變壓電路6〇。此等3個電路係形成於共通之 半導體基板上。 第一開關電路40係使電源電壓Vcc之供應源與M0SFET1 之閘極之間通電或斷電之電路，具有被達林頓式連接之2個 NPN型電晶體41及42。電晶體41及42之集極連接於電源電壓 Vcc之供應源。電晶體41之基極被供應來自未圖示之控制部 之控制訊號sc。電晶體41之射極連接於電晶體42之基極。 電晶體42之射極連接於M0SFET1i閘極。 第一開關私路50係用於與第一開關電路4〇互補地 (C_Plementarily)使接地端子與MOSFET1之閘極之間通電 或斷電之電路。第二開關電路5〇具有被達林頓式連接之2個 200402149 NPN型電晶體5卜52與二極體53。_型電晶體51之集極連 接於二極體53之陰極。二極體53之陽極與電晶體”之隼極 連接於M〇SFET1之閘極。電晶體51之射極連接於電晶= 之基極。電晶體5 2之射極連接於接地端子。 一 *電晶體51及二極體53具體上例如如圖2所示，係形成於半 導體基板上。即，如圖所示，在p型基板64之表面形成構 集極之高雜質濃度之n+型之埋人層65，在基板料上形成之 低雜質濃度之η—型之磊晶層66，施行元件分離後，在蟲曰 層66内形成Ρ型之基極67、η+型之射㈣、與連接於= (埋入層65)之插塞69。又，如圖所示，在蟲晶層_形成有 成為一極體53之陽極之15型半導體層7卜在半導體層71内带 成有成為二極體53之陰極型半導體層Μ。 ’ 在電晶體51，與圖6之構成之電晶體14同樣地，寄生著* 生電晶體23。又，在圖匕構成之電路中，也與圖: 同樣地寄生著以電晶體51及52之集極層作為射極之= 之寄生電晶體30。 主 寄生於採取圖2之構成之電晶㈣之寄生電晶 電晶體51之基極67作為射極，以構成電晶體51之隼極之埋 765作為基極’以構成接地端子之基⑽作為集極之PNP 電晶體。為I降低圖2之構成之寄生電晶體23之放大率， 如圖所不’插塞69係以包圍電晶體“之周邊之 又，在圖2之構成中’為了降低寄生電晶體23之放大率， Ϊ極體53及電^52係被配置成與其他元件之間保持-定 Ϊ以上之距離之狀態。 心 200402149 又，在圖2之構成中，如圖所示，二極體53係構成周圍被 磊晶層66包圍之狀態。又，電晶體52也構成周圍被磊晶層 66包圍之狀態。而，磊晶層66則被電源電壓Vcc或其他適合 於降低寄生電晶體30之放大率之適當電壓所偏壓。 控制訊號變壓電路60係施行控制訊號SC之變壓之電路。 控制訊號變壓電路60包含一端連接於電源電壓Vcc之供應 源之定電流源61、與集極連接於定電流源6 1之他端之NPN 型電晶體62。電晶體62之基極被供應控制訊號SC。電晶體 62之射極連接於接地端子。電晶體62之集極連接於第二開 關電路50之電晶體51之基極。而，電晶體62之集極成為輸 出反轉控制訊號SC之相位之控制訊號SC/之端。 又，如圖1所示，在驅動對象之Μ Ο S F E T1之閘極與源極之 間存在有寄生電容20。又，在MOSFET1之源極與接地端子 之間連接形成配線等之電感2 1。 其次，說明本實施形態之閘極驅動電路之動作。 控制部使控制訊號SC成為高位準（以下稱”Ηπ)時，可使基 極被供應控制訊號SC之電晶體41、62通電。集極被供應電 源電壓Vcc之電晶體41將控制訊號SC放大而供應至電晶體 42之基極。於是，使電晶體42通電，而將電源電壓Vcc供應 至 MOSFET1之閘極。其結果，MOSFET1之閘極被驅動成 為”11’’而使MOSFET1通電。 在電晶體62通電之期間，電晶體62之集極電壓下降，使 控制訊號SC/成為低位準（以下稱’’L1’）。因此，使基極連接於 電晶體62之集極之電晶體51斷電，並使電晶體52也斷電。 200402149 控制部使控制訊號SC成為nL’’時，可使基極被供應控制訊 號SC之電晶體41及62斷電。 利用電晶體41之斷電，使電晶體42也斷電，其結果，將 MOSFET1之閘極由電源電壓Vcc之供應源電性切離。 相對地，使電晶體62斷電時，定電流源61使電晶體62之 集極電壓上升，使控制訊號SC/成為ΠΗ”。電晶體51將此控 制訊號SC/放大而供應至電晶體52之基極。被供應放大之控 制訊號SC/之電晶體52通電，將MOSFET1之閘極連接於接地 端子，其結果，MOSFET1之閘極成為’’L’·，使MOSFET1斷 電。 又，MOSFET1斷電時，電感21會產生感應電壓，而使電 流以繞道方式經由寄生電容20而流通於MOSFET1之閘極、 源極之間。此電流會使MOSFET1之閘極電壓下降。但，因 MOSFET1之閘極與電晶體51之集極之間連接有二極體W， 故可妨礙寄生電晶體23通電。其結果，可防止供應至電晶 體5 1之基極之控制訊號SC/流至接地端子，確實將基極電流 供應至電晶體52。由於電晶體52之集極之電位低於電晶體 52之射極之電位，可使電晶體52施行反放大率動作（反電晶 體動作），而使基極電流之放大率倍之電流流至電晶體52之 集極一射極間。 在圖1之閘極驅動電路之動作中，如圖3所示，電晶體5 2 施行反放大率動作時（TERM1)，MOSFET1之閘極電壓V不會 低於電晶體52之飽和電壓VCE(SAT)，因此，寄生電晶體30 也不會通電。另外，由於採行將寄生電晶體30之電流放大 200402149 率和力抑制在低值之設計，故可防止其他pNp型電晶體之錯 誤動作。 又，因電晶體51之集極與則咖以之閘極之間連接有二 極體53，電晶體51之基極電流不會流至接地端子。因此， 可確貝將電晶體5 1之基極電流供應至電晶體52之基極，使 電晶體52確實通電。 又’因電晶體51被插塞所包圍’可將寄生電晶體23之放 大率保持於低值，因此，此插塞也有使電晶體以基極電 流難以流過接地端子之機能。 又，電晶體52之周圍受到被施加偏壓之磊晶層所包圍， 其結果，可將寄生電晶體3〇之電流放大率保持於低值，因 此，圖1之閘極驅動電路因寄生電晶體3〇之通電而引起錯誤 動作之危險性較低。 —又’在實施本發明之際，可考慮採行種種形態，並不限 定於上述實施形態。例如’在圖i之閘極驅動電路中，也可 將NPN型電晶體變更為PNp型電晶體，且可使二極體μ之極 性及電源電壓Vcc之極性反轉。又，圖i之閘極驅動電路也 可利用IGBT作為㈣對象之電晶體，以取rm〇sfet。 /又’如圖4所示，電晶體52也可被插塞所包圍。電晶的 採用此種構成時’可將寄生電晶體3〇之放大率保持於低值 又圖4所不之電晶體52係由形成於P型基板64表面之n + 型之埋入層85形成之集極、在元件分離後形成於基板64上 之上述磊晶層66内之P型之基極87、及n+型之射極⑽所構 成。而，如圖所示，插塞89係以包圍電晶體52之周邊之方 200402149 式形成。 【發明之效果】 如以上所詳述’依據本發明，可實現充分防止錯誤動作 之閘極驅動電路。 【圖式簡單說明】 圖1係表示有關本發明之實施形態之閘極驅動電路之 成之電路圖。 圖2係電晶體及二極體之剖面圖。 圖3係圖1之閘極驅動電路之動作之說明圖 圖4係電晶體之變形例之剖面圖。 圖5係以往之閘極驅動電路之電路圖。 圖6係寄生電晶體之構成說明用之剖面圖 圖式代表符號說明FIG. 1 is a diagram showing a configuration of a gate driving circuit according to an embodiment of the present invention. This gate driving circuit is a circuit for driving a MOSFET (Metal-Oxide-Silicon Field Effect Transistor) shown in FIG. 1. The gate driving circuit includes a first switching circuit 40, a second switching circuit 50, and a control signal transformer circuit 60. These three circuits are formed on a common semiconductor substrate. The first switch circuit 40 is a circuit for energizing or de-energizing the supply source of the power supply voltage Vcc and the gate of the MOSFET1, and has two NPN type transistors 41 and 42 connected by Darlington. The collectors of the transistors 41 and 42 are connected to a supply source of the power voltage Vcc. The base of the transistor 41 is supplied with a control signal sc from a control section (not shown). The emitter of the transistor 41 is connected to the base of the transistor 42. The emitter of the transistor 42 is connected to the MOSFET1i gate. The first switch private circuit 50 is a circuit for complementary or complementary to the first switch circuit 40 (C_Plementarily) to energize or de-energize the ground terminal and the gate of the MOSFET1. The second switching circuit 50 has two 200402149 NPN type transistors 52 and 52 connected by Darlington. The collector of the _-type transistor 51 is connected to the cathode of the diode 53. The anode of the diode 53 and the transistor "is connected to the gate of MOSFET 1. The emitter of transistor 51 is connected to the base of transistor =. The emitter of transistor 5 2 is connected to the ground terminal. * Specifically, the transistor 51 and the diode 53 are formed on a semiconductor substrate as shown in FIG. 2, that is, as shown in the figure, an n + type having a high impurity concentration is formed on the surface of the p-type substrate 64. The buried human layer 65 is a η-type epitaxial layer 66 with a low impurity concentration formed on the substrate. After the element is separated, a P-type base 67 and a η + -type emitter are formed in the insect layer 66. And a plug 69 connected to = (embedded layer 65). Also, as shown in the figure, a 15-type semiconductor layer 7 forming an anode of a polar body 53 is formed in the worm crystal layer. A cathode-type semiconductor layer M that becomes a diode 53 is formed. In the transistor 51, the * transistor 23 is parasitic in the same way as the transistor 14 of the structure of FIG. 6. In the circuit of the figure, It is also parasitic: the parasitic transistor 30 with the collector layer of the transistors 51 and 52 as the emitter is parasitic. The base 67 of the parasitic transistor 51 of the crystal is used as the emitter, and the buried electrode 765 which is the constituent of the transistor 51 is used as the base, and the base of the ground terminal is used as the collector of the PNP transistor. The magnification of the parasitic transistor 23 of the structure of FIG. 2 is shown in FIG. 2. The plug 69 is to surround the periphery of the transistor. In the structure of FIG. 2, to reduce the magnification of the parasitic transistor 23, Ϊ The pole body 53 and the electric body 52 are arranged in a state where a distance of more than or equal to a predetermined distance is maintained from other elements. Heart 200402149 In the structure of FIG. 2, as shown in the figure, the diode 53 constitutes a state surrounded by an epitaxial layer 66. The transistor 52 is also surrounded by the epitaxial layer 66. The epitaxial layer 66 is biased by a power supply voltage Vcc or another suitable voltage suitable for reducing the magnification of the parasitic transistor 30. The control signal transformer circuit 60 is a circuit that performs a transformer of the control signal SC. The control signal transformer circuit 60 includes a constant current source 61 whose one end is connected to a supply source of the power supply voltage Vcc, and an NPN transistor 62 which is connected to the collector at the other end of the constant current source 61. The base of the transistor 62 is supplied with a control signal SC. The emitter of the transistor 62 is connected to a ground terminal. The collector of the transistor 62 is connected to the base of the transistor 51 of the second switching circuit 50. Further, the collector of the transistor 62 becomes the terminal of the control signal SC / which outputs the phase of the inverted control signal SC. As shown in FIG. 1, a parasitic capacitance 20 is present between the gate and the source of the MOSFET MOSFET S1 T1 to be driven. An inductor 21 is formed between the source of the MOSFET 1 and the ground terminal to form a wiring or the like. Next, the operation of the gate driving circuit of this embodiment will be described. When the control unit sets the control signal SC to a high level (hereinafter referred to as "Ηπ"), the base 41 is energized by the transistors 41 and 62 to which the control signal SC is supplied. The collector is amplified by the transistor 41 which is supplied with the power supply voltage Vcc to amplify the control signal SC. The transistor 42 is supplied to the base of the transistor 42. Then, the transistor 42 is energized, and the power supply voltage Vcc is supplied to the gate of the MOSFET 1. As a result, the gate of the MOSFET 1 is driven to "11" and the MOSFET 1 is energized. While the transistor 62 is energized, the collector voltage of the transistor 62 decreases, so that the control signal SC / becomes a low level (hereinafter referred to as' 'L1'). Therefore, the transistor 51 whose base is connected to the collector of the transistor 62 is turned off, and the transistor 52 is also turned off. 200402149 When the control section makes the control signal SC nL '', the transistors 41 and 62 whose base is supplied with the control signal SC can be powered off. The transistor 42 is also de-energized by the power-off of the transistor 41. As a result, the gate of the MOSFET 1 is electrically cut off from the supply source of the power voltage Vcc. On the other hand, when the transistor 62 is powered off, the constant current source 61 increases the collector voltage of the transistor 62 to make the control signal SC / become ΠΗ. ”The transistor 51 amplifies the control signal SC / and supplies it to the transistor 52. The base 52. The amplified control signal SC / transistor 52 is energized, and the gate of MOSFET1 is connected to the ground terminal. As a result, the gate of MOSFET1 becomes "L" ·, which turns off MOSFET1. Also, MOSFET1 When the power is turned off, the inductor 21 generates an induced voltage, so that the current flows between the gate and the source of MOSFET1 in a detour manner through the parasitic capacitor 20. This current will cause the gate voltage of MOSFET1 to drop. However, because of the MOSFET1 A diode W is connected between the gate and the collector of the transistor 51, so that the parasitic transistor 23 can be prevented from being energized. As a result, the control signal SC / supplied to the base of the transistor 51 can be prevented from flowing to the ground terminal. The base current is indeed supplied to the transistor 52. Since the potential of the collector of the transistor 52 is lower than the potential of the emitter of the transistor 52, the transistor 52 can perform an inverse magnification action (anti-transistor action), and Double the magnification of the base current The current flows between the collector and the emitter of the transistor 52. In the operation of the gate driving circuit of FIG. 1, as shown in FIG. 3, when the transistor 5 2 performs the inverse magnification operation (TERM1), the gate of the MOSFET1 The voltage V will not be lower than the saturation voltage VCE (SAT) of the transistor 52, so the parasitic transistor 30 will not be energized. In addition, since the current of the parasitic transistor 30 is amplified by 200402149, the rate and force are suppressed to a low value. The design can prevent the wrong operation of other pNp-type transistors. In addition, since the collector of the transistor 51 and the gate of the transistor 51 are connected with the diode 53, the base current of the transistor 51 will not flow to The ground terminal. Therefore, it can be confirmed that the base 51 of the transistor 51 is supplied to the base of the transistor 52, so that the transistor 52 is indeed energized. Also, because the transistor 51 is surrounded by the plug, the parasitic transistor can be The magnification of 23 is kept low. Therefore, this plug also has the function of making it difficult for the transistor to pass the ground current through the ground terminal. Also, the periphery of the transistor 52 is surrounded by an epitaxial layer that is biased. As a result, the current amplification factor of the parasitic transistor 30 can be maintained at Therefore, the risk of erroneous operation due to the energization of the parasitic transistor 30 in the gate driving circuit of FIG. 1 is low.-Also, in the implementation of the present invention, various forms can be considered and are not limited to The above embodiment. For example, in the gate driving circuit of FIG. I, an NPN transistor can be changed to a PNp transistor, and the polarity of the diode μ and the polarity of the power supply voltage Vcc can be reversed. The gate driving circuit of Fig. I can also use IGBT as the transistor of the target to obtain rmsfet. / Again, as shown in FIG. 4, the transistor 52 can also be surrounded by a plug. In the construction, the magnification of the parasitic transistor 30 can be kept low and the transistor 52 shown in FIG. 4 is a collector formed by an n + -type buried layer 85 formed on the surface of the P-type substrate 64. A P-type base electrode 87 and an n + -type emitter electrode 内 formed in the above-mentioned epitaxial layer 66 on the substrate 64 after element separation are formed. As shown in the figure, the plug 89 is formed in a shape of 200402149 to surround the periphery of the transistor 52. [Effects of the Invention] As described in detail above, according to the present invention, a gate driving circuit capable of sufficiently preventing an erroneous operation can be realized. [Brief description of the drawings] Fig. 1 is a circuit diagram showing the construction of a gate driving circuit according to an embodiment of the present invention. Figure 2 is a sectional view of a transistor and a diode. Fig. 3 is an explanatory diagram of the operation of the gate driving circuit of Fig. 1. Fig. 4 is a sectional view of a modified example of the transistor. FIG. 5 is a circuit diagram of a conventional gate driving circuit. Figure 6 is a sectional view for explaining the structure of a parasitic transistor
MOSFET 16 20 21 30 40 50 51 52 53 60 電流源 寄生電容 電感 NPN型寄生電晶體 第一開關電路 第二開關電路 驅動用電晶體 開關用雙極性電晶體 二極體 控制訊號變壓電路 -14- 200402149 61 定電流源 66 蠢晶生長層 71 半導體層 11-15 、 41， 42 NPN型電晶體 23, 30 寄生電晶體 24, 27, 64 P型基板 25, 65, 85 n+型之埋入層 26, 66 n_型之蠢晶層 28, 68, 88 n+型之射極 29, 89 插塞 51，52, 62 電晶體 67, 87 P型之基極 GND 接地端子 SC, SC/ 控制訊號 T1 電源端子 Vcc 電源電壓 -15-MOSFET 16 20 21 30 40 50 51 52 53 60 Current source parasitic capacitance inductance NPN parasitic transistor first switching circuit second switching circuit driving transistor switch bipolar transistor diode control signal transformer circuit -14- 200402149 61 Constant current source 66 Stupid crystal growth layer 71 Semiconductor layer 11-15, 41, 42 NPN type transistor 23, 30 Parasitic transistor 24, 27, 64 P-type substrate 25, 65, 85 n + type buried layer 26 , 66 n_ type stupid crystal layer 28, 68, 88 n + type emitter 29, 89 plug 51, 52, 62 transistor 67, 87 P type base GND ground terminal SC, SC / control signal T1 power supply Terminal Vcc supply voltage -15-