TW200400358A - Semiconductor integrated circuit with built-in self-test function and system including the same - Google Patents
Semiconductor integrated circuit with built-in self-test function and system including the same Download PDFInfo
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- TW200400358A TW200400358A TW091135268A TW91135268A TW200400358A TW 200400358 A TW200400358 A TW 200400358A TW 091135268 A TW091135268 A TW 091135268A TW 91135268 A TW91135268 A TW 91135268A TW 200400358 A TW200400358 A TW 200400358A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 30
- 238000012360 testing method Methods 0.000 title claims abstract description 21
- 230000002093 peripheral effect Effects 0.000 claims abstract description 35
- 238000002405 diagnostic procedure Methods 0.000 claims description 18
- 238000003745 diagnosis Methods 0.000 claims description 16
- 230000005856 abnormality Effects 0.000 claims description 6
- 238000012545 processing Methods 0.000 claims description 6
- 238000004092 self-diagnosis Methods 0.000 claims description 5
- 238000001514 detection method Methods 0.000 claims description 4
- 208000012661 Dyskinesia Diseases 0.000 claims description 2
- 230000000052 comparative effect Effects 0.000 claims description 2
- 239000012536 storage buffer Substances 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 8
- 208000003251 Pruritus Diseases 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 206010011469 Crying Diseases 0.000 description 3
- 238000005259 measurement Methods 0.000 description 2
- 241001674044 Blattodea Species 0.000 description 1
- PEDCQBHIVMGVHV-UHFFFAOYSA-N Glycerine Chemical compound OCC(O)CO PEDCQBHIVMGVHV-UHFFFAOYSA-N 0.000 description 1
- 241000257303 Hymenoptera Species 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000002159 abnormal effect Effects 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 210000004556 brain Anatomy 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 235000013399 edible fruits Nutrition 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 210000000952 spleen Anatomy 0.000 description 1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3187—Built-in tests
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31703—Comparison aspects, e.g. signature analysis, comparators
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318566—Comparators; Diagnosing the device under test
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Abstract
Description
200400358 五、發明說明（1) [發明所屬之技術領域] 本發明係有關於内藏有自我診測功能之半導體積體電 路及具有該電路之系統。 [先前技術] 在習知之微電腦（m i cro compu t er )上，對於伴隨著來 自外部之輸入與輸出之診測，使用了半導體診測器 (t e s t e r )來執行診測，但是隨著近年來微電腦之高速化， 因高速而形成高價之測試器之必要，所以造成了診測 變高。 因此’有構成了將診測電路設置在微電腦内部之内 有自我診測功能之半導體積體電路之情況。 「發明内容] [發明所欲解決的課題] 因為習知之内藏有自我診測功能之半導體積體電路， 如以上地來構成，所以造成了被設置在微電腦内部之診 電路之規模之問題。為了對於微電腦之邏輯充分地執行吟 測，必須有大的診測電路，此部分形成了微電腦之構= 形化之問題。 人 而在製品出貨之後，有所謂的被組裝在系統後之 腦之診測上困難之課題。 n电 本發明係為了解決如以上之課題而發明，所以其目的， 於獲得一種藉由追加小規模之電路s對於周邊功能方在 忐夠自我診測，以實現診測成本之降低、與製品上之故 保險（faU safe)之内藏有自我診測功能之半導體積體電早200400358 V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to a semiconductor integrated circuit with a built-in self-diagnostic function and a system having the same. [Prior art] On conventional microcomputers (micro computer), semiconductor testers (testers) are used to perform diagnostic tests for diagnostic tests accompanied by external inputs and outputs. However, in recent years, microcomputers The increase in speed has necessitated the formation of a high-priced tester due to the high speed, which resulted in higher diagnostic tests. Therefore, a semiconductor integrated circuit having a self-diagnostic function may be included in a microcomputer, which is incorporated in the microcomputer. "Summary of the Invention" [Problems to be Solved by the Invention] Since the conventional semiconductor integrated circuit with a self-diagnostic function built therein is constructed as described above, it causes a problem of the scale of the diagnostic circuit installed inside the microcomputer. In order to fully perform the measurement of the logic of the microcomputer, there must be a large diagnostic circuit. This part forms the problem of the structure of the microcomputer = the shape. After the product is shipped, there is a so-called brain that is assembled behind the system. Difficult problems in diagnosis and testing. N The present invention is invented in order to solve the above problems, so the purpose is to obtain a self-diagnosis for peripheral functions by adding small-scale circuits. Reduced cost of diagnosis and testing, and semiconductor integrated circuit with self-diagnostic function built into faU safe
21〇3-5352-PF(Nl).ptd 第6頁 200400358 五、發明說明（2) 路及具有該電路之系統^ [用以解決課題的手段] 有關本發明之内藏有自我診蜊功能、… 路，係在欲診測周邊功能區塊之輪=之半導體積體電 區塊之輸出之期待值，設定至蟑暫：？/將對於周邊功‘ =為輸入淳之值，設定至痒方:以時將使輪」 至棒暫存器之期待值，來執行診 而I之值，與被設； 路，：發明之内藏有自我診測功 路，：關本發明之内藏有自我珍；：能中斷處理。 外部據比較器之診測叛定結果，從外部::積:出電至 路，：：二”之内藏有自我診測 至 痒方4;數之輸入出痒同時執行診測體； 複數之輪人屮μ 根據比較許可信號，來仏予對^ 有：同時診測之許可或不許可。 路’係對應輸入出埠之各ϋ診測功能之半導體積體電 對於複數之輸入出】ίί暫存器來被設置，⑥包括了在 ?可信號，將值再载；：執行診測之情況下’根據比較 益之再載入暫存器。t之輸入出埠之所對應之埠暫存 有關本發明之向 ♦ 體電路之系統，内藏有内藏有自我診測功能之半導體積 我診測功能之半導體積體電路被 20040035821〇3-5352-PF (Nl) .ptd Page 6 200400358 V. Description of the invention (2) Circuit and system with the circuit ^ [Means for solving problems] The self-diagnosis function is built in the invention The road is the expected value of the output of the semiconductor integrated electric block in the round of the peripheral functional block to be diagnosed and tested, and it is set to cock temporarily:? / Will be for the peripheral power '= the value of the input Chun, set to the itchy side: the time will make the round "to the expected value of the stick register, to perform the diagnosis and the value of I, and is set; road, within the invention There is a self-diagnostic and measurable power path: The self-esteem is hidden in the invention; the processing can be interrupted. According to the results of the external diagnosis of the comparator, the self-diagnostic test to the itch square 4 is contained in the external ::: product: power to the road, and the input of the number is performed at the same time to perform the test; The person in the wheel 根据 μ according to the comparison permission signal, to give the right ^ Yes: simultaneous diagnosis is permitted or not. Road 'is the corresponding input and output of the semiconductor integrated circuit for each diagnostic function of the input and output ports] ί Register is set, ⑥ includes the signal that can be reloaded when the signal is available ;: In the case of performing a diagnostic test, the register is reloaded according to the comparative advantage. The input port of t corresponds to the corresponding port. Temporary storage system related to the present invention, a semiconductor integrated circuit with a built-in semiconductor integrated self-diagnostic and self-diagnostic function is included.
組名至系’统’在電源投入後成重置後、或異常判定 診測時對於本身具有之周邊功能方塊來執行診測，而2 異常動作之早期測出和異常測出時之動作停止或上屏二:丨 程式’貫現了通信號之輸出或藉由 障保險功能。 ^ 、二組合之故 [實施方式] 實施例1 、 第1圖’係表示根攄本發明之實施例1之内藏有自.吟 測功能之半導體積體電路之構造圖。圖中，1為焊墊（γ 0 =)’2為路逕選擇開Μ，3為埠方向暫存器，4為埠暫^ 态’ 5為比較器。然而，藉由埠方向暫存器3、埠暫存= 4、及比較器5，來構成輸入出埠。 口口 6為周邊功能區塊，7為輸入信號線（璋輸入信縈 A、Β表示路徑。 、 第2圖，係表示根據本發明之實施例1之内藏有自我玲 測功能之半導體積體電路之動作之時序圖。 ν 接著，關於動作說明。 >、第3圖、第4圖’係表示習知之半導體積體電路之課題 如第3圖所不地，在追勒产。σ > . , Ah r- /. 旱暫存姦4和周邊功忐區塊6被連 接至相同之塾* 1日守，以制·+自^ 山的/ 如#闲I 乂對蜂暫存器4之寫入指令，能夠藉 由路徑A，封於周邊功能卩地e — ΤΜ、 1 I 月匕£塊6，來給予輸入（第4圖之 I N )。相反地’稭由從j：阜爸十 处 暫存器4讀出，能夠藉由路徑B， 此時之周邊功能區塊6之齡山 ® ^ ^ _ 輸出，經由焊墊1，當作埠暫存器The group name is “system”. After resetting after power is turned on, or when the abnormality is diagnosed and tested, the peripheral function blocks that it has are used to perform the diagnosis and test. 2 The early detection of abnormal movements and the operation stops when abnormalities are detected. Or on the second screen: The program realizes the output of the communication signal or through the barrier insurance function. ^ The reason for the two combinations [Embodiment] Embodiment 1 and FIG. 1 'are structural diagrams of a semiconductor integrated circuit having a self-contained measurement function according to Embodiment 1 of the present invention. In the figure, 1 is a pad (γ 0 =) ’2 is a path selection open M, 3 is a port direction register, and 4 is a port temporary state 5 is a comparator. However, the input and output ports are configured by the port direction register 3, the port register = 4, and the comparator 5. Mouth 6 is a peripheral function block, and 7 is an input signal line (璋 Input signals 萦 A, B represent paths., And FIG. 2 is a diagram showing a semiconductor product with a built-in self-test function according to Embodiment 1 of the present invention. Timing chart of the operation of the body circuit. Ν Next, the operation will be explained. ≫, FIG. 3, and FIG. 4 'show the problems of the conventional semiconductor integrated circuit as shown in FIG. >., Ah r- /. Drought temporary storage 4 and the surrounding function block 6 are connected to the same 塾 * 1 day guard, to control · + since ^ of the mountain / such as # 闲 I 乂 temporary storage of bees The writing instruction of the device 4 can be given an input by path A, sealed to the peripheral functions e-TM, 1 I, and 6 (IN in FIG. 4). Conversely, 'from the j: Fu Da's ten temporary registers 4 can be read out, and can be output by Path B. At this time, the peripheral function block 6's Lingshan® ^ ^ __ is output through pad 1 as a port register.
2103-5352-PF(Nl).ptd2103-5352-PF (Nl) .ptd
$ 8頁 200400358 五、發明說明（4) _____ 4之輸入，從輸入信號線來讀出，（此 已寫入之值，而不因讀出之值來更新）、，，埠暫存器4保持 邊功能區塊6之輸出（第4圖之〇υτ)。 所以能夠讀出周 但是，在對於周邊功能區塊6之輸入应 之輸出，因為使用相同的埠暫存器4別戶二、周邊功能區塊6 功能區塊6之輸人與輸出，同時作診測广:f f對於周邊 功能區塊6之輸出值，在來自埠暫存哭 就是說，周邊 謂無法診測之問題。 崎出期間’有所 在此，如第1圖所示地，設置了·· 來，嫩出键入痒或輸出璋之蜂方向破二 及按妝被设定至埠方向暫存器3的值， ::::，4值埠暫， ίΐ in 的期待值與從周邊功能區塊6所 f刖出之值’而執行診測判斷之比較器5。 女此地’在想對於周邊功能區塊6來給予輸入之時， 於向暫存器3上，將輪入出埠設定為輸出埠之值，、例 如設=成π 0 ” ，而從路徑A，將被設定至埠暫存器4之值， I由丈干墊1，給予至周邊功能區塊β。此時，比較器5因為 埠方向暫存器3之設定，所以成為比較不許可。 =在欲診測周邊功能區塊6之輸出之時，將對於其周 ^功能區塊6之輸出之期待值，設定至埠暫存器4，同時地 於=1向暫存器3上，將輸入出埠設定為輸入埠之值，例 f °又定成1 "，而以比較器4來比較從路徑B，由周邊功能 區塊6所輸出之經過焊墊1之值，和被設定至埠暫存器4之 2103-5352-PF(\：}.nld 第9頁 200400358 五 發明說明（5) 期 待值’來執行診測判斷。此時，比較器5因為埠方向暫 存器3之1"設定，所以成為比較許玎。 如以上地，根據本實施例丨，如第2圖所示地，藉由設 定至埠方向暫存器13之值，將寫入炱埠暫存器4之值，分成 對周邊功能區塊6之輸入值，與周邊功能區塊6之 期待值，而周邊功能區塊6之輸出值和期待值⑴值之 藉著=用比較器5來經常比較，而僅能夠於來 相等， 暫Ϊ t之讀出期㈤’來比較周邊功能區塊6之於之山可之埠 以月^解決所謂的無法同時診測輪入與輸，出值，所 ，於根據淳方向暫存器3之比較器5 問題。 使用：用表示周邊功能區塊6之輸出之信 ’亦可同時 貝方也例2 制。 本實施例2，係在根據上述每#办丨1夕— 功能之半導触并踔電路φ K %例1之内藏有自典' m : 積體？ 使根據比較器5之' 我診測 果成為中斷要求，來執行錯誤處理，以作杉剛判定結 如此地，能夠將錯誤處理二斷處理。 所以，有效率地執行診測判定作為中吨處理，來處理， 貫施例3 功能二例3 ’係在根據上述實施例…$ 8 pages 200400358 V. Description of the invention (4) _____ 4 The input is read from the input signal line (the value that has been written, not updated by the read value). Keep the output of side function block 6 (0υτ in Figure 4). Therefore, it is possible to read the week. However, the input to the peripheral function block 6 should be output because the same port register 4 is used for the second household 2 and the peripheral function block 6 for the input and output of the function block 6. Diagnose and test wide: ff For the output value of peripheral function block 6, crying temporarily from the port means that the peripheral said that it cannot diagnose and test. During the Kizumi period, there is something here, as shown in Figure 1, it is set to come out, tenderly type the itch or the output of the bee direction break 2 and press the makeup is set to the value of the port direction register 3, ::::, 4-valued port temporarily, the comparator 5 that executes diagnosis and judgment based on the expected value of ΐ in and the value f f from the peripheral function block 6 '. When women want to give input to the peripheral function block 6, set the round-in and port-out to the value of the output port to the register 3, for example, set = π 0, and from path A, Will be set to the value of the port register 4, I will be given to the peripheral function block β from the dry pad 1. At this time, the comparator 5 will be relatively disallowed because of the setting of the port direction register 3. = When the output of peripheral function block 6 is to be diagnosed, the expected value of the output of its peripheral function block 6 is set to the port register 4, and at the same time, it is set to = 1 to register 3, and The input and output ports are set to the value of the input port. For example, f ° is set to 1 again, and the value from path B, which is output from peripheral function block 6 and passed through pad 1 is compared with comparator 4, and is set. 2103-5352-PF (\:}. Nld to port register 4 Page 9 200400358 Fifth invention description (5) Expected value 'to perform diagnosis and judgment. At this time, comparator 5 because of port direction register 3 No. 1 " setting, so it becomes a little bit more. As above, according to this embodiment, as shown in Figure 2, by setting to the port direction register 1 The value of 3 will be written into the port register 4 and divided into the input value to the peripheral function block 6, and the expected value of the peripheral function block 6, and the output value and expected value of the peripheral function block 6. By the value of =, the comparator 5 is used to make frequent comparisons, and can only be equal to each other. Temporarily read the period Ϊ t to compare the peripheral function block 6 to the natural port in order to solve the so-called inability. Simultaneously check the input and output of the wheel, the value of the output, so the problem of the comparator 5 in the register 3 according to the direction of the Chun. Use: Use the letter that indicates the output of the peripheral function block 6 'Also can be used in the same way as in Example 2 The second embodiment is based on each of the above-mentioned operations. The semi-conductor contact parallel circuit φ K% of the function is included in Example 1. 'M: Integral? The diagnosis result becomes an interrupt request, and the error processing is executed to make Sugi-san's judgment. In this way, the error processing can be processed in two ways. Therefore, the diagnosis diagnosis is efficiently executed as a medium ton processing. Function 2 Example 3 'is based on the above embodiment ...
‘體積體電路中，脾# i 减有自我A 果，從外邮枝 ^ d 將根據比較器5之故、日，伐％剛 接腳，輸出至外部。 ％〉則判定結 如此地，能夠從外却# 出至本裴置以外。 腳，將輸出診剛判定結 實施例4 ，輪 200400358 五、發明說明（6) 本實施例4，係在根據上迷_ 功能之半導體積體電路中，在對貫施例1之内藏有自我診測 之輸入出埠，同時執行診測之法同時存取之複數的 3之值外，並根據比較許可信號况下，除了埠方向暫存哭 入出蟑，同時診測之許可或不^來給予對於之複數的輸 如此地，僅在埠方向暫存哭 埠，無法同時執行診測，但是因對於複數的之輸入出 給予對於複數的輸人出4，同日+ =據比較許可信號，來 以能夠對於複數的輸入出埠，二=之許可或不許可，所 實施例5 τ執行診測。 第5圖，係表示根據本發明 測功能之半導體積體電路之構造貫施例5之内藏有自我診 (reload)暫存器。其他的構造和圖中，8為再載入 接著，關於動作，作說明。汽知例4相等。 於上述實施例4所表示的内 體積體電路中，對應輪入出 我衫剛功能之半導 較許可信號，設置了將事先設定埠暫存為4，而根據比 複數的輸入出璋之所對應之:，載入值’再載入至之 在對於複數的之輪入出蟓，二為4之再載入暫存器8。 因為根據比較許可信號，同時執行診測之情況下， 輸入出埠之所對應之埠暫存琴入值，同時載入至複數的‘In the volume body circuit, the spleen # i minus has the self-A effect, and the external branch ^ d will be output to the outside according to the reason of the comparator 5, the day, and the%. %> Judges that in this way, it is possible to go out from outside but # outside of this Pei Zhi. The output of the foot will be judged in the fourth embodiment, and the round is 200400358. V. Description of the invention (6) This fourth embodiment is a semiconductor integrated circuit according to the above function, and is contained in the opposite embodiment 1. Self-diagnostic test input and output port, while the diagnostic test method simultaneously access the value of the plural 3, and according to the comparison permission signal condition, in addition to the temporary storage of crying in and out of the cockroach in the direction of the port, the simultaneous diagnostic test permission or not In order to give a plural number of inputs, in this way, the crying port is temporarily stored in the port direction, and the diagnostic test cannot be performed at the same time, but because the plural number of inputs is given to the plural number of inputs, the same day + = according to the comparison permission signal, In order to enable a plurality of input and output ports, whether the two = s are permitted or disallowed, a diagnosis test is performed in Embodiment 5 τ. Fig. 5 is a diagram showing a structure of a semiconductor integrated circuit according to the present invention, and a self-diagnosis (reload) register is built in the fifth embodiment. In other structures and figures, 8 is reloading. Next, the operation will be described. Steam knowledge example 4 is equal. In the inner volume circuit shown in the above embodiment 4, corresponding to the semi-conductive comparison permission signal of the function of turning in and out of the shirt, a preset setting port is temporarily stored as 4, and the corresponding response is based on a plurality of input and output. Of :, load value 'reload to it for the round in and out of the plural, and 2 is loaded into the register 8 again. Because according to the comparison permission signal, when the diagnostic test is performed at the same time, input the corresponding port of the port to temporarily store the piano input value and load it into the plural
Lj 旱暫存态4，所以對於複數的之輪入 出埠，能夠同時給予再載入值，而能同時執行診測。入 實施例6 本實施例6，其構造為使用根據從上述實施例1至上迷Lj is temporarily stored in a state of 4, so it is possible to give a reload value at the same time for a plurality of wheels to enter and leave the port, and to perform a diagnosis and test at the same time. Embodiment 6 This embodiment 6 is configured to be used according to the embodiment 1 to the above.
2103-5352-PF(Nl).?r，i 第11頁 200400358 五、發明說明（7) 一 實施例之5内藏有自我診測功能之半導體積體電 -個，而將此内藏有自我診測功能之半導體積 至系統，在電源投入後或重置後、或〜 、，衣 時對於本身具有之周邊功能方塊來執=對 動作之早期測出和異常測出時之動作停止上韦 保險功能。 吊之15说之輸出或根據這些組合之故障 能。因為如此地來構成’所以能夠獲得實現故障保險之功 [發明效果] 能區：：：出:m: ί構造為在欲診測周邊功 設定至痒二將门對±於周邊功能區塊之輪出之期待值， 設定至棒方向;將使輸”璋成為輸入埠之值， 塊輸出而經由立山：為’而以比較裔來比較從周邊功能區 後，來執行值，與被設定至埠暫存器之期待值 多功能化之半導：所以有不使用向價之診測器，而使 測成本之降體電路之診測自我珍測化，以謀求i 根據太《表gg 定結果，來‘行中：J其構造為按照根據比較器之診測叛 叛定之效ί執仃中斷處理’所以有能夠有效率地執行診測 根據本發明， 結果，從外部接腳 定結果，至本裝置 因為其構造為將根據比較器之診測叛定 輸出至外部’所以有能夠輸出診測叛 以外之效果。2103-5352-PF (Nl).? R, i Page 11 200400358 V. Description of the Invention (7) One of the 5th embodiment has a semiconductor integrated circuit with a self-diagnostic function, and this is hidden inside The self-diagnostic function of the semiconductor is integrated into the system. After the power is turned on or after resetting, or ~ ,, the peripheral function blocks that are included in the clothing are executed. = The early detection of the operation and the abnormal detection of the operation stop. Wei insurance function. The output of Dang 15 said or the fault performance based on these combinations. Because it is constituted in this way, the function of realizing fail-safe can be obtained. [Invention effect] Energy zone ::: out: m: ί It is structured to set the peripheral function to the itch in the diagnosis. The expected value of the rotation is set to the direction of the stick; the input “璋” will be the value of the input port, and the block output will be passed through Tateyama: the comparison value from the surrounding functional area will be compared with the comparison, and the execution value will be set to Expected value of the port register is a multi-functional semi-conductor: Therefore, there is no need to use a price-based diagnostic tester, so that the test cost of the circuit can be reduced. As a result, come on the line: J is structured to perform interrupt processing in accordance with the test result of the comparator, so that the test can be performed efficiently according to the present invention. As a result, the result is determined from the outside. This device has the effect of being able to output a diagnostic test to the outside because it is configured to output the diagnostic test to a comparator.
2103-5352-PF(Nl).ptd 第12頁 2004003582103-5352-PF (Nl) .ptd Page 12 200400358
五、發明說明（8) 根據本發明，因為其構造為在對於複數之輪入V. Description of the invention (8) According to the present invention, because it is structured to
時執行診測之情況下，除了埠方向暫存器之值外，# 〇J 比較許可信號，來給予對於複數之輪入出埠，同時診=據 許可或不許可，所以有能夠對於複數之輪^屮i 0 d之 —从、，a里。 < 輸入出蜂’同時執 輪入出埠之各埠暫存 輸入出埠，同時執行 將值再載入複數之輸 暫存器，所以有能夠 而同時執行診測之效 根據本發明’因為其構造為對應 器來被設置，而包括了在對於複數之 診測之情況下，根據比較許矸信號， 入出埠之所對應之埠暫存器之再載Λ 對於複數之輸入出埠，同時給予值， 果0 根據本發明，因為並構造為内 導俨籍辦雷攸、“ 、稱々鬥嘁有自我診測功能之半In the case of performing diagnostic tests at times, in addition to the value of the port direction register, # 〇J compares the permission signal to give access to the plural wheels in and out of the port, and simultaneous diagnosis = according to permission or non-permission, so there is ^ 屮 i 0 d 之 —from, a. < Input and output bee 'simultaneously executes the input and output of each port in turn and enters and exits at the same time, and executes the reloading of multiple input registers at the same time, so it has the effect of being able to perform the diagnostic test at the same time. It is configured as a corresponding device to be set, and includes the reloading of the port register corresponding to the input and output port according to the comparison of the Xu signal in the case of the plural test. For the plural input and output ports, at the same time, Value, according to the present invention, because it is constructed as the internal guidance office, Lei You, "
導ι積體電路被組裝至系在 J 昱堂主丨中时 μ ^ "眾仅入後或重置後、或 二 於矽測時對於本身具有之月、毐効处方娇來拙 停止或上層控制程式動= : = :異常測出時… 由這些組合之故陸 R -、系之信號之輸出或藉 保險功能之系统之二、X力月匕 斤以有能夠獲得了實現故障 L〈欢果。The integrated circuit is assembled to the time when it is connected to the master of J Yutang, and it is only after entering or resetting, or two months after the silicon test. Upper-level control program operation =: =: When abnormality is detected ... From the combination of these reasons, R-, the output of the signal or the system that borrows the insurance function, the X force moon dagger can achieve the realization failure L < Happy fruit.
200400358 圖式簡單說明 第1圖係表示根據本發明之實施例1之内藏有自我診測 功能之半導體積體電路之構造圖。 第2圖係表示根據本發明之實施例1之内藏有自我診測 功能之半導體積體電路之動作時序圖。 第3 圖 係 表 示 習 知 之 半 導 體 積 體 電路之課題之說明 圖（ 第4 圖 係 表 示 習 知 之 半 導 體 積 體 電路之課題之說明 圖（ ) 第5 圖 係 表 示 根 據 本 發 明 之 實 施 例5之内藏有自我診測 功能之半導體積體電路之構造圖。 [符號說明] 1焊墊（端子）； 2路徑選擇開關； 3 埠方向暫存器； 4 埠暫存器； 5 比較器； 6 周邊功能區塊； 7輸入信號線（璋輸入信號線）； 8 再載入暫存器； A、B 路徑。200400358 Brief Description of Drawings Fig. 1 is a diagram showing the structure of a semiconductor integrated circuit with a self-diagnostic function built in Embodiment 1 of the present invention. Fig. 2 is a timing chart showing the operation of a semiconductor integrated circuit with a self-diagnostic function built in Embodiment 1 of the present invention. Fig. 3 is an explanatory diagram showing a problem of a conventional semiconductor integrated circuit (Fig. 4 is an explanatory diagram showing a problem of a conventional semiconductor integrated circuit () Fig. 5 is a diagram showing a built-in device according to a fifth embodiment of the present invention Structure diagram of semiconductor integrated circuit with self-diagnosis function. [Symbol description] 1 pad (terminal); 2 path selection switch; 3 port direction register; 4 port register; 5 comparator; 6 peripheral functions Block; 7 input signal line (璋 input signal line); 8 reload register; A, B path.
2103-5352-PF(Nl).ptd 第14頁2103-5352-PF (Nl) .ptd Page 14
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| JP2002178872A JP2004021833A (en) | 2002-06-19 | 2002-06-19 | Semiconductor integrated circuit incorporated with self-test function and system comprising it |
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| WO2006080111A1 (en) * | 2005-01-27 | 2006-08-03 | Matsushita Electric Industrial Co., Ltd. | Semiconductor integrated circuit and system lsi |
| WO2006121882A2 (en) * | 2005-05-05 | 2006-11-16 | Cypress Semiconductor Corporation | Parallel input/output self-test circuit and method |
| JP5072251B2 (en) * | 2006-04-06 | 2012-11-14 | 三菱重工業株式会社 | Method and apparatus for producing mono-lower alkyl monoalkanolamine |
| JP4757910B2 (en) | 2006-04-27 | 2011-08-24 | 富士通セミコンダクター株式会社 | Semiconductor device and system |
| CN101907683B (en) * | 2009-06-02 | 2013-05-08 | 上海摩波彼克半导体有限公司 | Automatic circuit testing structure of I2C module in digital baseband chip and method thereof |
| CN104679196B (en) * | 2015-03-10 | 2018-07-06 | 江苏邦融微电子有限公司 | System and its implementation are resetted when processor-based self-test, exception |
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| US5867507A (en) * | 1995-12-12 | 1999-02-02 | International Business Machines Corporation | Testable programmable gate array and associated LSSD/deterministic test methodology |
| JP2861973B2 (en) * | 1996-10-11 | 1999-02-24 | 日本電気株式会社 | Test circuits for semiconductor integrated logic circuits |
| KR100222046B1 (en) * | 1996-12-20 | 1999-10-01 | 윤종용 | Semiconductor memory device with magnetic test circuit |
| US6381717B1 (en) * | 1998-04-24 | 2002-04-30 | Texas Instruments Incorporated | Snoopy test access port architecture for electronic circuits including embedded core having test access port with instruction driven wake-up |
| JP3509001B2 (en) * | 1999-12-07 | 2004-03-22 | 松下電器産業株式会社 | Semiconductor integrated circuit having self-diagnosis test circuit function and method of testing semiconductor integrated circuit |
| US6594802B1 (en) * | 2000-03-23 | 2003-07-15 | Intellitech Corporation | Method and apparatus for providing optimized access to circuits for debug, programming, and test |
| KR100374636B1 (en) * | 2000-10-18 | 2003-03-04 | 삼성전자주식회사 | Semiconductor device comprising built-in redundancy analysis circuit for testing and analyzing a plurality of memories simultaneously and analyzing method thereof |
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