JP7332204B1 - Information processing system, processing method executed by information processing system, and program - Google Patents

Abstract

Kind Code: A1 An information processing system is provided that is reconfigurable and capable of determining a failure while continuing processing. Kind Code: A1 An information processing system is a reconfigurable information processing system that corresponds one-to-one to a plurality of modules and to each of the plurality of modules, and to a one-to-one correspondence including its own defects. A BIST circuit capable of executing a BIST (Built In Self-Test) for detecting a defect in a module, and a test configuration section for storing an internal state including connection of the module, wherein the test configuration section is temporarily stopped. The BIST circuit stores an internal state including the connection of the module when the module is suspended, and corresponds to the suspended module one-to-one among the plurality of modules, and stores the faulty module in the suspended module. perform a test on [Selection drawing] Fig. 12

Description

The present disclosure relates to an information processing system, a processing method executed by the information processing system, and a program .

In recent years, reconfigurable circuits such as ASICs (Application Specific Integrated Circuits) and FPGAs (Field Programmable Gate Arrays) have become popular from the viewpoint of both high-speed processing and versatility. Patent Document 1 discloses, as a related technique, a technique related to an information processing apparatus using a reconfigurable circuit. In addition, Patent Literature 2 discloses, as a related technique, a technique for diagnosing a failure in a computer system.

Japanese Patent Application Laid-Open No. 2011-216020 JP 2006-252429 A

By the way, in a reconfigurable information processing system, it is generally difficult to determine a failure while continuing normal processing of the system. Therefore, there is a demand for a technique that can determine a failure of a reconfigurable information processing system while continuing processing.

An object of each aspect of the present disclosure is to provide an information processing system, a processing method executed by the information processing system, and a program that can solve the above problems.

In order to achieve the above object, according to one aspect of the present disclosure, an information processing system is a reconfigurable information processing system in which a plurality of modules and the plurality of modules correspond to each other on a one-to-one basis. , a BIST circuit capable of executing a BIST (Built In Self-Test) for detecting faults of modules corresponding one-to-one, including faults of the module itself, and a test configuration part for storing the internal state including the connection of the modules. , wherein the test configuration unit stores an internal state of the suspended module including the connection of the module at the time of the suspension, and corresponds to the suspended module among the plurality of modules on a one-to-one basis. The BIST circuit performs a test for the fault on the suspended module.

In order to achieve the above object, according to another aspect of the present disclosure, a processing method executed by an information processing system provides a one-to-one correspondence between a plurality of modules and each of the plurality of modules, and A BIST circuit capable of executing a BIST (Built In Self-Test) for detecting defects in modules corresponding one-to-one, including the A processing method executed by a configurable information processing system, wherein the test configuration unit stores an internal state including a connection of the module at the time of the suspension for the suspended module, and The BIST circuit, which corresponds one-to-one with the suspended module, performs a test for the fault on the suspended module.

In order to achieve the above object, according to another aspect of the present disclosure, a plurality of modules and modules corresponding to each of the plurality of modules on a one-to-one basis, including their own defects, are arranged in a one-to-one correspondence. A computer having a reconfigurable information processing system, comprising a BIST circuit capable of executing a BIST (Built In Self-Test) for detecting defects, and a test configuration section for storing internal states including connections of the modules. A program recorded on a readable recording medium causes the information processing system to store an internal state of the suspended module including connection of the module at the time of the suspension; and performing a test for the failure .

According to each aspect of the present disclosure, it is possible to reconfigure and determine a failure while continuing processing.

It is a figure showing an example of composition of an information processing system by one embodiment of this indication. 2 is a diagram illustrating an example of a configuration of a processor according to an embodiment of the present disclosure; FIG. FIG. 3 is a diagram illustrating an example of a configuration of a logic unit according to an embodiment of the present disclosure; FIG. 1 is a diagram illustrating an example configuration of a memory cell array according to an embodiment of the present disclosure; FIG. 1 is a diagram illustrating an example configuration of a test device according to an embodiment of the present disclosure; FIG. FIG. 4 is a diagram illustrating an example of test configuration information recorded by a test configuration unit according to an embodiment of the present disclosure; FIG. FIG. 2 is a diagram illustrating an example of a first processing flow of an information processing system according to an embodiment of the present disclosure; FIG. FIG. 5 is a diagram illustrating an example of a second processing flow of an information processing system according to an embodiment of the present disclosure; FIG. It is a figure showing an example of composition of an information processing system by modification 1 of one embodiment of this indication. It is a figure which shows an example of a structure of the information processing system by the modification 2 of one embodiment of this disclosure. FIG. 11 is a diagram illustrating an example of a configuration of an information processing system according to Modification 3 of an embodiment of the present disclosure; 1 is a diagram showing the minimum configuration of an information processing system according to an embodiment of the present disclosure; FIG. 1 is a diagram illustrating an example of a processing flow of an information processing system with a minimum configuration according to an embodiment of the present disclosure; FIG. 1 is a schematic block diagram showing a configuration of a computer according to at least one embodiment; FIG.

Hereinafter, embodiments will be described in detail with reference to the drawings.
<Embodiment>
FIG. 1 is a diagram illustrating an example configuration of an information processing system 100 according to an embodiment of the present disclosure. The information processing system 100 includes processors 1a, 1b, a test device 2, a main memory 3, a storage device 4, a configuration control device 5, an input/output device 6, a diagnostic bus 7, and a bus 8, as shown in FIG. The processors 1a and 1b are collectively referred to as a processor 1. FIG. Each of the processors 1 is connected via a bus 8 to each of the testing device 2 , the main memory 3 , the storage device 4 , the configuration control device 5 and the input/output device 6 . Each of the processors 1 is also connected to the testing device 2 via a diagnostic bus 7 . Diagnostic bus 7 is a communication path interconnecting processor 1 and test equipment 2 for testing.

The processor 1 is a circuit device that configures a functional circuit by programming user logic. Examples of the processor 1 include ASIC (Application Specific Integrated Circuit) and FPGA (Field Programmable Gate Array). FIG. 2 is a diagram illustrating an example configuration of the processor 1 according to an embodiment of the present disclosure. The processor 1 includes a logic unit 11 and a configuration memory 14, as shown in FIG.

The logic unit 11 receives inputs such as data and commands to the processor 1 . The logic unit 11 performs predetermined processing on the received data and instructions. The logic unit 11 outputs the processing result to the main memory 3 , the storage device 4 and the input/output device 6 . The logic section 11 includes a wiring logic section 12 (an example of a module) and a memory cell array 13 (an example of a module), and constitutes a combinational logic section 111 and a sequential logic section 112 as described later.

The wiring logic unit 12 is a circuit configured by physical wiring. The memory cell array 13 is a portion that functions as a circuit by being defined by a program. The memory cell array 13 functions as a circuit by developing definition information (that is, user logic) stored in the configuration memory 14 in the memory cell array 13 .

The wiring logic unit 12 also includes a BIST circuit 121 for detecting failures. The memory cell array 13 has a BIST circuit 131 for detecting failures. Each of the BIST circuits 121 and 131 is a circuit configured by physical wiring. The BIST circuit 121 executes BIST on the wiring logic section 12 upon receiving a test instruction from the test apparatus 2 . The BIST circuit 121 then outputs the test result to the test device 2 via the diagnostic bus 7 . Also, upon receiving a test instruction from the test apparatus 2 , the BIST circuit 131 performs BIST on the memory cell array 13 . The BIST circuit 131 then outputs the test results to the test device 2 via the diagnostic bus 7 .

FIG. 3 is a diagram showing an example configuration of the logic unit 11 according to an embodiment of the present disclosure. The logic section 11 includes a combinatorial logic section 111 and a sequential logic section 112 . The combinational logic unit 111 is a combinational circuit whose output is not affected by past input information. The sequential logic unit 112 is a sequential circuit, and is a circuit such as a memory that determines an output value based on a value input in the past. Combinatorial logic portion 111 and sequential logic portion 112 are constituted by wiring logic portion 12 and memory cells arranged on memory cell array 13 .

FIG. 4 is a diagram showing an example configuration of the memory cell array 13 according to an embodiment of the present disclosure. As shown in FIG. 4, the memory cell array 13 includes a plurality of memory cells 13a and a BIST circuit 131a for executing BIST corresponding to each memory cell 13a. The BIST circuit 131a can copy the internal state of the memory cell array 13 to the test device 2 before testing, and restore the internal state received from the test device 2 to the memory cell array 13 after the test. In the memory cell array 13, each memory cell 13a can be reset and configured by a test instruction.

The processor 1 also has registers, an arithmetic processing unit, an interface, a sequencer, and breakpoint functions. A register temporarily stores data used in an operation. The arithmetic processing unit executes arithmetic operations. The interface transmits and receives signals and data to and from the bus 8 . The sequencer controls the circuits described above (ie registers, processors, interfaces). A breakpoint function suspends operation for testing and debugging. These circuit logics (that is, registers, arithmetic processing units, interfaces, sequencers, and breakpoint functions) are configured by wiring logic units 12 or memory cell arrays 13 . In particular, the breakpoint function is configured by the wiring logic section 12 .

The test device 2 transmits test instructions to the processor 1 for testing. The test device 2 also receives test results from the processor 1 . FIG. 5 is a diagram illustrating an example configuration of the test apparatus 2 according to an embodiment of the present disclosure. The test apparatus 2 includes a test configuration section 21, a test instruction section 22, an internal state management section 23, and a test result determination section 24, as shown in FIG.

When the information processing system 100 is initialized, the test configuration unit 21 stores configuration information of the information processing system including the processor 1 input from the input/output device 6 or recorded in the main memory 3, configuration information of the logic unit 11, module It receives the test pattern (wiring logic unit 12 and memory cell array 13) and the expected value of the test, and records it in the main memory 3 via the bus 8 as test configuration information. FIG. 6 is a diagram showing an example of test configuration information recorded by the test configuration unit 21 according to an embodiment of the present disclosure. Here, the module is obtained by dividing and classifying the wiring logic section 12 and the memory cell array 13 to which the user logic is allocated into units such as arbitrary circuits, functional units, redundant units, and the like. Note that the memory cell array 13 may belong to a plurality of modules. A test pattern is a pattern to be input to the memory cell array 13 in order to execute BIST. Also, the expected output for that input is the expected value. The memory cell C and the wiring logic L in FIG. 6 are the configuration information of the logic section 11 .

The test instruction unit 22 receives test instructions from the input/output device 6 . Upon receiving the test instruction, the test instruction section 22 instructs the processor 1 to perform a test based on the test configuration of the test configuration section 21 .

The internal state management unit 23 receives the internal state of the target memory cell array 13 before testing. After the test, the internal state management unit 23 transmits the internal state to the target memory cell array 13 . The internal state of the memory cell array 13 may be stored in a storage area such as the main memory 3 or storage device 4 .

The test result determination unit 24 receives test results from the processor 1 . Then, the test result determination unit 24 determines a defect based on the test result. The test result determination unit 24 outputs the determination result to the input/output device 6 and the configuration control device 5 .

The main memory 3 is a storage area having, for example, a DRAM (Dynamic Random Access Memory), which is the main storage device 4 . The main memory 3 stores an operating system (not shown), user programs, data, and the like. Devices connected to bus 8 can access the memory space of main memory 3 . Devices connected to the bus 8 can also share data via the main memory 3 .

The storage device 4 is a storage area having, for example, an HDD (Hard Disk Drive) or an SSD (Solid State Drive), which is an auxiliary storage device 4 . Devices connected to bus 8 can access storage device 4 . Devices connected to the bus 8 can also share data via the storage device 4 .

The configuration control device 5 manages the configuration of the information processing system 100 . Configuration controller 5 receives test results from test device 2 . The configuration control device 5 isolates the failed processor 1 from the information processing system 100 or adds a new processor 1 to the information processing system 100 based on the test results. The configuration control device 5 can also instruct the processor 1 to reset or reconfigure.

The input/output device 6 is, for example, an external communication device such as a keyboard or display. The input/output device 6 receives test instructions from the user and displays test results according to control contents (for example, test instructions) by other devices connected to the bus 8 .

Next, processing performed by the information processing system 100 according to an embodiment of the present disclosure will be described. FIG. 7 is a diagram illustrating an example of a first processing flow of the information processing system 100 according to an embodiment of the present disclosure. FIG. 8 is a diagram illustrating an example of a second processing flow of the information processing system 100 according to an embodiment of the present disclosure. Here, processing performed by the information processing system 100 will be described with reference to FIGS. 7 and 8. FIG.

Test equipment 2 tests processor 1 under direction from a user, operating system, or configuration controller 5 . The test is performed on a module-by-module basis at specified intervals. The configuration information of the processor 1 to be tested is transmitted from the user or the operating system to the test configuration section 21 when the target system is initialized.

At the time of testing, the test apparatus 2 prepares (prepares) the test pattern by acquiring the test pattern of the test target module from the test configuration unit 21 (step S101). When the preparation is completed, the test instructing section 22 transmits a break signal for temporarily stopping the operation of the processor 1 to the processor 1 (step S102). Processor 1 stops its operation in response to the break signal.

After the processor 1 is stopped, the internal state manager 23 duplicates the internal state of each memory cell array 13 constituting the test target module to the main memory 3 or storage device 4 (step S103). The internal state management unit 23 transmits the test pattern and the test instruction to the test target module (step S104). Then, the internal state management unit 23 executes BIST (step S105).

The internal state management unit 23 determines whether the test result is normal (step S106). When the internal state management unit 23 determines that the test result is normal (YES in step S106), the internal state of each memory cell array 13 is restored from the duplicated data (step S107). The internal state management unit 23 transmits a break release signal for restarting the operation of the processor 1 to the processor 1 (step S108). Processor 1 resumes operation in response to the break release signal. Further, when the internal state management unit 23 determines that the test result is not normal (NO in step S106), the internal state management unit 23 outputs defect information indicating that a defect has occurred in the processor 1. The system is notified (step S109).

Here, detailed processing of the test instruction unit 22 and the test result determination unit 24 will be described. The test instruction unit 22 instructs the module to be tested and the memory cell array 13 constituting the module to be tested. Then, the test instruction section 22 transmits a test pattern for BIST. The test instruction unit 22 refers to the target module, the memory cell array 13 forming the same, and the test pattern in the test configuration unit 21 . The test instruction unit 22 transmits a test instruction and a test pattern to the test target module. Also, the test instruction section 22 transmits the expected value of the test pattern to the test result determination section 24 . When the test is completed, the test target module transmits the test result to the test result determination unit 24 . The test result determination unit 24 compares the received test results with expected values. The test result determination unit 24 determines whether or not the test result is normal based on the collation result.

In step S106 for judging the test result after executing the BIST, the test instruction unit 22 executes the test multiple times to confirm the degree of failure of the target module. The test result determination unit 24 determines whether or not the test result of the test target module is normal (steps S106 and S201).

When test result determination unit 24 determines that the test result is normal (YES in steps S106 and S201), the process ends. When the test result determination unit 24 determines that the test result is not normal (NO in steps S106 and S201), it instructs resetting and reconfiguration of the target module (step S202). Then, the test result determination unit 24 retests the target module (step S203). Then, the test result determination unit 24 determines whether or not the retest result is normal (step S204).

When the test result determination unit 24 determines that the retest result is normal (YES in step S204), the test result determination unit 24 determines that the defect is an intermittent failure (step S205). Examples of intermittent failures include failures that cause semiconductors to temporarily malfunction due to the effects of cosmic rays (neutron rays), etc., and are generally called soft-errors. failures that can be repaired by Then, the test result determination unit 24 terminates the processing.

Further, when the test result determination unit 24 determines that the retest result is not normal (NO in step S204), it determines whether or not the test has been performed a certain number of times or more (step S206). When the test result determining unit 24 determines that the test has been performed more than the given number of times (YES in step S206), it determines that the defect is a fixed failure (step S207). Examples of fixed failures include failures that permanently cause malfunctions due to physical circuit damage. Then, the test result determination unit 24 terminates the processing.
If the test result determination unit 24 determines that the test has not been performed more than the predetermined number of times (NO in step S206), the process returns to step S202.

Configuration controller 5 receives test results from test device 2 . If the malfunction of the processor 1 is a fixed failure, the configuration controller 5 disconnects the processor 1 from the information processing system 100 . The configuration controller 5 then notifies the operating system of the disconnection. Also, if the information processing system 100 has a spare processor 1 , the configuration control device 5 incorporates it as an alternative processor 1 .

The BIST processing described above is performed for all modules by suspending each module in turn.

(advantage)
The information processing system 100 according to an embodiment of the present disclosure has been described above. The information processing system 100 is a reconfigurable information processing system. The information processing system 100 has a one-to-one correspondence between a plurality of modules (wiring logic section 12, memory cell array 13) and the plurality of modules, and detects failures of the modules that correspond one-to-one, including its own failure. It comprises a BIST circuit (BIST circuits 121, 131) capable of executing BIST (Built In Self-Test) to be detected, and a test configuration section 21 for storing the internal state including connection of the modules. The test configuration unit 21 stores the internal state including the connection of the module at the time of the suspension for the suspended module, and the BIST corresponding to the suspended module among the plurality of modules on a one-to-one basis. A circuit performs a test for the fault on the suspended module. The information processing system 100 can be reconfigured and can determine a defect while continuing processing.

A plurality of modules (wiring logic section 12, memory cell array 13) correspond to each of the plurality of modules on a one-to-one basis, and a BIST ( BIST circuits (BIST circuits 121 and 131) capable of executing a Built In Self-Test), a test configuration section 21 for storing internal states including connection of the modules, and the above-mentioned The test configuration unit 21 that stores the internal state including the connection of the modules, and the BIST circuit that performs the test regarding the defect in the suspended module, can perform reconfigurable information processing by executing a configuration program. It may be implemented in system 100 .

<Modification 1 of Embodiment>
FIG. 9 is a diagram showing an example configuration of an information processing system 100 according to Modification 1 of an embodiment of the present disclosure. In Modified Example 1 of an embodiment of the present disclosure, the information processing system 100 may arrange the configuration memory 14 in the processor 1 as shown in FIG. 9 . Also, for example, the configuration memory may be arranged in the test device 2, the main memory 3, and the storage device 4 as well. Processor 1 can access configuration memories 14 , 25 , 31 , 41 via bus 8 or diagnostic bus 7 during its initialization (configuration) phase. Even if a problem occurs in the configuration memories 14, 25, 31, 41, the processing by the processor 1 and the test for the problem of the processor 1 can be continued.

<Modification 2 of Embodiment>
FIG. 10 is a diagram illustrating an example of a configuration of an information processing system 100 according to Modification 2 of an embodiment of the present disclosure. In Modified Example 2 of an embodiment of the present disclosure, the information processing system 100 may have a plurality of test apparatuses 2 arranged for redundant testing, as illustrated in FIG. 10 . The test configuration unit 21, test instruction unit 22, internal state management unit 23, and test result determination unit 24 of each test device 2 determine a test target module via the diagnostic bus 7, and execute the test on the same module. Then, the test results obtained by each test device 2 are shared, and the test result determination unit 24 determines that a problem has occurred in the test device 2 when the test results do not match.

<Modification 3 of Embodiment>
FIG. 11 is a diagram showing an example of a configuration of an information processing system 100 according to Modification 3 of an embodiment of the present disclosure. In Modified Example 3 of an embodiment of the present disclosure, an information processing system 100 packages a group of processors 1 as a many-core package 90 as shown in FIG. It may be something to do. This many-core package 90 improves the degree of integration and reduces manufacturing costs.

FIG. 12 is a diagram showing the minimum configuration of the information processing system 100 according to the embodiment of the present disclosure. The information processing system 100 is a reconfigurable information processing system. The information processing system 100 corresponds one-to-one to the plurality of modules 12 and 13 and the plurality of modules 12 and 13, respectively, and detects faults of the modules 12 and 13 that correspond one-to-one, including its own fault. and BIST circuits 121 and 131 capable of executing BIST (Built In Self-Test), and a test configuration unit 21 for storing internal states including connection of the modules 12 and 13 . The test configuration unit 21 stores the internal state of the suspended module including the connection of the module at the time of the suspension. The BIST circuit corresponding to the suspended module among the plurality of modules on a one-to-one basis tests the suspended module for the defect. This information processing system 100 can be reconfigured and can determine a defect while continuing processing.

FIG. 13 is a diagram illustrating an example of a processing flow of the minimum configuration information processing system 100 according to the embodiment of the present disclosure. Next, processing of the minimum configuration information processing system 100 according to the embodiment of the present disclosure will be described with reference to FIG. 13 .

BIST (Built In Self) for detecting defects in the modules 12 and 13 corresponding to the plurality of modules 12 and 13 on a one-to-one basis, including their own defects. -Test), and a test configuration unit 21 that stores the internal state including the connection of the modules 12 and 13. In the reconfigurable information processing system 100, the test configuration unit 21 is For the suspended module, the internal state including the connection of the module at the time of the suspension is stored (step S101). The BIST circuit corresponding one-to-one to the suspended module among the plurality of modules 12 and 13 tests the suspended module for the defect (step S102).

The information processing system 100 with the minimum configuration according to the embodiment of the present disclosure has been described above. This information processing system 100 can be reconfigured and can determine a defect while continuing processing.

It should be noted that the order of the processes in the embodiment of the present disclosure may be changed as long as appropriate processes are performed.

Although the embodiment of the present disclosure has been described, the information processing system 100 and other control devices described above may have a computer system inside. The process of the above-described processing is stored in a computer-readable recording medium in the form of a program, and the above-described processing is performed by reading and executing this program by a computer. Specific examples of computers are shown below.

FIG. 14 is a schematic block diagram showing the configuration of a computer according to at least one embodiment; The computer 50 includes a CPU 60, a main memory 3, a storage 80, and an interface 9, as shown in FIG.

For example, the information processing system 100 and other control devices described above are implemented in the computer 50 . The operation of each processing unit described above is stored in the storage 80 in the form of a program. The CPU 60 reads out the program from the storage 80, develops it in the main memory 3, and executes the above process according to the program. In addition, the CPU 60 secures storage areas corresponding to the storage units described above in the main memory 3 according to the program.

Examples of the storage 80 include HDD (Hard Disk Drive), SSD (Solid State Drive), magnetic disk, magneto-optical disk, CD-ROM (Compact Disc Read Only Memory), DVD-ROM (Digital Versatile Disc Read Only Memory). , semiconductor memory, and the like. The storage 80 may be an internal medium directly connected to the bus of the computer 50, or an external medium connected to the computer 50 via the interface 9 or communication line. Further, when this program is delivered to the computer 50 via a communication line, the computer 50 receiving the delivery may load the program into the main memory 3 and execute the above process. In at least one embodiment, storage 80 is a non-transitory, tangible storage medium.

Further, the program may implement part of the functions described above. Furthermore, the program may be a file capable of realizing the above functions in combination with a program already recorded in the computer system, that is, a so-called difference file (difference program).

While several embodiments of the disclosure have been described, these embodiments are examples and do not limit the scope of the disclosure. Various additions, omissions, replacements, and modifications may be made to these embodiments without departing from the gist of the disclosure.

1, 1a, 1b, 1c Processor 2 Test device 3 Main memory 4 Storage device 5 Configuration control device 6 I/O device 7 Diagnosis bus 8 Bus 9 Interface 11 Logic section 12 Wiring logic section 13 Memory cell arrays 14, 25, 31, 41 Configuration memory 21 Test configuration section 22 ..Test instruction unit 23..Internal state management unit 24..Test result determination unit 50..Computer 60..CPU
80... Storage 100... Information processing system 111... Combination logic unit 112... Sequential logic units 121, 131... BIST circuit

Claims (7)

A reconfigurable information processing system,
multiple modules and
a BIST circuit capable of executing a BIST (Built In Self-Test) that corresponds to each of the plurality of modules on a one-to-one basis and detects defects of the corresponding modules on a one-to-one basis including defects of its own;
a test configuration unit that stores internal states including connection of the modules;
with
The test configuration unit includes:
storing the internal state of the suspended module including the connection of the module at the time of the suspension;
The BIST circuit corresponding to the suspended module among the plurality of modules on a one-to-one basis,
performing a test for the fault on the suspended module;
Information processing system. The BIST circuit, in which all of the plurality of modules are suspended and which correspond one-to-one to each of the plurality of modules,
storing an internal state including the connection of the module when the suspended module is suspended, and executing a test regarding the defect for the suspended module;
The information processing system according to claim 1. a test result determination unit that determines a defect in the suspended module based on the result of the BIST by the BIST circuit and an expected value that is an expected output for the input when executing the BIST;
3. The information processing system according to claim 1, comprising: The test result determination unit,
When the result of the BIST indicates that the defect has occurred, if the result of the BIST re-executed by the BIST circuit determines that the result is normal, the defect is determined to be an intermittent failure;
The information processing system according to claim 3. The test result determination unit,
When the result of the BIST indicates that the defect has occurred, the result of the BIST re-executed by the BIST circuit determines that the defect has occurred, and the BIST is executed more than a predetermined number of times. 5. The information processing system according to claim 3, wherein if it is determined that the defect is a fixed failure. A BIST circuit capable of executing a BIST (Built In Self-Test) for detecting a defect of a module corresponding to a plurality of modules on a one-to-one basis, including its own defect. and a test configuration unit that stores an internal state including connection of the modules, and is executed by a reconfigurable information processing system, comprising:
The test configuration unit includes:
storing the internal state of the suspended module including the connection of the module at the time of the suspension;
The BIST circuit corresponding to the suspended module among the plurality of modules on a one-to-one basis,
performing a test for the fault on the suspended module;
A processing method performed by an information processing system. A BIST circuit capable of executing a BIST (Built In Self-Test) for detecting a defect of a module corresponding to a plurality of modules on a one-to-one basis, including its own defect. and a test configuration unit that stores an internal state including the connection of the modules, a reconfigurable information processing system comprising:
storing an internal state of the suspended module, including the connection of the module at the time of the suspension;
performing a test for the fault on the suspended module;
A program recorded on a computer-readable recording medium of the information processing system, which causes the execution of

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