200408011 五、發明說明（1) 發明領域： 本發明係有關於一種雙閘極薄膜電晶體（th i n f i 1 m transistor，TFT)之製造方法及其結構，特別是有關於 一種自我對準（self-alignment)之雙閘極薄膜電晶體之 製造方法及其結構。 發明背景： 低溫多晶石夕薄膜電晶體（low temperature p〇ly- Si thin f i lm transistor)可用以做為液晶顯示器中之切換 元件，低溫多晶矽薄膜電晶體也可用以做為液晶顯示器週 邊之驅動電路，將切換元件與驅動電路同時製作在玻璃基 板上可降低生產成本，故，低溫多晶石夕薄膜電晶體於現今 液晶顯示器之發展上甚為重要。然而，傳統低溫多晶石夕薄 膜電晶體之電流驅動能力較差，扭結效應（k i nk effect)嚴重，已經無法滿足現今要求，因此，具有較古 導通電流（on-current)且對短通道效應（short channel effect)敏感度低的雙閘極薄膜電晶體遂應薇而 生。不過，雙閘極薄膜電晶體的製作過程中，一直^在有 上閘極（top gate)與下閘極（bottom gate)對準偏差 的問題’除了產生較大的寄生電容（parasitic capaci tance)，薄膜電晶體尺寸亦無法縮小，薄膜電曰 體效能低劣預期可見，習知技術之缺失由此可見—般。aa 200408011 五、發明說明（2) 發明目的及概述： 鑒於習知技術之缺失，本發明的目的就是在提供一種自 我對準之雙閘極薄膜電晶體之製造方法及其結構，避免產 生較大的寄生電容。 本發明的另一目的就是在提供一種自我對準之雙閘極薄 膜電晶體之製造方法及其結構，可以縮小薄膜電晶體之尺 寸。 本發明的又一目的就是在提供一種自我對準之雙閘極薄 膜電晶體之製造方法及其結構，用以降低薄膜電晶體之 源/汲極的接觸電阻值與改善薄膜電晶體之扭結效應。 本發明的再一目的就是在提供一種自我對準之雙閘極薄 膜電晶體之製造方法及其結構，用以增大薄膜電晶體之輸 出阻抗與增益。 根據上述目的，本發明一方面提供一種自我對準之雙閘 極薄膜電晶體之製造方法，此製造方法先形成一下閘極於 一基礎層上方，再依序沉積一第一閘極介電層、一絕緣層 與一半導體層於下閘極與基礎層上方，然後化學機械研磨 半導體層而停止於絕緣層，移除未被半導體層覆蓋住之絕 緣層而暴露出第一閘極介電層，並依序沉積一導通層與一 第二閘極介電層於半導體層與第一閘極介電層上方，最後 形成一上閘極於第二閘極介電層上方。 本發明另一方面提供一種雙閘極薄膜電晶體之結構，此200408011 V. Description of the invention (1) Field of the invention: The present invention relates to a method and structure for manufacturing a double gate thin film transistor (thinfi 1 m transistor, TFT), and more particularly to a self-aligned (TFT) Aligned) manufacturing method and structure of double-gate thin film transistor. Background of the Invention: Low temperature poly-Si thin film transistors can be used as switching elements in liquid crystal displays, and low temperature polycrystalline silicon thin film transistors can also be used as drivers for liquid crystal displays. Circuits, and the simultaneous manufacture of switching elements and driving circuits on a glass substrate can reduce production costs. Therefore, low temperature polycrystalline silicon thin film transistors are very important in the development of today's liquid crystal displays. However, the traditional low-temperature polycrystalline silicon thin film transistor has poor current driving capability, serious kink effect, and has been unable to meet the current requirements. Therefore, it has an ancient on-current and has a short channel effect ( Short channel effect) dual-gate thin film transistor with low sensitivity was born. However, in the manufacturing process of the double-gate thin-film transistor, there has been a problem of misalignment between the top gate and the bottom gate, except that a large parasitic capacitance is generated. The size of the thin-film transistor cannot be reduced, and the poor performance of the thin-film transistor can be expected, and the lack of conventional technology can be seen. aa 200408011 V. Description of the invention (2) Purpose and summary of the invention: In view of the lack of conventional technology, the purpose of the present invention is to provide a method and structure for manufacturing a self-aligned double-gate thin-film transistor to avoid large Parasitic capacitance. Another object of the present invention is to provide a method and structure for manufacturing a self-aligned double-gate thin film transistor, which can reduce the size of the thin film transistor. Another object of the present invention is to provide a method and structure for manufacturing a self-aligned double-gate thin film transistor, which are used to reduce the contact resistance value of the source / drain of the thin film transistor and improve the kink effect of the thin film transistor. . Another object of the present invention is to provide a method and a structure for manufacturing a self-aligned double-gate thin film transistor, so as to increase the output impedance and gain of the thin film transistor. According to the above object, one aspect of the present invention is to provide a method for manufacturing a self-aligned double-gate thin-film transistor. This manufacturing method first forms a gate above a base layer, and then sequentially deposits a first gate dielectric layer. An insulating layer and a semiconductor layer over the lower gate and the base layer, and then chemically and mechanically grind the semiconductor layer to stop at the insulating layer, remove the insulating layer not covered by the semiconductor layer, and expose the first gate dielectric layer And sequentially depositing a conductive layer and a second gate dielectric layer over the semiconductor layer and the first gate dielectric layer, and finally forming an upper gate over the second gate dielectric layer. Another aspect of the present invention provides a structure of a double-gate thin film transistor.
第8頁 200408011 五、發明說明（3) 於下閘 上方之 一位於 電層上 上述 層與第 可為氮 本發 半導體 薄膜電 體之扭 極上方 導通層 導通層 方而與 下閘極 二閘極 化矽， 明除了 層之材 晶體之 結效應 基礎層、一位於基礎層上方之下閘極、一位 之2一閘極介電層、一位於第一問極介電層 位於第一閘極介電層兩侧之半導體層、 上方之第二閘極介電層、一位於第二閘極介 下閘極對準之上閘極。 與上閘極之材質可為多晶矽，第一閘極介電 "電層之材質可為二氧化矽，絕緣層之材質 且半導體層之材質可為多晶矽鍺。 具有自我對準上閘極與下閘極之功效，由於 質可為多晶矽鍺，因此，本發明並得以降低 源/汲極的接觸電阻值，並可改善薄膜電晶 問題。 發明詳細說明 凊參照第1A〜1 G圖’為緣示本發明製作自我對準之雙閘 極薄膜電晶體之剖面結構流程示意圖。首先，如第1 A圖所 示，先形成一下閘極11於一基礎層1 〇上方。其中，可利用 習知方式形成此下閘極11，亦即先以低壓化學氣相沉積法 (low pressure chemical vapor deposition， LPCVD) 於400〜45 0°C沉積一導體層於基礎層1 0上方，然後再以微 |影製程與餘刻技術定義導體層圖案，最後重掺雜磷於此導 體層，此導體層即形成下閘極11。較佳者，導體層之材質 為多晶矽，所沉積之導體層之厚度為2000〜3000A。Page 8200408011 V. Description of the invention (3) One of the upper layers above the lower gate is located on the electrical layer. The above-mentioned layer and the conductive layer above the torsion pole which may be a nitrogen thin film semiconductor body are connected to the lower gate by the second gate. Polarized silicon, except for the junction effect of the crystal base layer, a gate above and below the base layer, a gate dielectric layer of 2 and a gate dielectric layer on the first gate A semiconductor layer on both sides of the gate dielectric layer, a second gate dielectric layer above, and a gate positioned below the second gate and aligned above the gate. The material of the upper gate can be polycrystalline silicon, the material of the first gate dielectric " electrical layer can be silicon dioxide, the material of the insulating layer, and the material of the semiconductor layer can be polycrystalline silicon germanium. It has the effect of self-aligning the upper gate and the lower gate. Since the quality can be polycrystalline silicon germanium, the invention can reduce the contact resistance value of the source / drain and improve the problem of the thin film transistor. Detailed description of the invention 凊 Refer to Figures 1A to 1G 'for a schematic flow chart showing the cross-sectional structure of a self-aligned double-gate thin film transistor manufactured by the present invention. First, as shown in FIG. 1A, a gate electrode 11 is formed above a base layer 10 first. The lower gate 11 can be formed in a conventional manner, that is, a low pressure chemical vapor deposition (LPCVD) method is used to deposit a conductor layer above the base layer 10 at 400 ~ 45 0 ° C. Then, the conductor layer pattern is defined by the micro-lithography process and the after-cut technique. Finally, the conductor layer is heavily doped with phosphorus, and the conductor layer forms the lower gate electrode 11. Preferably, the material of the conductive layer is polycrystalline silicon, and the thickness of the deposited conductive layer is 2000 ~ 3000A.
第9頁 200408011 五、發明說明（4) 第1 B圖中，再依序沉積一第一閘極介電層1 2、一絕緣層 1 3與一半導體層1 4於下閘極1 1與基礎層丨〇上方。其中，第 一閘極介電層1 2之材質可為二氧化矽，可以低溫氧化沉積 法(low-temperature-oxide deposition, LT0)於 400〜 4 5 0°C沉積第一閘極介電層，較佳者，第一閘極介電層之 厚度為1000A。其中，絕緣層1 3之材質可為氮化石夕，可以 電漿加強化學氣相>儿積法（plasma-enhanced chemical vapor deposition, PECVD)沉積絕緣層，較佳者，絕緣 層之厚度為1500〜2500A。其中，半導體層η之材質可為多 晶矽鍺，可以高真空化學氣相沉積法（uitra —high vacuum chemical vapor deposition，UHV CVD)沉積半 導體層，較佳者，半導體層之厚度為2000〜3000A。 第1C圖中，然後以化學機械研磨（chemica卜 mechanical polishing，CMP)方式研磨此半導體層14， 而停止於絕緣層1 3，以分別於第一閘極介電層1 2兩侧形成 薄膜電晶體之源/汲極。 第1D圖中，移除未被半導體14層覆蓋住之絕緣層13，而 暴露出第一閘極介電層12。其中，若絕緣層13之材質為氮 化矽，則可以磷酸進行溼餘刻移除未被半導體1 4層覆蓋住 之絕緣層1 3。 第1 E圖中，形成一導通層1 5於半導體層丨4與第一閘極介 電層1 2上方。其中，可以先以低壓化學氣相沉積法沉積一 多晶石夕層於半導體層1 4與第一閘極介電層1 2上方，然後再 以雷射退火（laser anneal ing)或金屬引發側向結晶法 200408011 五、發明說明（5) (metal induced uni lateral crystallization, MILC) 方式來低溫結晶化多晶矽層，此多晶矽層即形成導通層 15。較佳者，多晶矽層之厚度為250〜350A。 第1 F圖中，沉積一第二閘極介電層1 6於導通層1 5上方。 其中，第二閘極介電層1 6之材質可為二氧化矽，可以低溫 氧化沉積法於4 0 0〜4 5 0°C沉積第二閘極介電層，較佳者， 第二閘極介電層之厚度為1000A。 最後，如第1 G圖所示，形成一上閘極1 7於第二閘極介電 層1 6上方。其中，可以先沉積一多晶矽層於第二閘極介電 層1 6上方，然後再化學機械研磨多晶矽層，而停止於第二 閘極介電層1 6，此多晶矽層即形成上閘極1 7。至此，則完 成自我對準之雙閘極薄膜電晶體之製作。 傳統即是分別以兩道光罩形成下閘極與上閘極，因此’ 曝光偏差（mis-alignment)即會造成上閘極與下閘極產 生對準偏差的問題；相對而言，本發明僅以一道光罩形成 下閘極11 (第1 A圖），而上閘極係利用沉積多晶矽層與研 磨方式形成上閘極1 7 (第1 G圖），因此，不會使上閘極1 7 與下閘極11產生對準偏差的問題，本發明可以避免產生較 大的寄生電容。 另外，本發明半導體層14之材質可選用多晶矽鍺（第1G 圖）做為薄膜電晶體之源/汲極，相關技術指出多晶矽鍺 較習知技術使用矽於源極端具有較低之能隙寬，可降低 源/没極的接觸電阻值、改善扭結效應問題，並增大輸出 阻抗（output impedance)與增益（gain)。Page 9 200408011 V. Description of the invention (4) In Figure 1B, a first gate dielectric layer 1 2, an insulating layer 1 3 and a semiconductor layer 1 4 are sequentially deposited on the lower gate 1 1 and Above the base layer. Wherein, the material of the first gate dielectric layer 12 may be silicon dioxide, and the first gate dielectric layer may be deposited at a temperature of 400 to 4 50 ° C by a low-temperature-oxide deposition (LT0) method. Preferably, the thickness of the first gate dielectric layer is 1000A. Among them, the material of the insulating layer 13 may be nitride stone, and plasma-enhanced chemical vapor deposition (PECVD) can be used to deposit the insulating layer. Preferably, the thickness of the insulating layer is 1500. ~ 2500A. The material of the semiconductor layer η may be polycrystalline silicon germanium, and a semiconductor layer may be deposited by a high vacuum chemical vapor deposition (Utra-high vacuum chemical vapor deposition (UHV CVD)) method. Preferably, the thickness of the semiconductor layer is 2000 to 3000A. In FIG. 1C, the semiconductor layer 14 is then polished by chemical mechanical polishing (CMP), and stopped at the insulating layer 13 to form thin-film electrodes on both sides of the first gate dielectric layer 12 respectively. Source / Drain of the Crystal. In FIG. 1D, the insulating layer 13 not covered by the semiconductor 14 layer is removed, and the first gate dielectric layer 12 is exposed. Among them, if the material of the insulating layer 13 is silicon nitride, the insulating layer 13 which is not covered by the semiconductor 14 layer can be removed by wet etching with phosphoric acid. In FIG. 1E, a conductive layer 15 is formed over the semiconductor layer 4 and the first gate dielectric layer 12. Among them, a polycrystalline silicon layer can be deposited on the semiconductor layer 14 and the first gate dielectric layer 12 by a low-pressure chemical vapor deposition method, and then laser annealing or metal-initiated side is performed. Directional crystallization method 20040811 V. Description of the invention (5) (metal induced uni lateral crystallization (MILC)) method to crystallize a polycrystalline silicon layer at a low temperature, and the polycrystalline silicon layer forms a conductive layer 15. Preferably, the thickness of the polycrystalline silicon layer is 250 ~ 350A. In Figure 1F, a second gate dielectric layer 16 is deposited over the conductive layer 15. Among them, the material of the second gate dielectric layer 16 may be silicon dioxide, and the second gate dielectric layer may be deposited at 400 ~ 450 ° C at a low temperature oxidative deposition method, preferably, the second gate The thickness of the dielectric layer is 1000A. Finally, as shown in Figure 1G, an upper gate 17 is formed over the second gate dielectric layer 16. Among them, a polycrystalline silicon layer can be deposited on the second gate dielectric layer 16 first, and then the polycrystalline silicon layer is chemically and mechanically polished, and then stopped on the second gate dielectric layer 16, and this polycrystalline silicon layer forms the upper gate 1 7. At this point, the fabrication of a self-aligned double-gate thin film transistor is completed. Traditionally, the lower gate and the upper gate are formed by two photomasks respectively, so 'mis-alignment' will cause the problem of misalignment between the upper gate and the lower gate; relatively speaking, the present invention only A photomask is used to form the lower gate 11 (Figure 1A), and the upper gate is formed by depositing a polycrystalline silicon layer and polishing to form the upper gate 1 7 (Figure 1G). Therefore, the upper gate 1 is not caused. 7 The problem of misalignment with the lower gate 11 can be avoided by the present invention. In addition, as the material of the semiconductor layer 14 of the present invention, polycrystalline silicon germanium (Figure 1G) can be selected as the source / drain of the thin film transistor. The related technology indicates that polycrystalline silicon germanium has a lower energy gap width than the conventional technology using silicon at the source extreme , Can reduce the contact resistance of the source / electrode, improve the problem of kink effect, and increase the output impedance (gain) and gain (gain).
第11頁 200408011 五、發明說明（6) 如熟悉此技術之人員所瞭解的，以上所述僅為本發明之 較佳實施例而已，並非用以限定本發明之申請專利範圍； 凡其它未脫離本發明所揭示之精神下所完成之等效改變或 修飾，均應包含在下述之申請專利範圍内。Page 11 20040011 V. Description of the invention (6) As understood by those skilled in the art, the above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of patent application of the present invention; Equivalent changes or modifications made under the spirit disclosed by the present invention should all be included in the scope of patent application described below.
第12頁 200408011 圖式簡單說明 圖式簡單說明： | 本發明的較佳實施例於前述之說明文字中輔以下列圖形 做更詳細的闞述，其中： 第1 A〜1 G圖為繪示本發明製作自我對準之雙閘極薄膜電 晶體之剖面結構流程不意圖。 圖號對照說明： 10基礎層11下閘極 1 2第一閘極介電層1 3絕緣層 14半導體層15導通層 16第二閘極介電層17上閘極Page 12 20040011 Brief description of the diagram Brief description of the diagram: The preferred embodiment of the present invention is supplemented by the following figures in the preceding explanatory text for a more detailed description, in which: Figures 1 A to 1 G are for illustration The cross-sectional structure process of manufacturing the self-aligned double-gate thin film transistor of the present invention is not intended. Drawing number comparison description: 10 base layer 11 lower gate 1 2 first gate dielectric layer 1 3 insulating layer 14 semiconductor layer 15 conduction layer 16 second gate dielectric layer 17 upper gate
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