200405434 玖、發明說明： 發明所屬之技術 本發明是有關於一種製造半導體元件的方法，且較特 別的是’有關與一種在半導體元件中形成一高介電層的方 法。 先前技術 一般而言’當半導體元件具有高密度集成以及其容量 增加時’聞隔絕層（gate insulating layer)的厚度會變小。因 其具有高熱穩定度、高可靠度、以及容易生產的優點，所 以一般以二氧化矽層（silicon oxide，Si02)層當成閘隔絕層 使用。然而，二氧化矽層的介電常數(dielectric constant)大 約爲3·9 ’因爲當二氧化矽層厚度減少時，漏電電流會大量 增加’所以使二氧化矽層具有縮放比例（scaling)的限制。 對於使用一種高介電層，以取代二氧化矽層當成閘隔 絕層的硏究，目前已經獲得相當進展。如果高介電層被用 來當成閘隔絕層，則藉由在保持相同電容値的條件之下， 將高介電層製造成較二氧化矽層厚度爲薄，即可降低其漏 電流。其中，（Bax，Sri.x)Ti03(BST)、Ti02、Ta205、Al2〇3、 ΖιΌ2、Zr矽酸鹽（silicate)、Hf02、Hf砂酸鹽、以及其他類似 材料，都可當成高介電層使用。 然而，如果將高介電層當成閘隔絕層使用，則上述的 高介電層會具有下列問題。換言之，如果將一個BST層、Ti02 層、或是一個Ta205層直接沈積（deposited)在一矽基底 (silicon substrate)上，則其與矽基底的界面特性(interfacial 12209pif.doc/008 6 200405434 characteristics)會變得薄弱，因此會使漏電流增加。此外， 界面陷阱電荷密度（interface trap charge density)也會增 加，而且遷移率（mobility)會大量降低。 雖然氧化鋁（aluminum oxide，Al2〇3)層具有高熱穩定性 的優點。然而，其介電常數相當低，大約只有11左右，而 且很難控制其臨界電壓（threshold voltage)Vth。 氧化鍩（zirconium oxide，Zr02)層、銷石夕酸鹽層Zr-Si_ 〇、氧化給(hafnium oxide，Hf02)層、以及給酸鹽層Hf-Si-0 ’ 都具有適當的熱穩定性，以及一般水平的介電常數’大約 爲12-25左右，可建議用來當成閘隔絕層使用。然而’因爲 氧化锆層會與多晶矽(polysilicon)相互作用，所以不適合將 氧化锆層單獨用來當成閘隔絕層使用。當氧化給層變厚 時，會變得容易結晶（crystallized)，因此經由晶粒邊界（Srain boundary)的漏電流就會增加。此外，氧化锆層與氧化給層 的臨界電壓都很難控制，使其達到一臨界電壓値。 發明內容 有鑑於此，本發明提供一種在半導體元件中成形一高 介電層的方法，該方法可補償使用氧化鋁層與氧化給層（或 氧化锆層）當成高介電層使用的每一層的弱點，並且加強每 一層的優點。 爲達成本發明之目的，本發明提供一種在半導體元件 中成形一高介電層的方法，該方法包括下列步驟：在一個 石夕基底上成形商介電層，其中該高介電層是藉由輪流沈積 氧化飴層（或氧化鐯層）與一個三群金屬氧化層（3-group 12209pif.doc/008 7 200405434 metal oxide layer)，戶斤成开多的一個奈米薄片(nano laminate) 所組成。如必要的話，再成形高介電層之前’可先成形一 個臭氧氧化層（ozone oxide layer)。接下來，在其上成形高 介電層的矽基底上，會執行表面氮化(nitriding)。接下來， 在其上施加表面氮化的矽基底上，會執行如退火（annealing) 或氧化（oxidizing)的後處理（post treating)。 三群金屬層是一個氧化鋁層或一個氧化釔層（yttrium oxide layer)。奈米薄片是藉由在矽基底上，更加沈積紿矽 酸鹽、锆矽酸鹽、以及鋁矽酸鹽的其中之一所成形。 表面氮化是使用一個氮氣電漿處理（nitrogen plasma treatment)、在氮氣環境中的熱處理、或是在高介電層上成 形氮層之後的熱處理所執行。退火是在一個惰性氣體（inert gas)、高氫、氣、氮與氫的混合氣體、或是真空的環境中所 執行。 退火較偏好是在攝氏950-1 100度的高溫之下執行。氧 化是藉由將其上成形高介電層的矽基底溼氧化（wet oxidizing)或乾氧化(dry oxidizing)所執行。氧化是藉由使用 臭氧、radical oxygen、以及oxygen plasma的其中之一，氧 化其上成形高介電層的矽基底所執行。 根據本發明另一方面，本發明提供一種的在導體元件 中成形一高介電層的方法，該方法包括下列步驟：在一個 矽基底上成形高介電層，其中該高介電層是藉由輪流沈積 氧化給層（或氧化锆層)與一個三群金屬氧化層，所成形的一 個奈米薄片所組成。如必要的話，再成形高介電層之前， 12209pif.doc/008 8 200405434 可先成形一個臭氧氧化層。接下來，在其上成形高介電層 的石夕基底上，會執行表面氮化。接下來，在其上施加表面 氮化的矽基底上，會執行如退火與氧化的後處理。 三群金屬層是一個氧化鋁層或一個氧化釔層。表面氮 化是使用一個氮氣電漿處理、在氮氣環境中的熱處理、或 是在高介電層上成形氮層之後的熱處理所執行。 氧化是藉由將其上成形高介電層的矽基底溼氧化或乾 氧化所執行。氧化是藉由使用臭氧、radical oxygen、以及 oxygen plasma的其中之一，氧化其上成形高介電層的砂基 底所執行。 退火是在一個惰性氣體、高氫、氫、氮與氫的混合氣 體、或是真空的環境中所執行。氧化較偏好是在攝氏700-900 度的低溫之下執行，而退火則較偏好是在攝氏950-1100度的 局溫之下執行。 如上所述，根據本發明在半導體元件中成形一高介電 層的方法，可獲得一個具有極佳遷移率與界面特性的高介 電層。此外，藉由在成形高介電層之前，先成形一個臭氧 界面氧化層，可不用增加等效氧化層，即可降低漏電流負 偏壓溫度不穩定性（negative bias temperature instability，以 下簡稱NBTI)。 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特以較佳實施例，並配合所附圖式，作詳細 說明如下： 實施方式· 12209pif.doc/008 9 200405434 以下將參考所附繪圖，詳細說明本發明的較佳實施 例。雖然本發明在此以較佳實施例說明，但本發明亦可以 其他多種不同形式實現，並不受限於在此所說明的實施 例。因此，在此所說明的實施例之目的爲使熟知相關技藝 者’充分明瞭本發明之要旨。 首先將分析尚介電層間的氧化錦層與氧化給層的電氣 與物理特性。 相較於在氧化砂層（silicon oxide layer)中，在氧化錦層 中的平帶電壓（flatband voltage)較偏向電容-電壓圖的右邊 移動’追個事實指出在氧化銘層中，有一個負固定電荷存 在。而相較於在氧化矽層中，在氧化給層(或氧化鉻層）中的 平帶電壓則較偏向電容-電壓圖的左邊移動，這個事實指出 在氧化給層中，有一個正固定電荷存在。相較於其他高介 電層’氧化銘層具有最佳熱穩定性，然而，其介電常數大 約爲11，相較於其他高介電層，其介電常數較低。另一方 面’不僅具有較高介電常數，大約爲12-25，而且具有氧化 鈴層(或氧化鉻層)極佳熱穩定性。但是，氧化鉻層會在多晶 矽層上起作用，而氧化給層則容易結晶，因此經由晶粒邊 界的漏電流會增加。 爲了強化氧化鋁層與氧化給層(或氧化鉻層）的優點，以 及補償其缺點，本發明作者採用一種藉由輪流沈積一種具 有正固定電荷與極佳熱穩定性的氧化鋁層，以及一種具有 負固定電荷與高介電常數的氧化給層(或氧化鉻層），所成形 的奈米薄片，當成半導體元件的高介電層使用。此外，本 12209pif.doc/008 10 200405434 發明作者使用奈米薄片當成半導體元件的高介電層使用， 其中奈米薄片是藉由輪流沈積氧化給層（或氧化鉻層）與如 氧化釔層的三群金屬氧化層，取代氧化鋁層所成形。本發 明作者使用輪流沈積氧化鋁層（或氧化釔層）與氧化給層（或 氧化絡層）所成形的奈米薄片，並且根據原子層（at〇rnic iayer) 沈積的發展結果，調整其厚度與成分。 再者，本發明作者注意到如給矽酸鹽、鉻矽酸鹽、或 鋁矽酸鹽的矽酸鹽材料的介電常數爲1(μΐ2,而且在矽基底 中相當穩定’因此在矽基底上可更加成形矽酸鹽材料，以 成形高介電層。且較特別的是，如飴矽酸鹽（或鉻矽酸鹽） 的砂酸鹽材料，在攝氏9〇〇度的熱度下會保持非晶形 (amorphous)，因此如果將其當成閘絕緣層，會具有極佳的 界面特性。 接下來’如果將輪流沈積氧化鋁層(或氧化釔層）與氧化 給層(或氧化鉻層），所成形的奈米薄片，當成半導體元件的 尚介電層使用，則會發生例如像是硼(b〇b〇n)穿透矽基底、 砂基底與高介電層之間的界面特性惡化、nM0S(n通道金屬 氧化半導體）中的雜質遷移率退化的各種問題。爲解決這些 問題’本發明作者提出一種做爲半導體元件的高介電層的 後熱處理之方法。 第一實施例 弟1圖係顯不·一個用來說明根據本發明一第一實施 例’在半導體兀件中成形一高介電層的方法的示意圖。 較明確地說，給矽酸鹽（或鉻矽酸鹽）與如氧化鋁層 12209pif.doc/008 200405434 的三群金屬層會輪流沈積，以成形一個奈米薄片，並且在 一個矽基底10上，藉由該奈米薄片，成形一個高介電層12。 鉛矽酸鹽（或鉻矽酸鹽)與三群金屬層，會使用原子層沈積， 成形奈米薄片。給矽酸鹽(或鉻矽酸鹽）具有高介電常數以及 負固定電荷。當成三群金屬層的氧化鋁層，則具有正固定 電荷與極佳熱穩定性。此外，因爲如飴矽酸鹽、鉻矽酸鹽、 或鋁矽酸鹽的矽酸鹽材料的介電常數爲10-12,而且在矽基 底上相當穩定，所以可在矽基底上更加成形一個矽酸鹽材 料，以成形高介電層。 接下來會使用如下列實施例中所描述的各種方法的其 中任一種方法，對其上成形高介電層12的矽基底10，執行 後熱處理。一個多晶砂層(polysilicon layer)14會成形在高 介電層12上。並且將砷（Arsenic，As)注入其上成形多晶砂 層14的矽基底上的nMOS，以及將硼(boixm，B)注入其上成 形多晶矽層14的矽基底上的pMOS(p通道金屬氧化半導 體）。接下來，會對矽基底10執行退火，使矽基底10變成 一低電極（lower electrode)，而多晶5夕層14變成一高電極 (upper electrode) 〇 像這樣的半導體元件，被用來根據下列的熱處理方 法，評估高介電層12的特性。此外，在本實施例中的高介 電層12，亦可被評估當成閘隔絕層使用。然而，亦可將該 高介電層12應用於半導體元件的一電容器隔絕層，或是一 非揮發性（non-volatile)元件的浮動閘（floating gate)與控制 閘（control gate)之間的一隔絕層。 12209pif.doc/008 12 200405434 第2圖係顯示一個流程圖，用來說明根據本發明在半 導體元件中成形一高介電層的方法的一個後熱處理的範 例。 較明確地說，在步驟100中，會對矽基底10執行氮化 處理，而且藉由輪流沈積氧化給層（或氧化鉻層）與如氧化鋁 層的三群金屬氧化層，而成形的一奈米薄片所成形的一個 高介電層12，是成形在矽基底10上。 執行氮化處理的目的是避免包含在多晶矽高電極中的 硼，因爲高介電層容易結晶的關係，經由晶粒邊界，滲透 入高介電層12。如果因爲氮化處理，使得在矽基底10與高 介電層12的介面存在氮，則硼的遷移率就會退化。因此， 必須在存在可觀氮量的高介電層上側，也就是多晶矽的高 電極，以及存在少量氮的矽基底中，成形一個氮輪廓 (nitrogen profile)，藉以避免硼滲透入高介電層12，其詳情 如第1圖的參考號碼16所示。因爲在保持相同電容値的條 件之下，高介電層12可比習知的氧化矽層還厚，所以可輕 易地調整氮輪廓。 表面氮化是使用一個氮氣電漿處理、在氮氣環境中的 熱處理、或是在高介電層12上成形氮層之後的熱處理所執 f了。氮热電發處理是使用 decoupled plasma、remote plasma、 或氨(ammonia)plasma所執行。熱處理是在氨(Nh3)或氧化氮 (N2〇或NO)環境中所執行的一種氮環境的熱處理。 接下來，在步驟12〇中，會對其上施加氮化處理的矽基 底10,執行一個後處理。由於在氮化處理之後的陷阱點（trap 12209pif.doc/008 13 200405434 sites)增加的原因，可能會造成漏電流增加，所以需要執行 後處理。後處理是藉由在其上成形高介電層12的矽基底10 上，執行退火或氧化處理所執行。像這樣根據本發明的高 介電層12，具有高品質、強界面特性、以及高遷移率的優 點。 第3圖係顯示一個流程圖，用來說明根據本發明在半導 體元件中成形一高介電層的方法的另一個後熱處理的範 例。 較明確地說，在步驟100中，會對矽基底10執行氮化 處理，而且藉由輪流沈積氧化給層(或氧化鉻層)與如氧化鋁 層的三群金屬氧化層，而成形的一奈米薄片所成形的一個 高介電層12，是成形在砂基底10上。氮化處理的方法與效 果，與第2圖中所描述的相同。 接下來，在步驟22〇中，會在其上施加氮化處理的矽基 底10上執行退火。退火是在一個惰性氣體、高氫、氫、氮 與氫的混合氣體、或是真空的環境中所執行。退火是在攝 氏950-1 100度的高溫之下執行。在高溫之下執行的退火可加 強增濃（densification)效果，並且提供一個強化界面層。退 火可修復沈積至少兩個金屬氧化層可能造成的缺陷。根據 本發明的高介電層12，具有高品質、強界面特性、以及高 遷移率的優點。 第4圖係顯示一個流程圖，用來說明根據本發明在半導 體元件中成形一高介電層的方法的再另一個後熱處理的範 例。 12209pif.doc/008 200405434 較明確地說，在步驟100中，會對矽基底10執行氮化處 理，而且藉由輪流沈積氧化給層(或氧化鉻層）與如氧化鋁層 的三群金屬氧化層，而成形的一奈米薄片所成形的一個高 介電層I2,是成形在矽基底10上。氮化處理的方法與效果， 與第2圖中所描述的相同。 接下來，在步驟320中，會在其上施加氮化處理的矽基 底10上執行氧化處理。氧化處理不只可修復缺陷，例如移 除像是在局介電層12中的氧空隙（oxygen vacancy)的陷讲 點，同時亦可滿足金屬氧化層的化學計量法 (stoichiometry) 〇 氧化處理可藉由溼氧化或乾氧化其上成形高介電層12 的矽基底10執行。溼氧化是使用H20、ISSG(原地產生蒸汽 (In-Situ Steam Generation))、或 WVG(水蒸汽產生（water vapor generation))所執行。在乾氧化中，具有高介電層的矽 基底，是在一個氧化氮或氧的環境中被氧化。此外，氧化 處理也可以藉由使用臭氧、radical oxygen、或oxygen plasma，氧化具有高介電層的矽基底執行。像這樣的根據本 發明的高介電層，具有高品質、強界面特性、以及高遷移 率的優點。 第5圖係顯示一個流程圖，用來說明根據本發明在半導 體元件中成形一高介電層的方法的再另一個後熱處理的範 例。 較明確地說，在步驟1〇〇中，會對矽基底10執行氮化處 理，而且藉由輪流沈積氧化給層(或氧化鉻層）與如氧化鋁層 12209pif.doc/008 15 200405434 的三群金屬氧化層，而成形的一奈米薄片所成形的一個高 介電層12,是成形在矽基底1〇上。氮化處理的方法與效果， 與弟2圖中所描述的相同。 接下來，在步驟320中，會在其上施加氮化處理的砂基 底1〇上執行氧化處理。氧化處理的方法與效果，與第4圖中 所描述的相同。氧化處理是在攝氏700-900度的低溫之下執 行。接下來，會對其上施加氮化處理與氧化處理的矽基底， 執行退火。退火的方法與效果，與第3圖中所描述的相同。 退火是在攝氏950-11〇〇度的高溫之下執行。像這樣的根據本 發明的高介電層，具有高品質、強界面特性、以及高遷移 率的優點。 針對後熱處理方法，下文將說明一個半導體元件的電 氣特性。其中，以輪流沈積氧化給層(或氧化鉻層）與氧化鋁 層（或氧化釔層)成形的奈米薄片所成形的高介電層，會成形 在半導體元件上。 在製造RTA的範例中，首先會使用原子層沈積，在矽 基底10上成形一厚度爲50埃（為的高介電層12，並且接下來 在氮氣的環境，以攝氏950度的溫度，對高介電層12，執行 30秒的快速熱退火處理。在製造RTNOA的範例中，首先會 在矽基底1〇上成形一厚度爲50埃（為的奈米薄片所成形的高 介電層12，並且接下來在氨氣的環境，以攝氏750度的溫 度，對高介電層12，執行60秒的氮化處理。接下來，在氧 氣的環境，以攝氏850度的溫度，對高介電層12，執行30秒 的氧化處理，並且在氮氣的環境，以攝氏950度的溫度，對 1 2209pif.doc/008 200405434 高介電層12，執行30秒的退火處理，藉以完成整個後熱處 理。接下來，多晶矽層14會沈積在RTA與RTNOA範例的高 介電層12上。此外，在沈積多晶矽層14之後，會將砷（As) 注入到nMOS，硼（B)注入到pMOS，並且以攝氏1000和1025 度的溫度，執行退火處理。 本發明是藉由使用RTNOA範例，評估高介電層的電氣 特性。然而，在執行氮化處理之後，其上可選擇性地執行 退火或氧化處理的高介電層的特性並未具有重大改變。 第6A圖和第6B圖係顯示根據本發明的一個RTA範例的 nMOS(n通道金屬氧化半導體（metal oxide semiconductor，以 下簡稱MOS)與pMOS(p通道金屬氧化半導體）的C-V曲線 圖。 較明確地說，如第6A圖所示，對於兩個啓動溫度 (activation temperatures)而言，在nMOS中的C-V曲線彼此之 間並未具有極大差異。然而，如第6B圖所示，在pMOS中， 以攝氏1000度退火的RTA範例呈現正常的C-V曲線，而以攝 氏1025度退火的RTA範例則呈現反常的C-V曲線。pMOS的 反常C-V曲線，是由於硼滲透造成界面特性退化的關係所產 生。 第7圖係顯示根據本發明的RTNOA範例與RTA範例的 漏電流與等效氧化厚度（equivalent oxide thickness，以下簡 稱EOT)的相互關係圖。其中，x-軸代表等效氧化厚度 (EOT)，而y-軸則代表在1.5伏特的漏電流。 較明確地說，第7圖係顯示RTNOA與RTA範例在1.5伏 12209pif.doc/008 17 200405434 特的nMOS累積區的漏電流與EOT値之間的相互關係。對相 同漏電流而言，相較於其中以氧化矽層當成閘隔絕層，而 且接下來執行氮化處理，具相同步漏電流的NSIO範例而 言，RTA與RTNOA範例具有較小的EOT値，而且其厚度少 4-5埃（為。此外，對相同漏電流而言，相較於RTNOA範例， RTA範例具有較小的EOT値。然而，因爲PMOS特性並未呈 現在由於硼滲透造成厚度少40埃（為的RTA範例中，所以就 可縮放性（scalability)而言，並不確定RTA範例的特性是否 較RTNOA範例爲優良。 第8A圖和第8B圖係顯示根據本發明的RTA範例的 nMOS與pMOS的C_V曲線圖。第9A圖和第9B圖係顯示 根據本發明的RTNOA範例的nMOS與pMOS的C-V曲線 圖。其中，第8A圖、第8B圖、第9A圖、和第9B圖中的 y-軸代表正規化電容値（normalized capacitances)。 較明確地說，如第8A圖和第8B圖所示，RTA範例的 C-V磁滯曲線(hysteresis curves)之間的寬度很大，也就是 0.37伏特或0.39伏特。另一方面，如第9A圖和第9B圖所 示，RTNOA範例的C-V磁滯曲線之間的寬度是小於0.1伏 特。這個現象說明了 RTNOA範例的界面特性較RTA範例 的界面特性爲優秀的事實。 第10A圖和第10B圖係顯示與根據本發明的RTA範例 與RTNOA範例的nMOS與pMOS電場有關的Gm(跨導値 (transconductance)的圖形。第 10A 圖和第 10B 圖中，CET 代表電容測量等效氧化厚度，Vg代表閘電壓，而且Vth代 12209pif.doc/008 200405434 表臨界電壓。pMOS與nMOS的寬度W與長度L分別爲10 和 〇·1 。 爲觀察遷移率特性，必須估算Gm(跨導値 (transconductance)。Gm是根據是使用其上施加氮化處理的 氧化層，當成用來比較的介電層的NSIO範例所代表。相較 於使用氮化處理的氧化層當成介電層的NSIO範例，在RTA 範例中的nMOS中的Gm只有45%，而且相較於NSIO範 例，在RTA範例中的pMOS中的Gm只有51%。因此遷移 率會大幅度降低。另一方面，相較於NSIO範例，在RTNOA 範例中的nMOS中的Gm只有78%，而且相較於NSIO範 例，在RTNOA範例中的pMOS中的Gm只有79%。因此， 相較於RTA範例而言，RTNOA範例的遷移率並未大幅度降 低。 第11A圖和第11B圖係顯示在根據本發明的RTA範例 與RTNOA範例的nMOS與pMOS的開啓狀態（on-state)的電 流Ion與關閉狀態(off-state)的電流Ioff的關係圖。其中， 汲電壓（drain voltage)設定成1.2伏特。 較明確地說，如第11A圖和第11B圖所示，相較於NSIO 範例而言，RTA範例的nMOS與pMOS的開啓狀態電流(或 驅動電流），分別是關閉狀態電流，也就是1〇ηΑ的52%與 50%。另一方面，相較於NSI◦範例而言，RTNOA範例的 nMOS與pMOS的開啓狀態電流，分別是關閉狀態電流，也 就是1〇ηΑ的81%與80%。 下列的第1表簡單繪示RTA與RTNOA範例的電氣特 12209pif.doc/008 19 200405434 性。 [第1表] \ 條件 結果 \ CET (累積） CET (反相） 閘消耗 磁滯曲線 寬度 與正規化 範例的 Gm比率 與正規化 範例的開 啓電流比 率 RTA nMOS 22.7 26.8 83.9% 0.37 45% 52% 範例 pMOS 20.9 30.6 68.3% 0.39 51% 50% RTNO nMOS 24.0 28.1 85.4% >0.1 78% 81% A範 例 pMOS 23.3 32.5 71.7% >0.1 79% 80% 如第1表所示，在RTA範例中，在累積區中的nMOS 與pMOS的電容測量等效氧化厚度CET分別爲22.7埃（今 與20.9埃（為，而在反相區中，則分別爲26.8埃（為與30.6 埃（為。另一方面，在RTNOA範例中，在累積區中的nMOS 與pMOS的電容測量等效氧化厚度CET分別爲24.0埃（為 與23·3埃（今，而在反相區中，則分別爲28.1埃（今與32.5 埃（為。因此，RTNOA範例具較大的CET値。然而，RTNOA 範例在漏電流方面有相當極限，而且可藉由使用後熱處 理，調整其氧化量。對閘消耗而言，RTA的nMOS與pMOS 分別爲84%與68%。然而，RTNOA的nMOS與pMOS則分 別爲85%與72%，這個事實証明RTNOA範例較爲優秀。 最後，相較於RTA範例而言，RTNOA範例表現較隹 的閘消耗特性、較小寬度的磁滯曲線、以及較佳遷移率。 雖然RTNOA具有較大CET値的缺點，但其在漏電流方面， 1 2209pif.doc/008 20 200405434 仍具有相當極限，因此可藉由最佳化氧化的溫度，而降低 其CET値。 第二實施例 第12圖係顯示一個用來說明根據本發明一第二實施 例’在半導體元件中成形一高介電層的方法的示意圖。 明確地說，在第1圖和第12圖中，相同的參考號碼係 代表類似元件。此外，除了臭氧界面氧化層11是在成形高 介電層12之前所成形之外，就其影響及結構而言，根據本 發明一第二實施例，在半導體元件中成形高介電層的方 法，係與第一實施例類似。 較明確地說，臭氧界面氧化層11是使用臭氧，成形在 矽基底10上。厚度爲8埃（為的臭氧界面氧化層11，是在 攝氏320-450度的溫度下成形。臭氧界面氧化層U是使用 一般用於成形高介電層的一種原子層沈積裝置，在原處以 臭氧沖洗矽基底10所成形。此外，亦可使用一種個別的化 學蒸發沈積裝置，成形該臭氧界面氧化層11。 接下來，高介電層12會以第1圖所示的方式，成形在 臭氧界面氧化層11上。接下來，其上成形高介電層12的 矽基底10，會以第2圖到第5圖所示的相同方式，執行後 熱處理。多晶矽層14會成形在高介電層12上。砷（As)會注 入到其上成形多晶矽層14的矽基底10上的nMOS，而硼（B) 則會注入到矽基底10上的pMOS。接下來，用來啓動的退 火處理，會施加到矽基底10上，以使得矽基底10變成一 個低電極，而多晶矽層14則變成一個高電極。 12209pif.doc/008 200405434 以下是根據本發明第二實施例，其上附加成形臭氧界 面氧化層π的半導體元件電氣特性的評估。 下列的RTNOA範例是以如第1圖所示的相同方式製 造。除了如第二實施例所述，在矽基底10上成形臭氧界面 氧化層11之外，ORTNOA範例是以與RTNOA範例相同的 方式所製造。NSIO範例採用一種氧化氮層（nitrided oxide layer)，當成介電層。多晶矽層會沈積在RTNOA範例、 ORTNOA範例、與NSIO範例的高介電層上。在沈積多晶 矽層之後，砷（As)會注入到nMOS，而硼（B)則會注入到 pMOS。接下來，會以攝氏1000-1025度的溫度，執行用來 啓動的退火。 較明確地說，本發明的第二實施例會使用ORTNOA範 例’評估高介電層的電氣特性。然而，在其上成形臭氧界 面氧化層與高介電層的矽基底上，執行氮化處理之後，選 擇性地執行退火或氧化處理的高介電層的特性，並未具有 重大變化。 第UA圖和第13B圖係顯示根據本發明的一個 ORTNOA範例與RTN〇A範例的漏電流圖。 _明確地說’第13A圖係顯示電流密度與閘電壓的關 係圖’而第13B圖係顯示當閘電壓爲土15伏特時的電流密 度的累積分佈圖。在第13A圖中，對X軸的中心0伏特而 言’左邊是與pMOS有關，而右邊則是與nMOS有關。在 第13B圖中’對X軸的中心1(Γ8伏特而言，左邊是與pMOS 有關’而右邊則是與nMOS有關。pMOS與nMOS的閘寬 1 2209pif.doc/008 22 200405434 度與長度，分別爲50μιη。從第13A圖和第13B圖可看出 ORTNOA範例的漏電流，明顯小於RTN0A範例或NSI0箪危 例的漏電流。此外，0RTN0A範例與RTNOA範例的等效氧 化層厚度分別爲19·9埃（為與19·7埃（為’彼此之間並未具 有很大差異。因此，可不用增加等效氧化層的厚度’即可 降低ORTNOA範例的漏電流。 第14圖係顯示一個用來說明根據本發明的ORTNOA 範例與RTNOA範例的負偏壓溫度不穩定性(NBTI)的示意 圖。 較明確地說，一旦電壓與溫度壓力施加到半導體元件 之後，即可發現電晶體的臨界電壓Vt移動。一般而言，當 臨界電壓Vt位移超過50mV時，電晶體壽命即被認定已告 結束。在第14圖中，X軸代表閘電壓，而y軸則代表電晶 體壽命。在ORTNOA範例中，-2.32伏特的閘電壓可保証 10年壽命。在RTNOA範例中，-1.53伏特的閘電壓可保証 10年壽命。當與RTNOA範例相比時，ORTNOA範例具有 大約0.8伏特的優勢，因此其NBTI可降低。 第15A圖和第15B圖係顯示根據本發明的ORTNOA 範例與RTNOA範例的C-V特性與Gm(跨導値)特性圖。 較明確地說，如第15A圖和第15B圖所示，就C-V特 性與Gm的最大値（Gmmax)而言，在ORTNOA範例與 RTNOA範例之間，並未發現巨大差異。綜合上述說明，當 與RTNOA範例相比時，根據本發明第二實施例的ORTNOA 範例，在不惡化電氣特性的條件之下，較能降低漏電流與 12209pif.doc/008 23 200405434 NBTI。 如上所述，根據在一半導體元件中成形高介電層的方 法，可獲得具較佳遷移率與界面特性的高介電層。此外’ 藉由在成形高介電層之前，先成形一個臭氧界面氧化層， 可不用增加等效氧化成的厚度，即可降低漏電流負偏壓溫 度不穩定性(NBTI)。 根據本發明的高介電層，亦可用來當成半導體元件的 電容器隔絕層、揮發性裝置的浮動閘與控制閘之間的隔絕 層、與半導體元件的閘隔絕層使用。 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，任何熟習此技藝者，在不脫離本發明之精神 和範圍內，當可作各種之更動與潤飾，因此本發明之保護 範圍當視後附之申請專利範圍所界定者爲準。 圖式簡單說明 第1圖係顯示一個用來說明根據本發明一第一實施 例，在半導體元件中成形一高介電層的方法的示意圖。 第2圖係顯示一個流程圖，用來說明根據本發明在半 導體元件中成形一高介電層的方法的一個後熱處理的範 例。 第3圖係顯示一個流程圖，用來說明根據本發明在半 導體元件中成形一高介電層的方法的另一個後熱處理的範 例。 第4圖係顯示一個流程圖，用來說明根據本發明在半 導體元件中成形一高介電層的方法的再另一個後熱處理的 12209pif.doc/008 24 200405434 範例。 第5圖係顯示一個流程圖，用來說明根據本發明在半 導體元件中成形一高介電層的方法的再另一個後熱處理的 範例。 第6A圖和第6B圖係顯示根據本發明的一個RTA範例 的 nMOS(n 通道金屬氧化半導體（metal oxide semiconductor， 以下簡稱M0S)與pM0S(p通道金屬氧化半導體）的C-V曲 線圖。 第7圖係顯示根據本發明的RTN0A範例與RTA範例 的漏電流與等效氧化厚度（equivalent oxide thickness，以下 簡稱EOT)的相互關係圖。 第8A圖和第8B圖係顯示根據本發明的RTA範例的 nMOS與pMOS的C-V曲線圖。 第9A圖和第9B圖係顯示根據本發明的RTN0A範例 的nMOS與pMOS的C-V曲線圖。 第10A圖和第10B圖係顯示與根據本發明的RTA範例 與RTN0A範例的nM〇s與PM〇s電場有關的Gm(跨導値 (transconductance)的圖形。 第11A圖和第11B圖係顯示在根據本發明的RTA範例 rtn〇A範例白勺nM〇S與pMOS白勺開啓狀態(on-state)的電 流I〇n與關閉狀態（〇ff-state)的電流Ioff的關係圖。 第12圖係顯示一個用來說明根據本發明一第二實施 例，在半導體元件中成形一高介電層的方法的示意圖。 第13A圖和第13B圖係顯示根據本發明的一個 25 12209pif.doc/008 200405434 ORTNOA範例與RTN〇A範例的漏電流圖。 弟14圖係顯不一個用來說明根據本發明的〇Rtn〇a 範例與RTNOA範例的負偏壓溫度不穩定性(NBTI)的示意 画。 第15A圖和第15B圖係顯示根據本發明的ORTNOA 範例與RTNOA範例的C-V特性與Gm(跨導値)特性圖。 圖式標記說明z 10 :矽基底 12 :高介電層 14 :多晶矽層 16 :氮輪廓 100,120,220,320,420,440 ··流程步驟 12209pif.doc/008 26200405434 (1) Description of the invention: The technology to which the invention belongs The present invention relates to a method for manufacturing a semiconductor element, and more particularly, it relates to a method for forming a high dielectric layer in a semiconductor element. Prior art Generally speaking, when a semiconductor element has high density integration and its capacity is increased, the thickness of the gate insulating layer becomes smaller. Because of its advantages of high thermal stability, high reliability, and easy production, silicon oxide (Si02) layer is generally used as the gate insulation layer. However, the dielectric constant of the silicon dioxide layer is about 3 · 9 'because when the thickness of the silicon dioxide layer is reduced, the leakage current will increase significantly', so the silicon dioxide layer has a limitation of scaling . Considerable progress has been made on the use of a high dielectric layer to replace the silicon dioxide layer as a gate insulation. If the high dielectric layer is used as a gate insulation layer, the leakage current can be reduced by making the high dielectric layer thinner than the silicon dioxide layer while maintaining the same capacitance. Among them, (Bax, Sri. x) Ti03 (BST), Ti02, Ta205, Al203, Zircon 2, Zr silicate, Hf02, Hf oxalate, and other similar materials can be used as high dielectric layers. However, if the high dielectric layer is used as a gate insulation layer, the above high dielectric layer has the following problems. In other words, if a BST layer, a Ti02 layer, or a Ta205 layer is directly deposited on a silicon substrate, its interface characteristics with the silicon substrate (interfacial 12209pif. doc / 008 6 200405434 characteristics) will become weak, which will increase the leakage current. In addition, the interface trap charge density will also increase, and the mobility will decrease significantly. Although an aluminum oxide (Al203) layer has the advantage of high thermal stability. However, its dielectric constant is quite low, only about 11, and it is difficult to control its threshold voltage Vth. The zirconium oxide (Zr02) layer, the pinite layer Zr-Si_ 0, the hafnium oxide (Hf02) layer, and the salt-donating layer Hf-Si-0 'all have appropriate thermal stability, And the general level of dielectric constant is about 12-25, which can be recommended to be used as a gate insulation layer. However, because the zirconia layer interacts with polysilicon, it is not suitable to use the zirconia layer alone as a gate insulation layer. When the oxide-feeding layer becomes thicker, it becomes easier to crystallize, so the leakage current through the grain boundary increases. In addition, the critical voltages of the zirconia layer and the oxide-donating layer are difficult to control so that they reach a critical voltage 値. SUMMARY OF THE INVENTION In view of this, the present invention provides a method for forming a high dielectric layer in a semiconductor device, which method can compensate each layer used as a high dielectric layer using an aluminum oxide layer and an oxide donating layer (or a zirconia layer). The weaknesses and strengths of each layer are enhanced. In order to achieve the purpose of the present invention, the present invention provides a method for forming a high dielectric layer in a semiconductor device. The method includes the following steps: forming a commercial dielectric layer on a Shi Xi substrate, wherein the high dielectric layer is formed by The hafnium oxide layer (or hafnium oxide layer) and a three-group metal oxide layer (3-group 12209pif. doc / 008 7 200405434 metal oxide layer), which is composed of a nano laminate. If necessary, an ozone oxide layer can be formed before the high dielectric layer is formed. Next, on a silicon substrate on which a high dielectric layer is formed, surface nitriding is performed. Next, on the silicon substrate on which the surface nitride is applied, post treatment such as annealing or oxidation treatment is performed. The three groups of metal layers are an aluminum oxide layer or a yttrium oxide layer. Nano flakes are formed by depositing one of erbium silicate, zirconium silicate, and aluminosilicate on a silicon substrate. Surface nitriding is performed using a nitrogen plasma treatment, a heat treatment in a nitrogen environment, or a heat treatment after forming a nitrogen layer on a high dielectric layer. Annealing is performed in an inert gas, high hydrogen, gas, a mixed gas of nitrogen and hydrogen, or a vacuum environment. Annealing is preferably performed at a high temperature of 950-1 100 ° C. Oxidation is performed by wet oxidizing or dry oxidizing the silicon substrate on which the high dielectric layer is formed. Oxidation is performed by oxidizing a silicon substrate on which a high dielectric layer is formed using one of ozone, radical oxygen, and oxygen plasma. According to another aspect of the present invention, the present invention provides a method for forming a high-dielectric layer in a conductive element, the method including the following steps: forming a high-dielectric layer on a silicon substrate, wherein the high-dielectric layer is formed by It consists of alternately depositing an oxidation layer (or a zirconia layer) and a three-group metal oxide layer, and forming a nano flake. If necessary, before reshaping the high dielectric layer, 12209pif. doc / 008 8 200405434 An ozone oxide layer can be formed first. Next, on the Shi Xi substrate on which the high dielectric layer is formed, surface nitriding is performed. Next, a post-treatment such as annealing and oxidation is performed on the silicon substrate on which the surface is nitrided. The three groups of metal layers are an aluminum oxide layer or a yttrium oxide layer. Surface nitrogenation is performed using a nitrogen plasma treatment, a heat treatment in a nitrogen atmosphere, or a heat treatment after forming a nitrogen layer on a high dielectric layer. Oxidation is performed by wet or dry oxidation of a silicon substrate on which a high dielectric layer is formed. Oxidation is performed by using one of ozone, radical oxygen, and oxygen plasma to oxidize a sand substrate on which a high dielectric layer is formed. Annealing is performed in an inert gas, high hydrogen, a mixture of hydrogen, nitrogen and hydrogen, or a vacuum environment. Oxidation is preferred to be performed at a low temperature of 700-900 ° C, while annealing is preferred to be performed at a local temperature of 950-1100 ° C. As described above, according to the method of forming a high dielectric layer in a semiconductor device according to the present invention, a high dielectric layer having excellent mobility and interface characteristics can be obtained. In addition, by forming an ozone interface oxide layer before forming the high dielectric layer, the negative bias temperature instability of leakage current (hereinafter referred to as NBTI) can be reduced without increasing the equivalent oxide layer. . In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a detailed description is given below in conjunction with the preferred embodiments and the accompanying drawings, as follows: Embodiment 12209pif. doc / 008 9 200405434 Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. Although the present invention is described herein with reference to preferred embodiments, the present invention may be implemented in many other different forms and is not limited to the embodiments described herein. Therefore, the embodiments described herein are intended to make those skilled in the relevant art ' fully understand the gist of the present invention. First, the electrical and physical characteristics of the oxide layer and the oxide donor layer between the dielectric layers will be analyzed. Compared to the silicon oxide layer, the flatband voltage in the oxide layer is shifted to the right of the capacitor-voltage diagram. The fact is pointed out that there is a negative fixation in the oxide layer. The charge exists. Compared to the silicon oxide layer, the flat band voltage in the oxide donor layer (or chromium oxide layer) is shifted to the left of the capacitance-voltage diagram. This fact indicates that there is a positive fixed charge in the oxide donor layer. presence. Compared with other high dielectric layers, the oxide layer has the best thermal stability, however, its dielectric constant is about 11 and its dielectric constant is lower than that of other high dielectric layers. On the other hand, it has not only a high dielectric constant, about 12-25, but also an excellent thermal stability of a bell oxide layer (or a chromium oxide layer). However, the chromium oxide layer functions on the polycrystalline silicon layer, and the oxide donating layer is easy to crystallize, so the leakage current through the grain boundary increases. In order to strengthen the advantages of the alumina layer and the oxide layer (or chromium oxide layer), and to compensate for their shortcomings, the author of the present invention uses an aluminum oxide layer with a positive fixed charge and excellent thermal stability by alternate deposition, and a An oxide donating layer (or a chromium oxide layer) having a negative fixed charge and a high dielectric constant, and the formed nano sheet is used as a high dielectric layer of a semiconductor device. In addition, this 12209pif. doc / 008 10 200405434 The inventor uses nano flakes as the high dielectric layer of the semiconductor device. The nano flakes are formed by alternately depositing an oxidation layer (or chromium oxide layer) and three groups of metal oxide layers such as yttria Instead of the alumina layer. The author of the present invention uses nano flakes formed by alternately depositing an aluminum oxide layer (or a yttrium oxide layer) and an oxide donor layer (or an oxide complex layer), and adjusts the thickness according to the development results of atomic layer (at〇rnic iayer) deposition. With ingredients. Furthermore, the authors of the present invention have noticed that the dielectric constant of silicate materials such as silicates, chrome silicates, or aluminosilicates is 1 (μΐ2, and is quite stable in silicon substrates. Silicate materials can be formed on it to form high dielectric layers. And more specifically, oxalate materials such as rhenium silicate (or chrome silicate) will be heated at 900 degrees Celsius It remains amorphous, so if it is used as a gate insulating layer, it will have excellent interface characteristics. Next, 'If the aluminum oxide layer (or yttrium oxide layer) and the oxidation donor layer (or chromium oxide layer) are alternately deposited, When the formed nano sheet is used as the dielectric layer of a semiconductor device, for example, the interface characteristics between boron (b0bON) penetrating a silicon substrate, a sand substrate, and a high dielectric layer may deteriorate. Various problems of impurity mobility degradation in nMOS (n-channel metal oxide semiconductor). To solve these problems, the author of the present invention proposes a method for post-heat treatment of a high dielectric layer of a semiconductor element. First Embodiment 1 The picture is not displayed A schematic view of a first embodiment of the method of the present invention 'forming a high dielectric layer in a semiconductor device in Wu. More specifically, to silicate (silicate or chromium), such as alumina layer 12209pif. The three groups of metal layers of doc / 008 200405434 are deposited in turns to form a nano sheet, and a high dielectric layer 12 is formed on the silicon substrate 10 with the nano sheet. Lead silicate (or chrome silicate) and three groups of metal layers are deposited using atomic layer to form nano flakes. The silicate (or chrome silicate) has a high dielectric constant and a negative fixed charge. As an aluminum oxide layer with three groups of metal layers, it has a positive fixed charge and excellent thermal stability. In addition, because the dielectric constant of silicate materials such as rhenium silicate, chrome silicate, or aluminosilicate is 10-12, and it is quite stable on a silicon substrate, it is possible to form one more on the silicon substrate. Silicate material to form a high dielectric layer. Next, any one of various methods as described in the following embodiments is used to perform a post-heat treatment on the silicon substrate 10 on which the high dielectric layer 12 is formed. A polysilicon layer 14 is formed on the high dielectric layer 12. Arsenic (As) is injected into the nMOS on the silicon substrate on which the polycrystalline sand layer 14 is formed, and boMOS (Bixm, B) is injected into the pMOS (p-channel metal oxide semiconductor) on the silicon substrate on which the polycrystalline silicon layer 14 is formed. ). Next, the silicon substrate 10 is annealed, so that the silicon substrate 10 becomes a lower electrode, and the polycrystalline silicon layer 14 becomes an upper electrode. A semiconductor device like this is used according to The following heat treatment method evaluates the characteristics of the high dielectric layer 12. In addition, the high-dielectric layer 12 in this embodiment can also be evaluated as a gate insulation layer. However, the high-dielectric layer 12 can also be applied to a capacitor isolation layer of a semiconductor device, or between a floating gate and a control gate of a non-volatile device. One insulation layer. 12209pif. doc / 008 12 200405434 Fig. 2 is a flowchart showing an example of a post-heat treatment of a method of forming a high dielectric layer in a semiconductor element according to the present invention. More specifically, in step 100, a nitridation process is performed on the silicon substrate 10, and an oxide layer (or a chromium oxide layer) and three groups of metal oxide layers, such as an aluminum oxide layer, are alternately deposited to form a silicon oxide layer. A high-dielectric layer 12 formed by nano-sheets is formed on a silicon substrate 10. The purpose of performing the nitriding treatment is to avoid boron contained in the polycrystalline silicon high electrode, because the high dielectric layer is easily crystallized, and penetrates into the high dielectric layer 12 through the grain boundary. If nitrogen is present at the interface between the silicon substrate 10 and the high-dielectric layer 12 due to the nitriding treatment, the mobility of boron is degraded. Therefore, a nitrogen profile must be formed on the upper side of the high dielectric layer with a considerable amount of nitrogen, that is, the high electrode of polycrystalline silicon, and the silicon substrate with a small amount of nitrogen, so as to prevent boron from penetrating into the high dielectric layer 12 The details are shown in reference number 16 in Figure 1. Because the high dielectric layer 12 can be thicker than the conventional silicon oxide layer while maintaining the same capacitance, the nitrogen profile can be easily adjusted. Surface nitriding is performed using a nitrogen plasma treatment, a heat treatment in a nitrogen atmosphere, or a heat treatment after forming a nitrogen layer on the high dielectric layer 12 f. The nitrogen thermoelectricity treatment is performed using decoupled plasma, remote plasma, or ammonia plasma. The heat treatment is a nitrogen environment heat treatment performed in an ammonia (Nh3) or nitrogen oxide (N20 or NO) environment. Next, in step 120, a nitrided silicon substrate 10 is subjected to a post-treatment. Due to trap points after nitriding treatment (trap 12209pif. doc / 008 13 200405434 sites) may increase the leakage current, so post-processing is required. Post-processing is performed by performing an annealing or oxidation process on the silicon substrate 10 on which the high-dielectric layer 12 is formed. The high-dielectric layer 12 according to the present invention has the advantages of high quality, strong interface characteristics, and high mobility. Fig. 3 is a flowchart showing another example of the post-heat treatment of the method of forming a high dielectric layer in a semiconductor device according to the present invention. More specifically, in step 100, a nitridation process is performed on the silicon substrate 10, and an oxide layer (or a chromium oxide layer) and three groups of metal oxide layers such as an aluminum oxide layer are deposited by turns to form a silicon oxide layer. A high-dielectric layer 12 formed by nano-sheets is formed on a sand substrate 10. The method and effect of the nitriding treatment are the same as those described in the second figure. Next, in step 22, annealing is performed on the silicon substrate 10 to which the nitriding treatment is applied. Annealing is performed in an inert gas, high hydrogen, a mixture of hydrogen, nitrogen and hydrogen, or a vacuum environment. Annealing is performed at a high temperature of 950-1 100 ° C. Annealing performed at high temperatures enhances the densification effect and provides a strengthening interface layer. Tempering can repair defects that may be caused by the deposition of at least two metal oxide layers. The high dielectric layer 12 according to the present invention has the advantages of high quality, strong interface characteristics, and high mobility. Fig. 4 shows a flowchart for explaining still another example of the post-heat treatment of the method of forming a high dielectric layer in a semiconductor device according to the present invention. 12209pif. doc / 008 200405434 More specifically, in step 100, a nitridation process is performed on the silicon substrate 10, and three layers of metal oxide layers such as an oxide layer (or chromium oxide layer) and an aluminum oxide layer are deposited by turns, A high-dielectric layer I2 formed by the formed one-nanometer sheet is formed on the silicon substrate 10. The method and effect of the nitriding treatment are the same as those described in FIG. 2. Next, in step 320, an oxidation process is performed on the silicon substrate 10 to which the nitriding process is applied. Oxidation treatment can not only repair defects, such as removing traps such as oxygen vacancy in the local dielectric layer 12, but also meet stoichiometry of the metal oxide layer. Oxidation treatment can be borrowed This is performed by wet or dry oxidation of the silicon substrate 10 on which the high dielectric layer 12 is formed. Wet oxidation is performed using H20, ISSG (In-Situ Steam Generation), or WVG (water vapor generation). In dry oxidation, a silicon substrate with a high dielectric layer is oxidized in a nitrogen oxide or oxygen environment. In addition, the oxidation treatment can also be performed by oxidizing a silicon substrate having a high dielectric layer using ozone, radical oxygen, or oxygen plasma. Such a high dielectric layer according to the present invention has advantages of high quality, strong interface characteristics, and high mobility. Fig. 5 shows a flowchart for explaining still another example of the post-heat treatment of the method of forming a high dielectric layer in a semiconductor device according to the present invention. More specifically, in step 100, a nitriding process is performed on the silicon substrate 10, and an oxidation layer (or a chromium oxide layer) and an aluminum oxide layer such as 12209pif are deposited by turns. doc / 008 15 200405434 has three groups of metal oxide layers, and a high-dielectric layer 12 formed from a formed one-nanometer sheet is formed on a silicon substrate 10. The method and effect of nitriding are the same as those described in Figure 2. Next, in step 320, an oxidation treatment is performed on the sand substrate 10 on which the nitriding treatment is applied. The method and effect of the oxidation treatment are the same as those described in the fourth figure. The oxidation treatment is performed at a low temperature of 700 to 900 degrees Celsius. Next, a silicon substrate subjected to a nitriding treatment and an oxidation treatment is subjected to annealing. The method and effect of annealing are the same as those described in Figure 3. Annealing is performed at a high temperature of 950-1100 degrees Celsius. Such a high dielectric layer according to the present invention has advantages of high quality, strong interface characteristics, and high mobility. Regarding the post-heat treatment method, the electrical characteristics of a semiconductor element will be described below. Among them, the high-dielectric layer formed by nano-sheets formed by alternately depositing an oxidation coating layer (or a chromium oxide layer) and an aluminum oxide layer (or a yttrium oxide layer) is formed on a semiconductor element. In the example of manufacturing RTA, firstly, using atomic layer deposition, a high dielectric layer 12 having a thickness of 50 angstroms is formed on a silicon substrate 10, and then in a nitrogen atmosphere at a temperature of 950 degrees Celsius, the The high dielectric layer 12 is subjected to a rapid thermal annealing process for 30 seconds. In the example of manufacturing an RTNOA, a high dielectric layer 12 having a thickness of 50 angstroms (for a nano-sheet) is first formed on a silicon substrate 10 Then, in the environment of ammonia, nitriding treatment is performed on the high dielectric layer 12 at a temperature of 750 degrees Celsius for 60 seconds. Next, in an oxygen environment, the temperature of 850 degrees Celsius is applied to Takasuke. The electric layer 12 is subjected to an oxidation treatment for 30 seconds, and in a nitrogen environment at a temperature of 950 degrees Celsius, to 1 2209 pif. doc / 008 200405434 The high dielectric layer 12 is subjected to an annealing process for 30 seconds to complete the entire post-heating process. Next, a polycrystalline silicon layer 14 is deposited on the high dielectric layer 12 of the RTA and RTNOA examples. In addition, after depositing the polycrystalline silicon layer 14, arsenic (As) is implanted into nMOS, boron (B) is implanted into pMOS, and an annealing process is performed at a temperature of 1000 and 1025 degrees Celsius. The present invention evaluates the electrical characteristics of high dielectric layers by using the RTNOA paradigm. However, after the nitriding process is performed, the characteristics of the high dielectric layer on which the annealing or oxidation process can be selectively performed are not significantly changed. 6A and 6B are CV curves of nMOS (n-channel metal oxide semiconductor (MOS) and pMOS (p-channel metal oxide semiconductor)) according to an RTA example of the present invention. That is, as shown in FIG. 6A, for two activation temperatures, the CV curves in nMOS do not differ greatly from each other. However, as shown in FIG. 6B, in pMOS, the The RTA example annealed at 1000 ° C shows a normal CV curve, while the RTA example annealed at 1025 ° C shows an abnormal CV curve. The abnormal CV curve of pMOS is due to the relationship between the degradation of the interface characteristics caused by boron infiltration. The figure shows the correlation between the leakage current and the equivalent oxide thickness (EOT) of the RTNOA example and the RTA example according to the present invention, where the x-axis represents the equivalent oxide thickness (EOT) and y -The axis represents at 1. 5 volt leakage current. More specifically, Figure 7 shows the RTNOA and RTA examples at 1. 5 Volts 12209pif. doc / 008 17 200405434 The correlation between the leakage current of special nMOS accumulation region and EOT 値. For the same leakage current, compared to the NSIO example in which a silicon oxide layer is used as the gate insulation layer and the subsequent nitriding treatment is performed, the RTA and RTNOA examples have smaller EOT 値, And its thickness is 4-5 Angstroms less. (In addition, for the same leakage current, the RTA example has a smaller EOT 値 compared to the RTNOA example. However, because the PMOS characteristics do not appear to be less in thickness due to boron infiltration. 40 angstroms (for the RTA paradigm, so in terms of scalability, it is not certain whether the characteristics of the RTA paradigm are better than the RTNOA paradigm. Figures 8A and 8B show the RTA paradigm according to the present invention. C_V curves of nMOS and pMOS. Figures 9A and 9B are CV curves of nMOS and pMOS according to the RTNOA example of the present invention. Among them, Figures 8A, 8B, 9A, and 9B The y-axis in the figure represents normalized capacitances. More specifically, as shown in Figures 8A and 8B, the width between the CV hysteresis curves of the RTA example is large, and Is 0. 37 volts or 0. 39 volts. On the other hand, as shown in FIGS. 9A and 9B, the width between the C-V hysteresis curves of the RTNOA example is less than 0. 1 volt. This phenomenon illustrates the fact that the interface characteristics of the RTNOA paradigm are superior to those of the RTA paradigm. Figures 10A and 10B are graphs showing Gm (transconductance) related to the nMOS and pMOS electric fields of the RTA and RTNOA examples according to the present invention. In Figures 10A and 10B, CET stands for capacitance measurement Equivalent oxidation thickness, Vg represents the gate voltage, and Vth generation 12209pif. doc / 008 200405434 indicates the threshold voltage. The width W and length L of pMOS and nMOS are 10 and 0.1 respectively. In order to observe the mobility characteristics, Gm (transconductance) must be estimated. Gm is based on the NSIO example using the oxide layer to which the nitriding treatment is applied as the dielectric layer for comparison. The nitrided oxide layer serves as the dielectric layer of the NSIO example. The Gm in nMOS in the RTA example is only 45%, and the Gm in pMOS in the RTA example is only 51% compared to the NSIO example. Therefore, the mobility It will be greatly reduced. On the other hand, compared to the NSIO example, Gm in nMOS in the RTNOA example is only 78%, and Gm in pMOS in the RTNOA example is only 79% compared to the NSIO example. Compared with the RTA example, the mobility of the RTNOA example is not significantly reduced. Figures 11A and 11B show the on-state of nMOS and pMOS in the RTA example and the RTNOA example according to the present invention. The relationship between the current Ion and the off-state current Ioff, wherein the drain voltage is set to 1. 2 Volts. More specifically, as shown in FIG. 11A and FIG. 11B, compared to the NSIO example, the on-state current (or driving current) of the nMOS and pMOS of the RTA example are the off-state currents, that is, 10 52% and 50% of ηΑ. On the other hand, compared to the NSI example, the on-state currents of the nMOS and pMOS of the RTNOA example are the off-state currents, which are 81% and 80% of 1〇ηΑ, respectively. The following table 1 briefly shows the electrical characteristics of the RTA and RTNOA examples 12209pif. doc / 008 19 200405434. [Table 1] \ Condition Result \ CET (Cumulative) CET (Reverse Phase) Gate Consumption Hysteresis Curve Width vs. Normalized Example Gm Ratio vs. Normalized Example Open Current Ratio RTA nMOS 22. 7 26. 8 83. 9% 0. 37 45% 52% Example pMOS 20. 9 30. 6 68. 3% 0. 39 51% 50% RTNO nMOS 24. 0 28. 1 85. 4% > 0. 1 78% 81% A example pMOS 23. 3 32. 5 71. 7% > 0. 1 79% 80% As shown in Table 1, in the RTA example, the equivalent oxide thicknesses CET of the capacitance measurements of the nMOS and pMOS in the accumulation region are 22. 7 Angstroms (present and 20. 9 angstroms (for, and in the reverse phase, respectively, 26. 8 Angstroms (for with 30. 6 angstroms (for. On the other hand, in the RTNOA example, the equivalent oxide thicknesses CET of the capacitance measurements of nMOS and pMOS in the accumulation region are 24. 0 angstroms (for and 23 · 3 angstroms (for now, in the reverse phase region, they are 28. 1 Angstrom (present and 32. 5 angstroms (for. Therefore, the RTNOA example has a larger CET 値. However, the RTNOA example has a considerable limit in terms of leakage current, and its oxidation amount can be adjusted by heat treatment after use. For gate consumption, RTA's nMOS And pMOS are 84% and 68% respectively. However, RTNOA's nMOS and pMOS are 85% and 72% respectively. This fact proves that the RTNOA example is better. Finally, compared to the RTA example, the RTNOA example performs better. Gate consumption characteristics, smaller width hysteresis curve, and better mobility. Although RTNOA has the disadvantages of larger CET 値, but in terms of leakage current, 1 2209 pif. doc / 008 20 200405434 still has considerable limits, so its CET 値 can be reduced by optimizing the oxidation temperature. Second Embodiment FIG. 12 is a schematic view for explaining a method of forming a high dielectric layer in a semiconductor device according to a second embodiment of the present invention. Specifically, in Figures 1 and 12, the same reference numerals represent similar elements. In addition, in addition to the ozone interface oxide layer 11 being formed before the high dielectric layer 12 is formed, in terms of its influence and structure, according to a second embodiment of the present invention, a method for forming a high dielectric layer in a semiconductor device Is similar to the first embodiment. More specifically, the ozone interface oxide layer 11 is formed on a silicon substrate 10 using ozone. The thickness of the ozone interface oxide layer 11 is 8 angstroms, which is formed at a temperature of 320-450 degrees Celsius. The ozone interface oxide layer U is an atomic layer deposition device generally used for forming high dielectric layers. The silicon substrate 10 is formed by washing. In addition, a separate chemical evaporation deposition device can also be used to form the ozone interface oxide layer 11. Next, the high dielectric layer 12 will be formed at the ozone interface in the manner shown in FIG. On the oxide layer 11. Next, the silicon substrate 10 on which the high-dielectric layer 12 is formed is subjected to post-heat treatment in the same manner as shown in Figs. 2 to 5. The polycrystalline silicon layer 14 is formed on the high-dielectric layer 12. Arsenic (As) is implanted into the nMOS on the silicon substrate 10 on which the polycrystalline silicon layer 14 is formed, and boron (B) is implanted into the pMOS on the silicon substrate 10. Next, the annealing process used to start, Will be applied to the silicon substrate 10, so that the silicon substrate 10 becomes a low electrode, and the polycrystalline silicon layer 14 becomes a high electrode. 12209pif. doc / 008 200405434 The following is an evaluation of the electrical characteristics of a semiconductor element according to a second embodiment of the present invention to which a shaped ozone interface oxide layer? is added. The following RTNOA example is made in the same way as shown in Figure 1. The ORTNOA example is manufactured in the same manner as the RTNOA example except that the ozone interface oxide layer 11 is formed on the silicon substrate 10 as described in the second embodiment. The NSIO example uses a nitrided oxide layer as the dielectric layer. Polycrystalline silicon layers are deposited on the high dielectric layers of the RTNOA example, the ORTNOA example, and the NSIO example. After depositing a polysilicon layer, arsenic (As) is implanted into nMOS, and boron (B) is implanted into pMOS. Next, annealing is performed at a temperature of 1000 to 1025 degrees Celsius to start. More specifically, the second embodiment of the present invention uses the ORTNOA paradigm 'to evaluate the electrical characteristics of a high dielectric layer. However, on the silicon substrate on which the ozone interface oxide layer and the high dielectric layer are formed, the characteristics of the high dielectric layer, which is selectively annealed or oxidized after the nitriding process is performed, have not changed significantly. Figures UA and 13B are leakage current graphs showing an ORTNOA example and an RTNOA example according to the present invention. _ Specifically, "Fig. 13A is a graph showing the relationship between the current density and the gate voltage" and Fig. 13B is a graph showing the cumulative distribution of the current density when the gate voltage is 15 volts. In Fig. 13A, for the center of the X axis of 0 volts, the left side is related to pMOS and the right side is related to nMOS. In Fig. 13B, 'for the center 1 of the X axis (Γ8 volts, the left is related to pMOS' and the right is related to nMOS. The gate width of pMOS and nMOS is 1 2209 pif. doc / 008 22 200405434 degrees and length, respectively 50 μm. From Figures 13A and 13B, it can be seen that the leakage current of the ORTNOA example is significantly smaller than that of the RTN0A example or the NSI0 threshold. In addition, the equivalent oxide layer thicknesses of the 0RTN0A example and the RTNOA example are 19.9 angstroms (for and 19.7 angstroms for each). Therefore, the thickness of the equivalent oxide layer need not be increased. 'The leakage current of the ORTNOA example can be reduced. FIG. 14 shows a schematic diagram for explaining the negative bias temperature instability (NBTI) of the ORTNOA example and the RTNOA example according to the present invention. More specifically, once the voltage and After the temperature pressure is applied to the semiconductor element, the threshold voltage Vt of the transistor can be found to move. Generally, when the threshold voltage Vt shifts more than 50mV, the transistor life is considered to have ended. In Figure 14, the X axis Represents the gate voltage, and the y-axis represents the lifetime of the transistor. In the ORTNOA example, -2. A 32-volt gate voltage guarantees a 10-year life. In the RTNOA example, -1. A 53-volt gate voltage guarantees a 10-year life. When compared to the RTNOA paradigm, the ORTNOA paradigm has approximately 0. The advantage of 8 volts, so its NBTI can be reduced. 15A and 15B are diagrams showing the C-V characteristics and Gm (transconductance chirp) characteristics of the ORTNOA example and the RTNOA example according to the present invention. More specifically, as shown in Figures 15A and 15B, in terms of C-V characteristics and Gmmax (Gmmax), no significant difference was found between the ORTNOA example and the RTNOA example. In summary, when compared with the RTNOA example, the ORTNOA example according to the second embodiment of the present invention can reduce the leakage current and 12209 pif more without deteriorating the electrical characteristics. doc / 008 23 200405434 NBTI. As described above, according to a method of forming a high dielectric layer in a semiconductor device, a high dielectric layer having better mobility and interface characteristics can be obtained. In addition, by forming an ozone interface oxide layer before forming the high dielectric layer, the leakage current negative bias temperature instability (NBTI) can be reduced without increasing the thickness of the equivalent oxidation layer. The high dielectric layer according to the present invention can also be used as a capacitor insulating layer for a semiconductor element, an insulating layer between a floating gate and a control gate of a volatile device, and a gate insulating layer for a semiconductor element. Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and retouches without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall be determined by the scope of the attached patent application. Brief Description of the Drawings Fig. 1 is a diagram showing a method for forming a high dielectric layer in a semiconductor device according to a first embodiment of the present invention. Fig. 2 is a flowchart showing an example of a post-heat treatment of a method of forming a high dielectric layer in a semiconductor element according to the present invention. Fig. 3 shows a flowchart for explaining another example of the post-heat treatment of the method of forming a high dielectric layer in a semiconductor element according to the present invention. Figure 4 shows a flow chart for explaining another method for forming a high dielectric layer in a semiconductor element according to the present invention, and another post-heat treatment 12209 pif. doc / 008 24 200405434 example. Fig. 5 shows a flowchart for explaining still another example of the post-heat treatment of the method of forming a high dielectric layer in a semiconductor element according to the present invention. 6A and 6B are CV curves of nMOS (n-channel metal oxide semiconductor (hereinafter referred to as MOS)) and pM0S (p-channel metal oxide semiconductor) according to an RTA example of the present invention. FIG. 7 Figures 8A and 8B show the relationship between the leakage current and the equivalent oxide thickness (EOT) of the RTN0A example and the RTA example according to the present invention. CV plots with pMOS. Figures 9A and 9B show CV plots of nMOS and pMOS according to the RTN0A example of the present invention. Figures 10A and 10B show RTA examples and RTN0A examples with the present invention. Figures of Gm (transconductance) related to the electric field of PMOS. The figures 11A and 11B are shown in the RTA example rtn〇A example nMOS and pMOS The relationship between the on-state current Ion and the off-state current Ioff is shown in Fig. 12. Fig. 12 shows a semiconductor device according to a second embodiment of the present invention. Forming one A schematic view of the method of the dielectric layer. FIGS. 13A, 13B and FIG. 25 12209pif a display system according to the present invention. doc / 008 200405434 Leakage current diagrams for the ORTNOA example and the RTNOA example. Figure 14 is a schematic diagram illustrating the negative bias temperature instability (NBTI) of the ORTnoa example and the RTNOA example according to the present invention. 15A and 15B are diagrams showing the C-V characteristics and Gm (transconductance chirp) characteristics of the ORTNOA example and the RTNOA example according to the present invention. Description of the graphical symbols: z 10: silicon substrate 12: high dielectric layer 14: polycrystalline silicon layer 16: nitrogen profile 100, 120, 220, 320, 420, 440.Flow step 12209 pif. doc / 008 26