SU1735852A1 - Parity signal predictor at binary code shifting - Google Patents

Abstract

The invention relates to computing and can be used in parity-shifting information shear systems. The purpose of the invention is to increase the speed of the device. The device contains a group of 1 blocks of elements And, a group of 2 nodes forming a signal in parity and a group of 3 nodes of convolution modulo two. The information word arrives at the information input of the device. With the help of signals at input 7, a device mask block in the blocks of elements of And 1 occurs the allocation of bits advanced byte byte. The parity signal shaping nodes of group 2 form parity signals of the discharge bits at output 15 and the remaining bits at output 1. Modulo convolution nodes two groups 3 Generate new check bits at the device output 6, k Il. a

Description

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The invention relates to computing technology and can be used in information shift systems with parity.

The aim of the invention is to improve the speed of the device.

Figure 1 shows the functional diagram of the device for case n 4 (n is the number of blocks of elements I), figure 2 shows the functional diagram of the group parity forming unit} in FIG. 3 is the functional diagram of the modulo convolution generator two parity signaling nodes groups; in FIG. - a functional diagram of a convolution node modulo two groups.

The device contains a group of 1 blocks of elements AND, a group of 2 nodes for generating parity signals, a group of modules of convolution modulo two, information input 4 and input 5 of the control bits of the device, output b of the control bits of the device, input 7 specifying the mask code and input 8 specifying the direction the device shift, the inputs 9 and 10 of the parity attribute of the device, the outputs 11 and 12 of the parity attribute of the device, the input 13 of the information bits of the node for generating parity signals of group 2, the parity output 14 of the remaining bits and the output 15 of the parity attribute of the node f arranging parity signals of group 2 (Fig. 1),

The node for generating parity signals of group 2 contains modulo-two drivers 16-21. The convolution modifier 16 modulo two contains AND-NOT elements 22-25 and AND 26 with direct and inverse outputs. The convolution node modulo two groups 3 contains the elements AND NOT

 27-31.

The device is designed to shift by an amount not greater than K - 1, where K is the number of data bits connected to the block of AND elements of group 1.

The device works as follows.

The inputs 4 and 5 of the device receive, respectively, an information word consisting of four bytes and check bits of information bytes.

Since the management of information on the amount of shift entering the input

1735852 5

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Specifying the device mask code, blocks of elements And group J allocate information bits in each byte to

Some are pushed beyond byte limits. The blocks of AND elements of group 1 can be built, for example, in the form of eight AND elements, to the first inputs of which informational rows of the SERIES are received, and to the second - code bits from input 7 of the device mask code. I

The allocated information bits arrive at the inputs 13 of the information bits of the corresponding nodes of forming parity signals of group 2, which collapse these bits modulo two and form a parity signal of the nominated bits at the output 15 of the parity feature of the node. At the outputs Ik of nodes of group 2, the parity signals of the remaining bits are formed, which are formed by

5 add modulo two push-up information bits and a check bit byte.

The inputs of each i-ro convolution node modulo two groups 3 receive a signal from the output AND of the 1st node of group 2 and signals from the outputs 15 (i-l) -ro and (i + 1) -ro of nodes of group 2 (). Depending on the signal at the input 8, specifying the direction of the device shift, the nodes of group 3 form the predicted byte parity signals by adding modulo two signals from the output 14 of the corresponding node of group 2 to the output 15 of one of the neighboring nodes of group 2.

0 The resulting signals are output 6 of the device.

Using inputs 9 and 10 and outputs 11 and 12 of the device, it is possible to combine several

S devices to increase the size of the word being monitored, f

Unused inputs 9 and 10

devices are connected to the zero potential bus of the device.

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Claims (1)

Formula of gain and A device for predicting parity signals during shifts of binary codes containing a group of blocks of elements AND, the first inputs of blocks of elements AND of a group being connected to the corresponding bits of information51 The device’s input, the second inputs of the elements of the AND group are connected to the input of the device mask code, characterized in that, in order to increase the device’s speed, a group of parity signaling nodes and a group of convolution nodes are entered into it; the block of elements AND of the group is connected to the input of the information bits of the 1st node of forming the parity of the group (lЈiЈn), where n is the number of blocks of elements of the AND group, the input of the check bit of the 1st node of forming the parity of the group The i-th bit of the device control bits input, the parity output of the remaining bits of the 1st parity signaling node is connected to the first information input of the 1st convolution unit modulo two groups, the parity attribute output of each j-ro node of the group parity signal generation connected to the second info358526 By the input (j-HJ-ro of the convolution node, modulo two groups (lfeign-1), the output of the parity attribute of each Who node of the group parity signal generation is connected to the third information input (K-1) of the convolution node modulo two groups ( ), the parity feature of the first and JQ of the last nodes of forming the group parity signals are connected respectively to the first and second outputs of the parity attribute of the device, the second information input of the first U and the third information input of the last convolution nodes modulo two groups are connected respectively to the first and second inputs of the device parity, respectively, input There are 20 groups of modulation of the convolution nodes; two groups are connected to the. The arrays, the outputs of the nodes of the convolution according to the MO-L two, form two groups that form the output of the controller. Phage. 2 Figz