SU1686449A2 - Addressing device - Google Patents

Abstract

The invention relates to automation and computer technology and can be used as a hardware module for connecting mathematical and physical addresses. The purpose of the invention is to expand the functionality of the device by giving it the ability to self-monitor. The device contains switches 1 -3 register 4 logical address decoder 5 logical address first group elements OR 6 7, elements 8 9 switching, encoder 11 physical address, register 13 physical address, the second group of elements OR 15, 16 cipherto p 17 logical addresses, control units 20 and 21, output element OR 22 The device can be used not only as a device for addressing, but also as a device for associating mathematical and physical addresses in fault-tolerant computing systems 1 c f files, 2 or

Description

The invention relates to automation and computer technology and can be used as a module for associating the logical and physical addresses of any functionally complete blocks (processors, memory blocks, etc.)

The aim of the invention is to expand the functionality of the device by giving it the ability to self-control.

Fig. 1 shows the functional diagram of the device (for three memory blocks), Fig. 2 shows the control unit diagram.

The device contains a group of switches 1 -3 register 4 logical address decoder 5 logical address first group of elements OR 6, 7 elements 8 and 9 switching of the first and second groups, input 10 logical address encoder 11 physical address output 12 physical address register 13 and decoder 14 physical

addresses, the second group of elements OR 15 and 16, the encoder 17 of the logical address, output 18 of the logical address, input 19 of the physical address, blocks 20 and 21 of the control, output element OR 22, output 23 of the symptom, input 24 Control 1, input 25 Control 2 Each control unit (see FIG. 2) contains a multiplexer 26, a demultiplexer 27, a comparison circuit 28 and an OR element 29, the first 30 and second 31 information inputs, the first 32 and second 33 information outputs, the start operation input 34, the control input 35. output 36 sign of failure

The device works as follows

Immediately after the power is supplied, the switching session in the matrix begins (elements 6-9 15, 16) in accordance with the signals of the switches 1-3. The high level signal (WU) at the output of the switches 1 3 corresponds to

About 00

About 4 Yu

YU

The unit is on / healthy, the signal is low / WELL / - The unit is turned off / faulty. After the transients in the matrix switch are completed, the device is ready for operation in the mode of connecting logical and physical addresses (L A and FA). In this case, the LA-FA and FA-LA transformations occur completely independently of each other: the LA, the incoming input 10, is converted to the FA at output 12, and the FA from input 19 - to LA And at the output 18. At those times when the central processor does not use the associated address (after its capture), the device can be translated into one of two control modes. These modes differ from each other only in what address is the control - LA at input 10 (Control 1) or FA at input 19 (Control 2).

Modes are defined as follows.

Consider the Monitoring mode 1. In this case, the WU signal at input 24 through the start input of the first BC 20 permits operation of the comparison circuit 28 of the BC 20. The same WOO signal at input 24 through the control input of the second BC 21, first, enters the control A multiplexer 26 makes it possible for the FA to pass from the output of the FA encoder 11 to the first information output of the BC 21 and, secondly, to the control input of the demultiplexer 27, sends a signal from its input to the first output. (The signal WU / WELL / at the control input of multiplexer 26 means connecting its output with its second (first) input; WU / WELL / signal at the controlling input of demultiplexer 27 means connecting its input with its first (second) output). Since in Control 1 mode, the signal at input 25 has a CU, the comparison circuit 28 of the second BC 21 does not work. Thus, in the Control 1 mode, the second BC allows the input of the register 13 of the FA, the physical address coming from the output of the encoder 11, and at the same time ensures that output 12 and input 19 are disconnected from the rest of the circuit. It compares the logical address from input 10 to the logical address taken from the output of the encoder 17 This is the case of the control LA LA conversion and the inverse LA conversion with the comparison of the original and the received LA. Similarly, in the Control 2 mode, the first BC provides the input to the register 4 of the logical

addresses coming from the output of the encoder 17, and, at the same time, disconnecting output 18 and input 10 from the rest of the circuit. In the second BC, a comparison is made between the FA arriving from input 19, and the FA arriving

from the output of the encoder 11. Thus, the control transforms of the FA of the aircraft and the inverse transformation of the LA of the FA (with the comparison of the initial and the obtained FA) occur. Fault signal taken in mode

Control 1 from the output of the BC 20, and in the Control 2 mode from the output of the BC 21, goes through the OR 22 element to the device output 23 and is used as a flag — a sign of a device malfunction for addressing.

Claims (2)

1. Device for addressing auth. EV No. 1573458, characterized in that, in order to expand functionality by giving it the ability to self-control, two control blocks and an OR output element are introduced into it, the inputs of the logical and physical addresses of the device are connected to the first information inputs of the first and second control blocks, respectively , the first information outputs of which are connected to the information inputs of the registers of the logical and physical addresses, respectively, and the second information outputs are respectively the outputs of the logical and physical addresses of the device, the second information inputs of the control units are connected respectively to the outputs of the encoders of the logical and physical addresses, the start input of the first control unit and the control input of the second control unit are combined and are the input Control 1 of the device, the control input of the first control unit and the start input the operation of the second control unit is connected and is the input of Control 2 of the device, the outputs of the symptom of the control units are connected to the inputs of the output element OR, the output of which is the output of the symptom of the device. 2. The device according to claim 1, which means that the control unit contains a multiplexer, a demultiplexer, a comparison circuit, and an element. OR, the block start input is connected to the first input of the OR element and to the control input of the comparison circuit, the control input of the block is connected to the second input of the OR element and to the control input of the multiplexer, the output of which is the first information output of the block, the first information input which is connected to the first information input of the multiplexer and the first input of the comparison circuit, the output of which is the output of the sign of a malfunction of the block, the second information input of which is connected to the second information input th data input of the multiplexer and demultiplexer, a first output connected to the second input of the comparison circuit, a control input - with the output of the OR gate, and the second output is a second data output unit. 33