SU1649507A1 - Programmable control unit - Google Patents

Abstract

The invention relates to automation and computing technology and can be used in distributed fault-tolerant control systems for automated process control systems that use software control principle and allow extensions with an increase in the number of functions performed. The purpose of the invention is to increase the speed of the module. The goal is achieved by the fact that in a known device containing a microinstructions memory block, address registers and microoperations, address and logic conditions multiplexers, a sign decoder, a trigger trigger, the first and second elements OR, the first - third elements And, the first and second main elements , additionally introduced are registers of comparison and logical conditions, a unit of comparison, a third element OR, a fourth and fifth elements AND, a third main element, the introduction of new elements makes it possible to provide Ranma operation of comparing the measurement code with which the identification is carried out address code, setting control module, increase system performance, implemented in modules, by parallel operation of modules each koto-. The system has its own algorithm of functioning, increase the fault tolerance of the system due to the redistribution of the functions of the failed module between the healthy modules of the system. 4 ill., 1 tabl, 0 & -U has eaten

Description

The invention relates to the field of automation and computer technology and can be used in distributed fault-tolerant control systems for automated process control systems that use the software control principle and can be expanded by increasing the number of functions to be performed.

The purpose of the invention is to increase the speed of the module by reducing.

program execution time in case of failure of one of the control modules — and replacing it with a backup one.

FIG. Figure 1 shows the functional diagram of the programmable control module (PIP), in Srig. 2 - Functional diagram of the system implemented on the modules; in fig. 3 - timing diagrams of the two modules of the distributed system; in fig. 4 is a block diagram of the module operation algorithm.

The module contains a block of 1 memory of micro-commands with the fields of feature 1.1, micro-op code (MO) 1.2, code of logical conditions (LU) 1.3 and addresses 1.4, address registers 2, micro-operations 3, comparison 4 and logical conditions 5, multiplexers of address 6 and logical conditions 7, the decoder 8 of the sign, block 9 comparison, trigger 10 start, the first 11, the second 12 and the third 13 elements OR, the first 14, the second 15, the third 16, the fourth 17 and the fifth 18 And elements, as well as the first 19 , the second 20 and the third 21 main elements and has information input 22 of the main element 21, output 23 magi1

elemental element 20, the input-output 24 2Q start at least one module of the system.

bus mode, the first 25 and second 26 synchronization inputs, address bus input / output 27, data bus input / output 28, micro-operations 29 outputs, status output 30, request output 31, start-up input 32, input 33 of logic conditions, The input 34 of the response to the request and the input 35 of the operation code.

The system is formed by a generator of 36 clock pulses and a determinant of 37 at-ed priority.

A programmable control module within a distributed system operates as follows.

In the initial state, the generator 36, clock pulses, at its outputs, generates a series of clock pulses that are shifted relative to each other, all modules are in the initial state of waiting. All 0 memory elements, except register 4 comparisons, are set to the zero state. The compare register 4 is set to one, i.e. in him

Each module can operate in the following modes: standby code of the next MP} control mode; comparison code change mode; control transfer mode; logical conditions query mode; AKU standby mode.

The initial state of the module is equivalent to the state of the module in ACU standby mode.

The transition of the module to the expectation mode of the MP code from the initial state is effected by the Start signal coming from input 32 through the OR 11 element to the installation trigger trigger 10 input. The signal from the trigger start output opens elements 14 and 15, allowing the passage of clock pulses from the generator outputs 36 clock pulses to the corresponding module inputs.

If at the time of occurrence at the sync input of the address register 2 of the trailing edge module of the first clock pulse (fc |) from the output of the AND 14 element at the output 35 of the operation code, it has not yet appeared,

recorded single code. From block 1; pa; d5 in register 2 of address changes to zero

$

Rez, which passes to the information inputs of the register 2 addresses the operation code from the input 35 of the module. The unit code from the output of the comparison register 4 goes to the corresponding information inputs of the comparison block 9, the other inputs of which receive the zero code from the address bus 27. Thus, the comparison block 9 generates a zero signal at the output that prohibits the passage through elements 12 and 12 17 signals of the mode of the bus 24 mode, Setting the comparison register 4 to one state causes the module to perceive the zero code in the address bus 27 as foreign. In this state, the control system is before the arrival of the signal. Start at input 32

Each module can operate in the following modes: standby code of the next MP} control mode; comparison code change mode; control transfer mode; logical conditions query mode; AKU standby mode.

The initial state of the module is equivalent to the state of the module in ACU standby mode.

The transition of the module to the standby MP code from the initial state is effected by the Start signal, coming from input 32 through the OR 11 element to the installation trigger trigger 10. The signal from the trigger output Yu start opens elements And 14 and 15, allowing the passage of clock pulses from the generator outputs 36 clock pulses through the corresponding inputs of the module.

If at the time of the occurrence at the synchronous input of the address register 2 of the trailing edge module of the first clock pulse (fc |) from the output of the AND 14 element at the output 35 of the operation code has not yet appeared,

A set of microinstructions reads the contents of the cell at the zero address.

In the table, this is a microcommand (MC) of type A. In its field 1.1, a zero code is written, which is decoded by the decoder of feature 8 as a waiting signal for the code of the next MP. This single signal is fed to output 30 of the jHHH MODULE.

In addition, the waiting signal of the code of the regular MP from the first output of the decoder of the sign 8 is fed to the second control input of the multiplexer 6 address and from block 1 of the micro-instruction memory the A type MK is read again. Since the 1.2 code is written in its field 1.2 a clock pulse from the output of the second element AND 15. The register 3 of the micro-operations does not change its state.

After the code MP appears at the input 35 of the module, this code is written to the address register 2 via the multiplexer of address 6 and the module goes into control mode.

But the trailing edge of the clock pulse r from the output of the element I 15 in pe516495076

Micro-operation micromaster 3 is written to the mixes zero codes. Signal KFnets is the operation code of the first MK microbots on the falling edge of the next L | programs. In addition, in the control clock mode, 52 is recorded in

Register 3 micro-operations. Then, from the corresponding output 3.1 of register 3 of the micro-operations, a single signal of the micro-operation. The end of the work embraces the trigger trigger 10 and the register 2 addresses. From the JQ microcommand memory block, the type C MK is read.

If it is necessary to change the comparison code recorded in the comparison register 4, the module will go from the control mode to the change code of the comparison code. On the trailing edge of the next pulse Ј, from the output of the element 14 in the address register 2, the address of the C-type C is recorded. 1 memory microinstructions.

On the falling edge of the next clock pulse Јg from the output of the AND 15 element, a new comparison code is written to the comparison register 4. In the mode of changing the comparison code, the register 3 micro 30 operations is set to the zero state by a signal from the high bit of the output field 1.1.

Any new code other than zero can be written to the comparison register.

If it is necessary to transfer information to another module of the system, the module in question is transferred to the transfer control mode.

On the falling edge of the next cycle, the seventh output of the decoder 8 of the feature is suspended, and a single signal at the first output of the decoder 8 of the feature disappears.

On the falling edge of the next clock pulse from the output of the AND 14 element into the address register 2 from the outputs of the address multiplexer 6, the address of the next MC is recorded. This address is fed to the third information input of the multiplexer of address 6 from the high-order bits of outputs 1.4 of the field of the address of the microcommand memory block t (the unmodifiable part) and the multiplexer output of the logical conditions 7 (the modified part). In linear MK, the value of the low order bit of the address of the next MK is determined by the value of the low bit of the address field 1.4. In the field 1.3 of logical conditions in linear MK recorded zero code. According to this code, the multiplexer 25 7 logical conditions passes the value of the signal from the lower bit of the field 1.4 to the output. In MK branching, in field 1.3, a logical condition code is written, the value of which is analyzed when generating the address of the next MC. According to this code, the multiplexer 7 of logical conditions passes from the input 33 logic conditions to its output the values of the desired logical condition. Thus, in the control mode, the least significant bit of the next MC address is completely determined by the value of the signal at the output of the multiplexer 7 logical

Loviy. According to the recorded in the register 2 ad-4d Vogo pulse Ј; from the output of the address of the address from block 1 of memory of micro and 20 (Fig. 3), address MK of type D is written to address register 2. This MK of the procommands is read the next MK linear or branching.

From the control mode the module can switch to any other mode.

When switching to the standby mode of the code of the next MP in pbl 1.3 and 1.4 of the format of the last MC, zero codes are executed and in the next clock the zero MC of type A is read, i.e. the module enters the idle state.

When switching to ACU standby mode or when the module finishes, field 1.1 in the last MC format records the code by which the decoder of feature 8 generates at the sixth output a micro-operation signal of the end of operation. In fields 1.3 and 1.4 of this MC (type G MC), the system is ready to transfer from the Nth module to the Lth module (group of modules) of the ACU.

At the fourth output of the decoder of feature 8, a data bus status, address and mode request signal is generated. This signal is sent to the corresponding

50 the current Y-and input of the priority determinant 37. If in this system operation cycle the request signals from other modules did not arrive at the priority determinant 37, then it forms

55 n-m output signal to enable use of system-wide tires in the next system cycle. Otherwise, such a signal is formed at another output of the determiner 37 prioritize

35

believes the system is ready to transmit from the Nth module to the Lth module (module group) of the ACU.

At the fourth output of the decoder of feature 8, a data bus status, address and mode request signal is generated. This signal is sent to the corresponding

input S and the input of the priority determiner 37. If in this system operation cycle the request from other modules did not arrive at the priority determinant 37, then it forms

The nth output is the enable signal of the use of system-wide tires in the next system cycle. Otherwise, such a signal is formed at the other output of the determiner 37 priorit

com, which is connected to the input 34 of the response to the request of another higher priority module of the system. When the response signal to the request at the input of the 34th module is zero, the element And 16 forms a single signal, which is fed to the control input of the multiplexer 7 logical conditions. By this signal, the multiplexer 7 of logical conditions passes a zero signal from its low-order output to field 1.4, pulse Ј, address MK of type D is written to address register 2; Micro-register of Micro-operation register 3 is zeroed by the signal from the first exit floor 1.1. As soon as the module 34 I-go module enters

At the inverse control input of the multiplexer logic conditions 7, the single signal disappears and at its output appears the value of the logic condition from the output 30 of the state of the L-ro module.

If the signal of this logical field is zero, i.e. If the L-th module is not ready to receive ACU, then in the next cycle of operation, the type-D MK is read out again from the N-ro module for the indicated reasons.

As soon as a single signal appears at the input of the 34th module, the logical condition from the output 30 of the L-ro module at input 34 of the N-ro module becomes one (the Lth module at

is in the waiting state of the ACU), the value of the lower bit of the next MC in the Nth module will become one. By impulse с, from the output of element 14 into the address register of the n-th module, the address of the MK of type E is written. and, in addition, it enters the input of the backbone element 19. At the information input of the address register 2, the next MC address is generated, the output code of the 1.3 field reads the address code of the L-ro module, and from the output 1.2, the ACU enters the data bus 28. In block 9, the comparison of each module of the system compares the address code transmitted to address bus 27 by the UM module with the comparison code, which is recorded in comparison register 4. In those modules of the system in which these codes coincided, a single unit is formed at the output of the comparison unit.

eight

ten

15

20

30 35

45

40 is a signal that permits the passage of a mode-of-operation signal from mode 24 bus through AND 17 element. This signal is sent to address 6 multiplexer, which passes AKA address 2 register input from data bus 28 to input. In addition, this signal through the OR element 11 sets in one state the trigger 10 of the start of the L-ro module. According to the next impulse Ј (, from the output of the element I 14 to the address register 2 L-ro module is written ACU, and to the register 2 addresses of the W-ro module is the address of the next MC. If the L-th module did not have a fault, then output 30 No single signal disappears. If the L-th module is faulty, then a single signal remains at the output 30 of this module. The L-th module remains in the AKU standby state.

To check the reception of ACU from block 1 of the memory of microinstructions of the N-th module, a type B branching module is read, field 1.3 of which contains a code corresponding to 25 points of output 30 of the L-ro module. If the L-th module has not left the ACC standby mode, then the N-th module refers to the emergency subroutine to eliminate the failure of the L-ro module.

If it is necessary to query the logical conditions, the L-ro module L-th module switches to the mode of requesting logical conditions. On the next clock pulse Ј, from the output of the element 14 in the address register 2, the type D MK is written. The bus check in the logic conditions request mode is similar to the control transfer mode. As soon as a single signal appears at the input of the 34th module, then by pulse Ј, from the output of the AND 14 element into the address register 2, the address of the type F MK is written.

A single signal from the fifth output of the decoder of feature 8 opens the trunk element 19, allows writing the logical conditions to the register 5, through the OR element 12 to the inverse control input of the multiplexer 7 logical conditions, the output Lro of the module J.3 is read out through the open trunk element 19 enters the bus 27 addresses. Since there is an F-type MK, the third output of the tag decoder is not excited, but the mag.

The main element 20 remains closed and a zero signal is output to the mode bus 24 from the low-bit output of the main element 19. At the same time, it is impossible to request the codes of the logical conditions of several modules. If the addresses in block 9 of the comparison of the L-ro module match, the request signal passes through the AND 16 element, which is fed to the input of the AND 18 element. This signal opens the trunk element 21 and allows

passing the code of logical conditions to jg the least significant bit of the output of the address code

bus 28 of data, which in the Nth module is written to the register 5 of the logic conditions by pulse 2. At the same time, the next micro-operation code is written from the register 1.2 to the register 3 of the micro-operations.

In this way, the interaction of the modules of the distributed system and their coordinated operation are organized.

Claims (1)

Invention Formula 20 the microinstructions memory block is with wide bits of information inputs of a logical conditions multiplexer, the course of which is connected to the younger time of the first group of information inputs of the address multiplexer, the second g of the inputs of the multiplex operation code of the address, the second group in the multiplexer addresses of the address is connected to the data bus, the third output of the tag decoder is connected to the control input of the second trunk element, with the low-order bit of the information inputs of the first trunk elec- OR OR, the output of which is connected to the full resolution enable input of the multiplier of logical conditions, the fourth move of the attribute decoder is in the course of the module request and connected to the fifth input of the third AND element, the second inverse input of which the module responds and the second element OR is connected to the second input, the fifth output of the deciphered feature is connected to the third input of the second OR element, the first input of the fifth OR element is the input of the module p 5, and the output is connected to the input A programmable control module containing a microinstructions memory block, 25 address registers and microoperations, address and logic conditions multiplexers, a tag decoder, a trigger trigger, first and second elements OR, first, second, third elements AND, first and second main lines elements, which are the outputs of the field of the sign of the microinstructor memory block are connected to the inputs of the attribute decoder, the first output of which is the output of the module state and connected to the first address input of the address multiplexer whose information outputs connected to the information inputs of the address register,  g 35 45 information outputs of which connect start triggering triggers, the output of which is with address inputs of the microinstructions memory block, the most significant bit of the field of the sign of which is connected to the reset input of the micro-operations register, whose outputs are the outputs of the micro-operations of the module, and the output End of operation is connected with trigger reset inputs,. the start and address register, the sixth output of the attribute decoder, and the micro-operations microcode operations outputs of the microcommand memory block are information inputs of the microoperation register and the backbone element, whose outputs are connected to the data bus; the microoperations memory logic output terminals are connected to the logic conditions multiplexer address inputs and higher bits of information inputs of the first main element, 50 55 connected to the first inputs of the second and first elements, the second inputs of which are respectively the second and first synchronization inputs of the module, and the outputs are connected respectively to the inputs of the register of micro-operations and address registers, characterized in that, in order to increase the speed of the module, the registers of comparison and logical conditions, the comparison block, the third element OR, the fourth and fifth elements AND, and the third main element, whose information outputs are connected to the data bus, the sixth output decoder and outputs the characteristic micro code memory unit rooperatsii microinstructions are data inputs of the comparison register, whose outputs soe950710 the higher bits of the information outputs of which are connected to the address bus, and the lower bits are connected to the mode bus, the higher digits of the outputs of the address code of the block of microcommand blocks are connected to the higher bits of the first group of information inputs of the multiplexer address, lower bit of the output of the address code the microinstruction memory block is the highest bits of the information inputs of the logical conditions multiplexer, the output of which is connected to the lower bits of the first group of information inputs of the address multiplexer, the second group of inputs of the operation code of the multiplexer address, the second group of inputs of the address multiplexer connected to the data bus, the third output of the tag decoder is connected to the control input of the second main element, with the lower-order information inputs of the first A trunk element OR whose output is connected to the inverse of the logical conditions multiplexer resolution input, the fourth output of the attribute decoder is the output of the module request and connected to the first input of the third element AND, the second inverse input of which is the input of the response to the module request, and the output connected to the second input of the second OR element, the fifth output of the attribute decoder is connected to the third input of the second OR element, the first input of the first OR element is the module start input, and the output is connected to the input Installation of trigger triggering, the output of which connected to the first inputs of the second and first elements, the second inputs of which are respectively the second and first synchronization inputs of the module, and the outputs are connected respectively to the inputs of the register of micro-operations and address registers, characterized in that, in order to increase the speed of the module, the registers of comparison and logical conditions, the comparison block, the third element OR, the fourth and fifth elements AND, and the third main element, whose information outputs are connected to the data bus, the sixth output decoder and outputs the characteristic code block memory microoperation microinstructions are data inputs of the comparison register, the outputs of which are connected with the first group of information inputs of the comparison unit, whose output is connected to the first inputs of the fourth and fifth AND gates, the second vho- ,. The ports of which are connected to the mode bus, and the outputs are connected respectively to the second address input of the address multiplexer, the second input of the first OR element, and the control input of the third JQ trunk element, the group of logic condition inputs and the lower order bits of the microinstruction memory address code outputs the third main element, the output of the BTO-JJ of the third element And is connected to the inputs of the record of the comparison register and the register of logical conditions, the outputs of which are connected to the lower bits of the information inputs logical logic Q checks AKU transmissions LU query end of work 0 ... 0 Address MK type D + 1 Address MK type D + 1 conditions, the information inputs of the logical conditions register are connected to the data bus, the second output of the attribute decoder is connected to the comparison register resolution input, the third output of the attribute decoder is connected to the first input of the third OR element, the output of which is connected to the control input of the first main element, the fifth output of the decoder the sign is connected to the second input of the third OR element and to the resolution input of the register of logical conditions, the second group of information inputs of the comparison unit is connected to the bus ad ENA, address bus, and data mode are respective inputs-outputs module. 0 ... 0 0 ... 0 0 ... 0 0 ... 0 Code L-ro Address MK module type E or f Code module and 0 ... 0 0. ..О V 29 Fig, 1 Fie.2 G / h MP ozhayet AKU, counting / hp / iff mt / na С (Start L AM is expected and transmission seams are free.