SU1667090A1 - Device for interfacing computer with peripheral devices - Google Patents

Abstract

The invention relates to automation and computer technology and is intended to transmit information in automated control systems for slowly running processes. The aim of the invention is to reduce hardware costs. The device comprises a synchronization unit, a computer communication unit, a memory management unit, a memory unit, an address generation unit, an address switching unit, an address switching unit, an I / O unit. 4 hp f-ly, 8 ill., 1 tab.

Description

The invention relates to automation and computer technology and is intended to transmit information in automated control systems for slowly running processes.

The purpose of the invention is to reduce hardware costs.

Figure 1 presents the block diagram of the device; figure 2 - block synchronization; FIG. 3 shows a computer communication unit; 4 shows a memory control unit; 5 shows a memory block; 6 shows an address generation unit; 7 - address switching unit; on Fig - block I / o.

The device contains (FIG. 1) synchronization unit 1, computer communication unit 2, memory management unit 3, memory unit 4, address generation unit 5, address switching unit 6, input-output unit 7, circuits 8 and 9 st computer circuit, the circuit 10-28 communication between the blocks, the circuit 29 of the initial installation signal, the circuit 30 of the start signal, the circuit 31-33 communication between the blocks, the circuit 34 of the peripheral signal supply

attribute addressing, 16-bit tires 35-50,51-66, 67-92. 93-108 data, 10-bit address tires 109-118, 119-128, 129-138, 139-148, 149-158 addresses.

The synchronization unit 1 (FIG. 2) is designed to generate the control signals necessary for synchronizing the operation of the device, and contains a clock pulse generator (GTI), a frequency divider 160, counters 161 and 162, triggers 163 and 164, a single vibrator 165, And 166 elements - 175, OR elements 176 and 177, delay elements 178 and 179, EXCLUSIVE OR 180 element. Elements NOT 181-191. Positions 192-198 denote internal communications for the unit.

The computer communication unit 2 (Fig. 3) is designed to convert the word-state of the output processor element of the computer recorded in the state register into control signals and contains bus drivers 199-200, EXCLUSIVE OR 201, elements 202 and 203

J

ABOUT

about

vj oh oh

delays, elements AND NOT 204 and 205, elements NOT 206 and 207.

The memory management unit 3 (FIG. 4) is intended to provide the priority of the computer when operating with the memory unit 4 and contains AND elements 208 and 209, OR elements 210 and 211. delay elements 212 and 213.

The memory unit 4 (FIG. 5) is intended for the on-line storage of information intended for transmission to the network or incoming from the network, and contains two operational storage nodes 214 and 215 with the organization 1024x8.

The address generation unit 5 (Fig. 6) is designed to generate address codes and contains counters 216-218. element AND 219, element OR 220, elements NOT 221 and 222, delay elements 223-225, positions 226-229 denote internal communications.

The address switching unit 6 (Fig. 7) is designed to switch the address inputs of the memory block 4 to the address buses of a computer or address generation unit 5 (depending on the presence of a computer access signal to the device), contains registers 230 and 231 and bus drivers 232 and 233 .

The input-output unit 7 (Fig. 8) is intended for short-term storage of information and its simultaneous issuing or receiving, for separating input and output information buses, for transmitting the address code to peripheral devices at the time of addressing, for disabling address lines when transmitting or receiving information and contains data bus drivers 234-237, output address registers 238 and 239, output registers 240 and 241 of data, input registers 242 and 243 of data, the element NOT 244.

The device works as follows.

Two modes of operation of the device are distinguished: the mode of information exchange between the computer and the memory unit and the mode of information exchange between the memory unit and peripheral devices (PU). Before the device starts working from the computer, the information stored in the device must be loaded into the corresponding memory cells. further for transmission to PU. In addition, a device has a computer priority for exchanging information with the device. Work in the mode of information exchange between the memory unit and the PU is divided into two cycles. The first cycle is the reception of information from the PU into the memory block; the second cycle is the transfer of information from the memory block to the PU.

Each destination in the PU corresponds to two address codes: even and odd, respectively, in the device memory block.

each addressee is assigned two cells with address codes differing by the lower order. One of them (corresponding to the even-numbered address code) is intended for storing information received from the PU. The other cell (corresponding to an odd address code) is intended for storing information that must be transmitted to the control panel. Thus, the younger bit of the address code does not participate in the selection of the addressee, but only determines the direction of information transfer. If in the lower order of the address code is logical O, then the information comes from the PU;

5, if in the low order of the address code is logical 1, then the information is transmitted to the CP; depending on the logic level on this line, the corresponding channel will be opened in the control panel to transmit or receive data.

The cycle of receiving information from the PU in the memory block consists of four cycles: the first is to generate an address code and a signal about the addressing feature, writing the address and signal about

5 sign of addressing in the output address registers; the second is the transfer of the address code to the control center together with the signal about the attribute of addressing; the third is the recording of information from the PU into the input data registers: the fourth, the recording of information from the input data registers into the memory block.

The cycle of transferring information from the memory block to the control panel also consists of four cycles: the first and second cycles are similar to the first and second cycles of the previous cycle: the third cycle is the recording of information from the memory block to the output data registers: the fourth cycle is the transfer of information from the output registers data in PU.

0Because at the beginning of the device

The address generation unit 5 immediately generates an address code. equal to one (i.e., the zero address code is excluded), and each addressee must correspond to

5, two address codes differing only in the lower section, when programming a computer, it should be taken into account that the zero and first cell of the memory unit should not be involved and, accordingly, no control panel

0 must be recipients that respond to zero and one address codes.

In order for the specified cycles to be performed alternately for each addressee, the device forms and arrives at

5 control inputs of the elements of the device signals in accordance with the table.

The generation of control signals is organized based on the operation of the binary four-bit counter 161 (FIG. 2). Clock Counter 161

resolves the counting of clock pulses from the clock generator 159 through frequency divider 160 and element 168. Upon the arrival of each of the pulses to the input of clock counter 161, a certain code is generated at its outputs. By converting this code through the synchronization unit 1 and the memory management unit 3, control signals are generated to ensure that all four clock cycles are executed.

The duration of one clock cycle is determined by the frequency of the clock pulse, which in this case is selected 100 kHz (the clock duration is 10 µs). The clock source is GTI. Its quartz resonator is capable of producing frequencies of 10-20 MHz. The GTI includes a frequency divider by nine. Setting the frequency divider to 12 at the GTI output allows obtaining frequencies in the range of 80-160 kHz.

Before starting the operation, when power is applied, a potential jump across circuit 29 (Fig. 2) through delay element 179 is fed to the input of the one-shot 165. As a result, a pulse is generated that arrives at the reset input of the trigger 164 A low potential is established at its output to one of the inputs element AND 168. which prohibits the passage of clock pulses to the counting input of the clock counter 161: thus the device is in the waiting state

Upon the arrival of the starting signal through circuit 30 to the setup input of the trigger 163, logical 1 is set at its output, arriving at the input of the AND element 166, but the device will start to work if further information is transmitted to the control panel for the corresponding cells of the memory block 4 . To accomplish this, a triggering circuit is provided, consisting of flip-flops 163 and 164. one-shot 165. elements AND 166 and 167, elements NOT 181. 191. 222. delay elements 179 (FIG. 2) and delay elements 223-225 (FIG. ).

Information is loaded into memory block 4 in the mode of information exchange between the computer and the memory block. The computer access signal to the device and all the signals necessary for the device to operate in the mode of information exchange between the computer and the memory unit are formed in computer communication unit 2 (FIG. 3) by using the WR and RD control signals of the central processor K1810BM86. working in minimal mode. The output of the RD processor element along the chain 8 and the output of the WR along the chain 9 are connected to the input of the element 201.

A computer access signal to the device is generated at the output of element 201 (Fig. 3) when it enters the Low potential circuit 8 or 9. Formed at the exit

the element 201, the signal of the computer to the device through the circuit 10 enters the synchronization unit 1 (Fig. 2) at the input of the element AND 166, while at the output of the element AND 166 a high potential is generated, arriving

0 input element NOT 191; formed at the output of the element HE 191 logical O through the chain 31 enters the block 5 forming the address (Fig. 6) at the input of the element HE 222, the high generated at its output

5, the potential is fed to the input of the element OR 220. The high level formed at the output of the element OR 220 is fed to the reset inputs of counters 216-218. whereby counters 216-218 are installed in

0 zero state. In addition, a low level in the circuit 31 from the output of the element HE 191 enters the address switching unit 6 (FIG. 7) to reset the registers 230 and 231, as well as the input / output unit 7 (FIG. 8) to the inputs

5 reset the output address registers 238 and 239. output and input registers 240-243 data.

From the output of the element AND 166 at the beginning of operation of the device, a high potential through the element OR 177 (FIG. 2) resets the counter 162. At the same time, from the output of the element HE 222, a high level enters the input of the delay elements 223-225. From the output of the element 225 on the circuit 32 high level

5 enters the synchronization unit 1 (FIG. 2) at the setup input of the trigger 164, a logical 1 is generated at its output, which, arriving at the input of the AND element 168, permits the arrival of pulses from the GTI to the count input of the clock counter 161.

Delay elements 223-225 are needed to set the duration of a drop pulse. sufficient for these elements to be reset before the first clock pulse arrives at the counting input of counter 161.

High levels from the output of the element HE 222 through the circuit 32 and from the output of the trigger 164 fall on the inputs of the element AND 167, the start signal (the Start signal) enters the synchronization unit 1 via the chain 30 (figure 1). When at the end of the Start signal on the circuit 30 a low potential is established, from the output of the element HE 181 to the input of the element AND 167

5 will also receive a logical one. A high potential will be generated at the output of the AND element 167, which will reset the trigger 163. High potential will be established on circuit 31, and low potential will be established on circuit 32, but since logical 1 output trig repa 164 is Vits only after a low potential is established at its reset input, then the low potential received at the installation input of trigger 164 via circuit 32 will not change its state, and logical 1 at the input of element AND 168 will be maintained until power is applied to the circuit. Thus, the device will be in a standby state until a signal is generated by the computer to access the device. This launch phase will take place only at the beginning of the device operation.

After the startup phase, information is exchanged between the computer and the memory unit. The signal generated by the output of element 201 (Fig. 3) of the computer to the device along the circuit 10 is also fed to the input of the element HE 182 (FIG. 2), while a logical O is received from the output of the element HE 182 to one of the inputs of the element OR 176, but at the output of the element OR 176, the logical O for the Vits only if the remaining three rods of the element OR 176 also have low potentials. This is possible only when the clock counter 161 is in the reset state, i.e. the next cycle of transmission or reception of information is completed (or not yet started). In this case, at the output of the element OR 176, a logical O is formed, which arrives at the input of the element AND 168, which prohibits further passage of the clock pulses to the counting input of the clock counter 161; along with this, the low potential after inversion in the element HE 183 enters the input element AND 171.

If a high potential also appears at the second input of the element And 171, then logical 1 will be formed at its output, i.e. signal to interrupt the operation of the device. This signal on the circuit 14 (figure 4) enters the memory control unit 3 at the inputs of the elements OR 210 and 211 and at their outputs high levels are formed which, at the inputs of the elements AND 208 and 209 (figure 4), will ensure the passage through elements AND 208 and 209 of control signals formed in block 2 of the communication with a computer and fed through circuit 22 and 23. At the same time, across the circuit 11, the same high potential through delay element 202 goes to the inputs of AND-HE elements 204 and 205, which allows the formation of control signals that provide the mode of information exchange between the computer and com 4 memory.

The delay element 202 is needed so that the formation of these signals begins later than the work will be interrupted.

devices in the mode of information exchange between the memory unit and the PU. At the same time, logical 1 from circuit 11 will go to the readiness input in the computer, informing that the operation of the device is interrupted.

If there is a low potential on circuit 8 (Fig. 2), and a high potential on circuit 9 (which corresponds to the mode of reading information from memory block 4 in a computer), then logic G c

0 output element 201 (Fig. 3) gets to the input element AND-NOT 205, and the logical element O from circuit 8 enters the input of element IS-NOT 204. Thus, logical 1 is formed at the output of element AND-HE 204 and output 5 In this case, a logical O element is generated in the NAND element 205 (since the other inputs maintain a high potential formed at the output of the delay element 202).

0 The circuit 23 from the output of the element AND-NOT 204 logical 1 arrives at the input of the element AND 208 (FIG. 4), and since a high potential is maintained at the other input of this element, a logical 1 and through the circuit 27 will go to the write-read inputs of the memory block 4 (Fig. 5).

At the same time, the logical O from the output of the NAND element 205 is fed to the input of the delay element 203. From the output of the delay element 203, a logical O arrives at the input of the element AND 209 (Fig. 4) (while logical 1 is maintained at the other input of the element 209), so a logical O is formed at the input of the element 209 to the synchronous inputs of the memory block 4 (figure 5), which will allow its operation in the read mode, since logical 1 is at the write / read inputs.

The delay element 203 is necessary so that the signal arriving at the synchronous inputs of memory block 4 and allowing access to it, comes a bit later than

5 signal to the write / read inputs, determining the operation mode of the memory block.

Simultaneously, the logical About from the output of the element AND-NOT 205 will go to the inputs CS1 of registers 230 and 231 (Fig.7) along the circuit

0 33, as well as the input element HE 207 (Fig. 3), from the output of which the circuit 24 sends the logical 1 to the inputs EW, MD, CS2 of registers 230 and 231. The signals generated in this way allow the transmission of address codes from the computer 109-118 to the address inputs 129-138 of memory block 4. In this case, bus formers 232-233 (Fig. 7) switch to high impedance (along circuit 24 to inputs OE of bus formers (FF) 232 and 233)

logic 1, which provides electrical isolation between the output lines of registers 230 and 231 and ShF 232 and 233). In addition, the logical O from the output of the element AND-NOT 205 (Fig. 3) will go to the control inputs of the OE ShF 199 and 200 (Fig. 3), which will allow their operation, and the logical 1 from the output of the element HE 207 will go through 24 to the control inputs C5 ShF 234-237 (Fig. 8), which will allow their operation. At the same time, logical 1 from the output of the AND-HE element 204 will go to the input of the HE element 206 (FIG. 3). The logical O generated at the output of the element 206 is fed to the inputs T of the SchFs 199 and 200, which will ensure their operation in the mode of data transmission from the memory block to the computer.

In the event that circuit 8 is logical 1, and circuit 9 is logical O (which corresponds to the recording mode in block 4 of the information stored in the computer), all processes proceed in the same way, except that -NON-204 logical O is formed and through circuit 23 through AND of 208 (FIG. 4) through circuit 27 will go to the write / read control inputs of memory 4, which will transfer it to write mode: the same level from the output of the AND- element HE 204 to the input element HE 206 and a high level from the output of the element NOT 206 falls on the control inputs T of the group of bus terminals Lines 199 and 200, which will ensure the direction of data transmission from the computer to memory block 4 from circuits 35-50 on circuit 51-66.

If at the time of the formation of a signal to interrupt the operation of the device. those. when the three lower bits of the counter 161 are in the state 000 and the first input of the element OR 176 (FIG. 2) also received a logical O, the counting input of the counter 161 passed the regular clock pulse through the element 168 And, the clock counter 161 will take the state at outputs 001 and at the output of the element OR 176, logic 1 is also caught, which means the beginning of a new cycle. In this case, the logical O, formed at the output of the element OR 176, arriving at the input of the element NOT 183, will allow the unit 2 to communicate with the computer, which outputs control signals simultaneously with the control signals of the synchronization unit. In order to exclude such a case, the generated signal about the interruption of the operation of the device passes through a duration test circuit implemented on the basis of the counter 162 and included in the synchronization unit 1 (Fig. 2).

The scheme works as follows.

The counter 162, when there is no signal from the computer to the device, will be reset to zero, since in this case, the output of the OR element 176 will be a logical G, which will be fed to the reset input of the counter 162. At the outputs of the counter 162, a low potential is maintained, the output corresponding to Section 2 is connected to the input element HE 187, i.e. element output

0 NOT 187 logical 1. is generated. It is fed to one of the inputs of the AND 169 element. The other input of the AND 169 element receives clock pulses from the output of the frequency divider 160. At the third entrance of the element And 169 in

At this moment, the low potential coming from the output of the element HE 183 will be maintained, therefore the clock pulses will not pass to the counting input of the counter 162. As soon as the output of the element OR

0 176 a logical O is generated; at the reset input of the counter 162 also a logical O.

In addition, formed at the output of the element HE 183 logical 1 through the chain 198

5 permits the passage through the AND element of 169 clock pulses, which from the output of the AND element 169 are sent to the counting input of the counter 162.

If during the formation of the signal about

If an interrupt through the element And 168 did not have time to pass the next clock pulse to the counting input of the clock counter 161, then the potential of the element OR 176 will be kept low. This low potential will prohibit the passage of clock pulses through AND 168. Logic 1, formed at the output of the HE element 183, will allow the passage of clock pulses through AND 169 to the counting

0 is the input of counter 162. When the second pulse is applied to the counting input of counter 162, its output corresponds to bit 21. A logical 1 turns on, which goes to the input of the And 171 element and will allow the interrupt signal from the other input of And 171 to pass its output, i.e. on circuits 11 and 14. If the interrupt signal has a duration of one clock cycle (from the front of the first pulse that arrived at the counting input

0 of the counter 162, up to the front of the second pulse), the case of passing the clock pulse through the AND element 168 at the time of generating the interrupt signal is excluded (since the switching time of the elements

5 176.168 order 25NS. and the time of one tick Yumks).

If during the formation of the interrupt signal, the next clock pulse hits the counting input of the counter 161, logical O at the output of the element

OR 176 through 50NS is replaced by logical 1, which will allow the arrival of clock pulses at the counting input of the clock counter 161 and simultaneously reset the counter 162, at discharge 2 of which the logical 1 does not have time, so the high potential does not pass to the input of the And 171 element, which prohibits the passage on the circuit 11 and 14 of a false interrupt signal. The device in this case will be interrupted only on the next cycle.

In the event of the termination of the signal from the computer to the device at the output of the element OR 176, a high potential is established, which resets the counter 162 and allows the arrival of clock pulses to the count input of the counter counter 161. i.e. The device switches from the mode of information exchange between the computer and the memory unit 4 to the mode of information exchange between the memory unit 4 and the control unit.

When a pulse arrives at the counting input of counter 161 (Fig. 2), its outputs send a code of 0001, respectively, a high potential is established on circuit 192, and a low potential on circuit 193, and logical 1 is formed at the output of HE 185 and goes to one from the inputs of the element And 172, to the other input of the element And 172, the circuit 192 also receives logical 1. At the output of the element And 172, a high potential is formed and through the circuit 12 it goes to the counting input of the counter 216 (Fig. 6).

At the same time, at the outputs of a group of counters 216-218 (on chains 119-128), the address code is displayed. The counting input of the counter 216 pulse will be received only if there is a logical 1 on the circuit 192 and a logical O on the circuit 193, which corresponds to the case when the outputs of the clock counter 161 are 0001, in any other case the counting input of the counter 216 will have a low potential, and the generated address code will be held at the outputs of a group of counters 216-218 for the entire four-cycle cycle.

The address code enters the chains 119-128 to the input of SchF 232-233 (Fig. 7. SchF constantly working in the same direction of transmission). From output ShF 232-233 through the chains 139-149, the address code is written into the output address registers 238-239. The MD inputs of these registers provide a write mode, which is at a low potential, which is formed by the following elements: element NOT 186, element AND 173; when entering the inputs from the circuits 192 and 193 of logical 1 and logical O, respectively, both the inputs of the element And 173 will have a low potential, therefore

A logical O is formed at the output of the AND 173 element and enters the MD of the output address registers 238 and 239 via the circuit 19 (FIG. 8), the logical 1 formed at the output of the EW strobe of the output address registers 238 and 239 of the output 20 of the HE 184 (FIG. 2), logical O is fed to inputs CS1 of registers 238 and 239, logical 1 is fed to inputs CS2, which ensures that the output address registers 238 and 239 (FIG. 7) work in recording mode.

At the same time, the incoming through circuit 12 to the counting input of the counter 216 (Fig. 6) logical 1, allowing the formation of the address code, also enters through delay element 178 (Fig. 2) through the circuit 21 into the register 239 and is fixed in it. In this way, a signal of the addressing feature is generated. The high potential of the addressing feature, having entered the PU into a separate circuit 34 (FIG. 1) together with the address code, carries information about the arrival of the address. Since the direction of transmission is determined by the lower-order bit of the address code after passing the address through ShF 232 and 233, the lower-order bit of the address along circuit 139 (Fig. 7) is supplied to memory management unit 3.

This ends the first beat. Along with these processes, during the first clock cycle, circuits 192 and 193 are logical 1 and logical O, respectively, fed to the inputs of element 180, forming logical 1 at its output, which flows through circuit 13 to one of the inputs of the OR element 211 (FIG. 4) , on the other input of which, in the absence of a signal with interruption, there will be a low potential. From the output of the element OR 211, logical 1 is fed to one of the inputs of the element AND 209, the second input of which, provided that there is no interruption signal, is at a high potential, i.e. At the output of the element And 209, a logical 1 is formed, which is fed through the circuit 26 to the synchronous inputs of the memory block 4 and permits its operation.

In addition, from the output of the element OR 211 through 28, the logical is fed to the inputs of the CS registers 240-243 (Fig. 8) and the inputs of the CS2 registers 238 and 239. After the element HE 244, this potential is converted into a logical O and fed to the inputs CS2 of the registers 240 243 and to the inputs CS1 of registers 238 and 239. thereby permitting the operation of output address registers 238 and 239 and prohibiting the operation of output and input registers 240-243 data.

In the second cycle, after the next clock pulse arrives at the counting input of counter 161, its outputs change

the code and on circuit 192 is now set to logical O, and on circuit 193 - logical 1. At the same time, logical O is formed at the output of AND 172 (FIG. 2), and logical 1 is output at AND 173, which enters input 19 through circuit 19 MD output address registers 238 and 239, which puts them in read mode. The address code on chains 149-158, along with the signal about the sign of addressing (on chain 34), will go to the control panel. All other elements of the device will remain as they were, since the potential at the output of element 180 will remain unchanged. The delay element OR 178 is necessary so that when switching the output address registers 238 and 239 from the write mode to the read mode, the high potential along the circuit 21 does not knowingly change the state of the output address register 239.

During the third cycle on the chains 192 and 193 (Fig. 2), a high potential is maintained, and the output potential of the And 172 element is still low. At the output of the element And 173, a low potential is also established, which places the output address registers 238 and 239 in the recording mode, disconnecting their outputs from the PU. At the output of the element 180, the logical O turns on. If there is no signal about interrupting the circuit 14, there will be a logical O, and on chains 22, 23 - logical 1. Thus, the logical O formed at the output of the element 180. without changing it goes through the LRI element 211 and the AND element 209 (FIG. 4) to the CS outputs of the memory block 4 (FIG. 5), which will allow access to the memory (to the input of the OR element 211 (FIG. 4, in this case, circuit 14 receives logical O, and the logical element 1 goes to the input of the AND element 209 from the circuit 22. At the same time, logical O from the output of the OR element 211 goes to the input 28 via the circuit 28 The CS1 registers 240-243 (Fig. 8) and the inputs CS2 of registers 238 and 239, while logical inputs G are formed at the inputs CS2 of registers 240-243 and at the inputs CS1 of registers 238 and 239, which will allow the operation of registers 240-243, and The registers 238 and 239 will be disabled. However, the potential from the output of the bus drivers 232 and 233 will be maintained on the circuit 139 (Fig. 7) corresponding to the lower-order bit, since the address code does not change.

Through the elements 212 and 213 of the delay (figure 4), this signal enters the input of the element OR 210, and from its output unchanged - at the input of the element AND 208 and further from the output of the element AND 208 also unchanged through the circuit 27 to the inputs of the write / read block 4

memory (FIG. 5), since in the absence of an interrupt signal, the input of the OR 210 element will be 0m from the circuit 14, and the logical 5 eka 1 will go to the AND208 element from the circuit 23.

The same low-order address signal, removed from the output of the OR 210 element, is fed through the circuit 25 to the inputs B of the bus driver (PF) 234-237 (FIG. 8), which denotes the corresponding channel PF 234-237, since Circuits 139, in this case, the potential is low, while the memory block 4 will be ready for recording, and SchF 234-237 (Fig. 8) will be opened to transfer information from the input data registers 242 and 243 to the memory block 4. Registers 240-243 will be in recording mode, since high potentials are maintained on lines 192 and 193 (Fig. 2), and HE 185 and

0 186 low potentials will be formed that go to the inputs of the elements And 174 and 175. At the outputs of which logical O are also formed. Through the circuit 15, the logical O will go to the inputs of the MD registers 242 and 243

5 (FIG. 8), and via circuit 17, to the inputs of MD registers 240 and 241. Through the elements HE 189 and 190 (FIG. 2), via the chains 16 and 18, these signals in the form of logical 1 arrive at the inputs of the strobe registers 240 -243 (Fig.8), which corresponds to

0 their operation in the recording mode, In the registers 242, 243 will be recorded information received in this cycle from the PU. The state of registers 240 and 241 in the third cycle is indifferent. During the fourth cycle on the chain

5 192 and 193 (Fig. 2) the potential is kept low. In this case, the outputs of the elements And 172 and 173 is still low potential. Access to memory block 4 (FIG. 5) is allowed at input Cg (on circuit 26 logical O).

0 On circuit 27 is also a logical O, coming to the write / read inputs of memory 4 and defining the operation of memory 4 in write mode. ShF 234-237 (Fig.8) work in the direction of transmission

5 information from the input data registers 242 and 243 to the information inputs 51-56 of memory block 4. In the fourth, also the input data registers 242 and 243 operate in the information reading mode, the state

0 output data registers 240 and 241 are indifferent.

From the outputs of the elements HE 185 and 186 (Fig. 2) logical inputs 1 are fed to the inputs of the elements AND 174 and 175 along the chains 195 and 196.

5 Logical 1 arrives at the input of AND 175 through circuit 25 and logical 1 also arrives at the input of element AND 174 from the output of element HE 188. At output of element AND 174, logical 1 is output. At output of element 175, logical O is received.

Thus, the inputs of the strobe of the output data registers 240, 241 (Fig. 8) from the output of the HE element 190 (Fig. 2) go through circuit 18 to logical 1, and to the inputs of MD, via the wire 17 from the output of item And 175, logical O comes. The input MD of the input data registers 242 and 243 (Fig. 8) from the output of the AND element 174 (Fig. 2) goes through logic 15 through the circuit 15. To the input of the gate of the input data registers 242 and 243 (Fig. 8) from the output of the HE element 189 (FIG. 2) a logical O will be sent along the circuit 16, and from the input data registers 242 and 243 (FIG. 8), the information received from the PU and the simultaneous write through ShF 234-237 to block 4 of memory along chains 51- 66. At the inputs of the CS1 registers 240-243 and CS2, the registers 238, 239 are still low potential, and at the inputs of the CS2 registers 240-243 and CS1 of registers 238 and 239 - high potential.

In the cycle of information transfer from memory block 4 to the control unit, the first two cycles are similar to the first two cycles of the information reception cycle from the control unit to memory block 4. In the third cycle, access to the memory block 4 is allowed. The high potential arriving through the circuit 139 forms, at the output of the element OR 210 (Fig. 4), a logical 1st, which through the element AND 208 and further along the chain 27 enters the write / read input, transferring the memory block 4 to the read mode. At the same time, the same logical 1 through the circuit 25 is fed to the inputs of ShF 234-237 (Fig. 8), which determines the direction of transfer of ShF 234-237 from memory block 4 to output data registers 240 and 241. Information read from the block 4 memories in chains 51-66 through ShF 234-237 in chains 245-260, will be written into the output registers 240 and 241 of the data. The inputs of the CS1 registers 240 243 CS2 registers

238 and 239 - low potential; on inputs CS2 of registers 240-243 and CS1 of registers 238 and

239 - high potential; at the inputs of MD registers 240-241 - low potential, at the inputs of the gate - high potential.

Thus, registers 240 and 241 operate in write mode, the state of registers 242 and 243 is indifferent, registers 238 and

239 are disabled.

In the fourth cycle, information is read from the output registers 240 and 241 of data in the control panel along chains 67-92. Memory block 4 is still in read mode, but the output data registers

240 and 241 do not perceive more data from information circuits 51-66 of memory block 4, transmitting information to PU, since circuit 25 has a high potential, the output of the AND 174 element (figure 2) is low, and the output of the AND 175 element - tall. Accordingly, at the inputs of the gate of registers 240 and 241 (Fig. 8) there are logs of the ioi cue O, and at the inputs of the MD - logical 1, which provides

their operation in the read mode, the inputs of the strobe of the registers 242 and 243 will go to logical 1, and to the inputs of the MD will be logical O, which brings the registers 242 and 243 to the write mode, but their state in this case is personal; output address registers 238 and 239 are still off the circuit

The indifference of the address registers is possible because the address was previously recorded in the corresponding PU. At the end

5 of each four-cycle cycle, the counter 161 is reset (FIG. 2) and when the next clock pulse arrives at the counting input of the counter 161, the counting begins first, a new address is generated and

0, all processes are repeated.

The delay elements 212 and 213 (Fig. 6) are necessary so that at the end of the fourth cycle before the beginning of the first cycle, the memory access is stopped at the beginning,

5 and then a switch was made on the write / read input j to avoid distortion of information. When zero and single address codes are maintained at the outputs of a group of counters 216-218 (FIG. 6), the device runs idle, since there is no destination in the control center, and in the memory block - cells that would react to these address codes. When the output of the address resolver group is set

5 code corresponding to the number 1025, counters 216-218 are reset. In this case, the output of the element is NOT 221. A logical 1 is formed, along the chain 226, coming to the input of the element 219, to the input of the element 219

0 enters logical 1 from the output of the counter 218, corresponding to the second discharge through the chain 227, Logic 1, formed at the output of the AND 219 element, through the chain 228 enters the input of the OR element 220, and from it

5 outputs on circuit 229, the counters 216-218 are reset.

Claims (4)

Claim 1. Device for interfacing a computer with peripheral devices containing a communication unit with a computer, a memory unit, an input / output unit, a memory management unit, the first group of information input-output units of the communication unit with a computer forming a group of inputs -outputs for 5 connections to a group of information inputs / outputs of a computer, the first, second groups of information outputs and the first group of information inputs of an I / O unit form a group of inputs and outputs of a device for connecting to information and address inputs / outputs of peripheral devices, reduce hardware costs, a synchronization block, an address generation block, an address switching block are entered into the device, and the setup input and the trigger input of the synchronization block are device inputs for connecting According to the installation input and the start output of the computer, the first synchronized output of the synchronization unit is connected to the enabling input of the communication unit with the computer and is the output of the device for connection to the readiness of the computer, the first, second information inputs of the communication unit with the computer are connecting respectively to the write and read outputs of the computer, the first group of information inputs of the address switching unit forms a group of device inputs for connecting to the group of address outputs of the computer, the information output of the block water output is the output of the device for connecting to the inputs of the addressing attribute of peripheral devices, while the second group of information inputs-outputs of the communication unit with a computer is connected to the group of information inputs-outputs of the memory unit and the group of information inputs-outputs of the input-output unit , a group of gate inputs of which is connected to a group of sync outputs of the synchronization unit, the first enabling input of which is connected to the information output of the address generation unit, the group of information outputs of which are connected Inena with the second group of information inputs of the address switching unit, the first group of information outputs of which is connected to the second group of information inputs of the input / output unit, the gate input of which is connected to the control input of the address switching unit and the first information output of the communication unit with a computer, the second information the output of which is connected to the gate input of the address switching unit, the second group of information outputs of which is connected to the group of address inputs of the memory block, the gate input and input which records are connected respectively to the first and second outputs of the memory control unit, the third output of which is connected to the second enabling input of the synchronization unit and to the first input of the operation mode of the I / O unit, the second input of the operation mode of which is connected to the fourth output of the memory management unit , the first and second inputs of the logic condition of which are connected respectively to the third and fourth information outputs of the communication unit with a computer, the fifth information output of which is connected to the third permitting input The second, third, and fourth sync outputs of the synchronization unit are connected respectively to the third and fourth inputs of the logical condition of the memory management unit and to the synchronous input of the address generation unit, the setup input of which is connected to the sync output of the synchronization unit - output and with the installation input of the address switching unit, junior The 5th bit of the first group of information outputs of which is connected to the fifth input of the logic condition of the memory control unit. 2. The device according to claim 1. that is, that the memory control unit contains two OR elements, two AND elements, two delay elements, the first inputs of the first and second AND elements being respectively, the first, the second inputs of the logical condition of the block, the first input of the first OR element is connected to the first input of the second OR element and is the third input of the logical condition of the block, the second input of the second OR element and 0, the input of the first delay element are respectively the fourth and fifth inputs of the logical condition of the block, the outputs of the first and second elements of AND are the first and second outputs of the block, respectively 5, the output of the first element OR is connected to the second input of the second element AND, and is the third output of the block, the output of the second element OR is connected to the second input of the first element AND, and is the fourth 0 by the output of the block, while the output of the first delay element is connected to the input of the second delay element, the output of which is connected to the second input of the first OR element. five 3. The device according to claim 1, of which is that the communication unit with a computer contains two bus formers, two elements are NOT. two NOT elements, two delay elements, EXCLUSIVE OR. where 0 group of information outputs of the first bus driver and a group of information inputs of the second bus driver form the first group of information inputs / outputs of the block, 5 the group of information inputs of the first bus driver and the group of information outputs of the second bus driver form the second group of information inputs-outputs of the block, the first input of the EXCLUSIVE element OR is connected to the first input of the first NAND element and is the first information input of the block, the second input of the EXCLUSIVE OR element and the input of the first delay element are respectively the second information and enabling inputs of the block, the output of the first element is NOT the first information output of the block, the output of the second element is NOT connected to the input of the second delay element, to the input of the first element NOT, to the first control inputs of the first and second bus drivers and is the second information output block a, the output of the second delay element is the third information output of the block, the output of the first element AND- NOT is connected to the input of the second element NOT and is the fourth information output of the block, the output of the element EXCLUSIVE OR is connected to the first input of the second element AND-NOT and is n In this case, the output of the first delay element is connected to the second inputs of the first and second NAND elements, the output of the second element is NOT connected to the second control inputs of the first and second bus drivers. 4. Device pop. 1, characterized in that the address generation unit contains three counters, two NOT elements, AND element, OR element, three delay elements, the input of the first element is NOT the installation input of the block, the count input of the first counter is the synchronous input of the block, the output of the first delay element is the information output of the block, the groups of the bit outputs of the first, second and third counters form a group of information outputs of the block, and the input of the first delay element is connected to the output of the second element delay, the input of which is connected to the output of the third delay element, the input of which is connected to the output of the first element NOT and to the first input of the element OR, the second input and output of which are connected respectively to the output of the element AND and to the installation inputs of the second, third and first counters, the least significant g group of bit outputs of which is connected to the input of the second element NOT, the output of which is connected to the first input of the element I, the second input of which is connected to the transfer output of the third counter, the counting input of which is connected to the output house transport of the second counter, the counting input of which is connected to the output of the first counter transfer. 5, the device according to claim 1. This is due to the fact that the synchronization unit contains two triggers, two counters), clock generator, frequency divider, one-shot, ten AND elements, two OR elements, eleven NO elements, the EXCLUSIVE OR element , two delay elements, the installation input of the first trigger is connected to the input of the first element NOT and is the start input of the block, the input of the first delay element is the installation input of the block, the input input of the second trigger is connected to the first input of the first AND element and R The block enable input, the input of the second element is NOT connected to the first input of the second element AND, and is the second allowing input of the block, the input of the third element is NOT connected to the first 0 is the input of the third AND element and is the third enable input of the block, the output of the fourth AND element is the first and second sync outputs of the block, the output of the EXCLUSIVE OR element is 5, the third sync output of the block, the output of the fifth element I is connected to the input of the second delay element and is the fourth synchronized output of the block, the output of the fourth element is NOT the fifth synchronous block of the block, the output of the second delay element, the output of the sixth element I connected to the input of the fifth element NO, the output of the fifth element is NOT, the output of the sixth element is NOT, the output of the seventh element AND, connected to 5 the input of the sixth element is NOT, the output of the seventh element is NOT, the output of the second element is And connected to the input of the seventh element of the NOT form a group of sync outputs, block, and the generator output 0 clock pulses connected to the input of the frequency divider, the output of which is connected to the first inputs of the eighth and ninth elements And, the outputs of which are connected respectively to the counting inputs of the first and 5 of the second counter, the output of the first element And is connected to the reset input of the first trigger, the output of which is connected to the second input of the third element And, the output of which is connected to the input of the fourth element NOT 0 and with the first input of the first element OR, the output of which is connected to the installation input of the second counter, the output of which is connected to the first input of the fourth element AND, and to the input of the eighth element NOT, 5 whose output is connected to the second input of the ninth element AND, the third input of which is connected to the second input of the fourth element AND and to the output of the ninth element NOT whose input is connected to the output of the second OR element, to the second input of the first the OR element and the second input of the eighth element AND, the third input of which is connected to the second input of the first element AND and the output of the second trigger, the reset input of which is connected to the output of the one-oscillator, the start input of which is connected to the output of the first delay element the third input of the first element I. the output of the third element is NOT connected to the first input of the second element OR, the second input of which is connected to the first input of the fifth AND element, to the first input of the EXCLUSIVE OR element, to the first output of the first and the input of the tenth item is NOT. the output of which is connected to the second input of the second element I, to the first inputs of the sixth, 0 five the seventh And elements and the first input of the tenth And element, the output of which is connected to the installation input of the first counter, the second output of which is connected to the second input of the sixth AND element, to the second input of the EXCLUSIVE OR element, to the eleventh element input and to the third input of the second element OR, the fourth input of which is connected to the third output of the first counter and to the second input of the tenth element AND, the third input of which is connected to the output of the eleventh element NOT, to the second input of the fifth element AND, and to the third input the second AND gate and a second input of the seventh AND gate, the third input of which is connected to the output of the second NOT member. 15-21 50 1 23 Physical.4 u129-m L III t 225 12 Ur-j t-of 230 WB-fff 31 1L and FIG. five 32 226 119-128 g 218 227 229 FIG. AT H9-f4ff Pd-1b FIG. 7