SU1580362A1 - Device for arbitration of inquiries - Google Patents

Abstract

The invention relates to computing and can be used in multiprocessor trunk-modular computing systems. The purpose of the invention is to increase speed. The device contains three memory blocks 1, two registers 2.3 groups of elements OR 6, the inputs of which are connected to the outputs of memory block 1, multiplexer 10. The device provides a sequential service of requests received at the input of register 3, and the search for each next request is performed by one measure. This ensures the highest priority of the request, the number of which is the closest, next to the served one. 1 il.

Description

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The invention relates to computing and can be used in multiprocessor trunk-modular computing systems.

The purpose of the invention is to increase the speed of action.

The drawing shows a functional diagram of the device.

The device contains 1 memory blocks (programmable logic arrays), register 2, register 3, inputs 4 device requests, device synchronization input 5, elements OR 6, addressable

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inputs 7 of blocks 1, informational inputs of the blocks to be counted by the number of electronic signals 8 blocks 1, outputs 9 blocks 1, multiplexer 10, outputs 11 blocks 1, device synchronization input 12, device information outputs 13, decoder 14, device interrupt outputs 15 , outputs 16-18 blocks 1, elements AND-OR 19, outputs 20 blocks 1.

The device works as follows.

According to the initial setting signal 21-25, all bits of registers 2 and 3 are set to the zero state. In this case, all outputs of the first group of information outputs of register 2 are in the zero state, and one of the outputs of the second group is in the single state, which corresponds to the highest current priority

Service requests 4 from all

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Sa, which is selected as follows, the Co-H corresponding group of requests is selected. In one of the following cases: at the input 8 of the corresponding block 1 there is a request, the number of which is greater than the code at input 7 (unit at output 17); 1, at the input 8 of the corresponding block 1 there is at least one request t and at the inputs 8 there are no other requests (unit at output 16) of the corresponding block 1 and at outputs 18 of the other blocks 1; at outputs 8 of the corresponding block 1 there is at least one request, and at inputs 8 of the previous block 1 there is no request, the number of which is greater than the code at inputs 7 (unit at output 16) of the corresponding block 1 at output 20 of the previous block 1 and at outputs 4 and 5 or 6 of register 2, indicating that a query from the previous block 1 was selected before,

devices are sent to register 3, requests are received at input 5, blocks 1 at input 8 receive all requests from the second register 3, and inputs 7 from register 2 through the elements OR 6 - the request number code, which is currently servicing - NII.

Each block 1 compares the picture of requests arriving at its inputs 8 from the output of register 3, with the code arriving at its inputs 7 B. As a result of the analysis, block 1 generates at outputs 9 the code of one of the requests received at its inputs 8 whose number is greater than the code at inputs 7 and next. If the request with this number is not present, then at the outputs 9, a request code is formed at input 8 with the smallest number. For example, input requests 7 have been received with numbers 1, 7, and code 5 has arrived at input 7. Then

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Additional outputs of blocks I show; outputs 11 and 16 - at input 8 there is at least one request output 17 - at input 8 there is a request whose number is greater than the code at input 7; exit 18 - there is not a single query at input 8; exit 20 - there are no requests at the input 8, the numbers of which are greater than the code at input 7,

The elements AND-OR 19 analyze the additional outputs of blocks 1 in order to determine which group should be preferred, i.e. outputs 9 ka0

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Sa, which is selected as follows, the Co-H corresponding group of requests is selected. In one of the following cases: at the input 8 of the corresponding block 1 there is a request, the number of which is greater than the code at input 7 (unit at output 17); 1, at the input 8 of the corresponding block 1 there is at least one request t and at the inputs 8 there are no other requests (unit at output 16) of the corresponding block 1 and at outputs 18 of the other blocks 1; at outputs 8 of the corresponding block 1 there is at least one request, and at inputs 8 of the previous block 1 there is no request, the number of which is greater than the code at inputs 7 (unit at output 16) of the corresponding block 1 at output 20 of the previous block 1 and at outputs 4 and 5 or 6 of register 2, indicating that a query from the previous block 1 was selected before,

At the same time, the unit can appear at the output of only one of the three AND-OR elements. 19 In register 2, the code from the output of the selected block 1 (outputs 1-3 of register 2) and the outputs of the AND-OR 9 .. elements is entered (unit

at one of the outputs 4-6 register 2).

with

Claims (1)

The invention The device for arbitration requests, containing two registers, a decoder, (and a group of device request inputs are connected to a group of information inputs of the first register, the synchronization inputs of the first and second registers are connected to the device synchronization input, which speed, the device contains three groups of elements OR, three elements AND-OR (the number of groups of elements OR and the number of elements AND-OR is equal to the number of request inputs), three memory blocks and multiplexer, the output group of which is connected to the first group of information inputs of the second register, the second group of information inputs of which are connected to the outputs of all AND-OR elements, the reset inputs of the first and second registers connected to the reset input of the device, the first, second and third outputs of the second register are connected to the direct inputs of the first, second and third elements OR of the first group, the fourth, fifth and sixth outputs of the second register are connected to the inverse by the inputs of the OR elements of the first, second and third groups, respectively, the group of outputs of the first register is connected to the address x inputs of all memory blocks, the address inputs of each of which are also connected to the outputs of the elements of the OR group of the same name, the first groups of outputs 15 all the memory blocks are connected to the informational outputs of the second memory unit connected by the multiplexer's memory inputs, whose address inputs are connected (to the outputs of all AND-OR elements, the sixth output of the second register is connected to with the seventh input of the second element AND-OR, the third output of the second group of outputs of the third memory block is connected to the fifth and sixth inputs of the third the first input of the first AND-OR element, the AND-OR element, the seventh input of which the second input of which is connected to the first output of the second group of outputs of the third memory block, the first output of the second group of outputs of the first memory block is connected to the first input of the second AND-OR element, the second input of which is connected to the fourth output of the second register, the fifth output of which is connected to the first input of the third element is AND-OR, the second input is k35 connected to the fourth output of the second group of outputs of the third memory block; the fifth outputs of the second group of outputs of the memory block are combined and are the signal output of the device; the outputs of the decoder are outputs of the interrupt of the device, the information outputs of which are connected to the outputs of the second register, 40 Editor G. Gerber Compiled by M. Kudr Shev Tehred A. Kravchuk Proofreader I. Muska Order 2013 Circulation 571 VNIIPI State Committee for Inventions and Discoveries at the State Committee on Science and Technology of the USSR 113035, Moscow, Zh-35, Raushsk nab. 4/5 362 five 0 Secondly, it is connected to the first output of the second group of outputs of the second memory block, the second output of the second group of outputs of the first memory block is connected to the third inputs of the second and third AND-OR elements, the second output of the second group of outputs of the second memory block is connected to the third input of the first and with the fourth input of the third AND-OR element, the second output of the second group of outputs of the third memory block is connected to the fourth inputs of the first and second AND-OR elements, the third output of the second group of outputs of the first memory block is connected to the fifth and sixth inputs The first element is AND-OR, the fourth output of the second group of outputs of the first memory block is connected to the seventh input of the first AND-OR element, the third output of the second group of outputs of the second memory block is connected to the fifth and sixth inputs of the second AND-OR element, fourth output second group  the outputs of the second memory block is connected with the seventh input of the second element AND-OR, the third output of the second group of outputs of the third memory block is connected to the fifth and sixth inputs of the third five connected to the fourth output of the second group of outputs of the third memory block; the fifth outputs of the second group of outputs of the memory block are combined and are the signal output of the device; the outputs of the decoder are outputs of the interrupt of the device, the information outputs of which are connected to the outputs of the second register, 40 Subscription