SU1125762A1 - Start-stop synchronizer of sessions of slave station - Google Patents

Abstract

A START-UP TIME CHRONIZER OF THE SESSIONS OF A SLAVE STANVDSH containing an address signal detector, a clock pulse generator, and a start-stop trigger connected, a clock counter and a decoder block, the corresponding bit outputs of which, except for the first and second-last bit outputs, can be adapted by the drawers, and the digs can be used by the drawers, and the corresponding digits can be used by the drawers, which correspond to the bit outputs of which, except for the first and the last last bit outputs, the draws can be used. , to the other relevant inputs of which are connected the outputs of the synchronization depth determination unit, the penultimate and last outputs of which are connected The first element OR is connected to the clock counter, and the output of the address signal and nepsbtft is the bit output of the decoder unit connected to the first and second inputs of the sync depth unit, which is In order to improve the stability of synchronization without reducing the noise immunity of synchronizing data sessions, the second and third OR elements, the delay block 55: ki and the AND element, to the first, second The first and second inputs of which are connected to the output of the address signal detector, the penultimate output of the synchronization depth block and 9 the penultimate bit output of the decoder block, and the output of the AND element are connected to the delay block and the first input of the second SHS element, to the second input of which is connected the output of the block of elements is AND-OR, and the output of the block of delay is connected to the first input of the third element OR, to the second input of which the output of the address signal detector is connected, while the outputs of the second and mp t- or its elements are connected respectively to the start and stop inputs of the start-stop trigger and the output of the first OR gate is connected to input elements sootvetstvukltsemu block I-Hilti.

Description

The invention relates to telecommunications and is intended for terminal stations of combined data transmission systems and trajectory measurements with time division and session synchronization by signals from the main station.

A start-stop chronizer of sessions of a slave station is known, containing a successively connected address signal detector, a start-stop trigger and a clock pulse counter with descramblers, which counter is connected to the generator of 1 pulses: pulses, and the serially connected register and element of NL-NE.

The closest to the technical solution of the invention is the startCTOtiiB) slave SF-session clock, which contains the addressor signal detector, the clock generator & , besides the first center of the pre-day single-stage output outputs, are connected to the corresponding inputs of the block of the J-ShZh elements, to other corresponding inputs of which under the KJBooeifu Bbtxo i block of the definition of the synchronization depth, the prerequisites The last and the last one, who received the podkvvog cheyy to the inputs of the first aneMeH fa ШШ, jump the output of the clock generator. And in {pulses it is connected to the counting input of the clock clock counter, and vxpjB (it detected the address address 91 tKtpm / A times; the output of the block | F9Tors was connected to the second input of the synchronization unit and the sync element and the output of which is connected to the corresponding input of the B-doc element of the I-ShSH, and the outputs of the block for determining the synchronization depth are connected to the inputs of the SH-element, while the output of the block of the I-SH-elements is connected to the stop input of the start-stop Trägger 2.

However, the devices have low noise immunity.

The purpose of the invention is to improve the synchronization stability without reducing the noise immunity of synchronizing data sessions.

 is achieved by the fact that in, the start / stop clock of the slave station sessions, containing the Address signal detector, clock generator and the start / stop trigger connected in series, the clock counter count and the decoder unit, the corresponding bit outputs of which, except the first and second to last bit outputs, are connected to the corresponding entrances

a block of elements AND-OR, to other corresponding inputs of which is under-. The outputs of the synchronization depth determination unit are turned on, the last but one and the last outputs of which are connected to the inputs of the first element OR, and the output of the clock generator: pulses are connected to the counting input

clock counter, and the output of the address signal detector to the first bit output of a block of its ratios are connected respectively to the first and second inputs of block 6 for determining the synchronization depth, entered the second and third OR elements, the delay block and the And element, to the first second and to the third inputs of which pores are, respectively, the output of the address signal detector, the penultimate output of the synchronization depth block and the penultimate of the SRI bit output of the decoder block, and the output of the AND element connected to the input of the block delays and the first input of the BTopforo, the IZH element, to the second input of which the output of the block of elements is connected, I-IZH, and the output of the delay block is connected to the first input of the third element OR, to the second of which the output of the detector of the address signal is connected, while the second and The third ICH elements are connected respectively & to the stop and start input f of the start-stop trigger, and the output of the first OR element is connected to the corresponding input of the I-IC block.

Fig. 1 shows a structural electrical circuit of the start-stop chronizer of the slave station sessions; ya fig. 2 - diagrams explaining his work.

The start / stop clock of the slave station contains: 1 address signal detector, start / stop trigger 2, 3 clock pulses, 31 pulses, 4 clock pulses counter, decoder block 5, synchronization depth determination block 6, AND 7 block of elements the first, second and third elements OR 9-11, delay unit 12, terminal installation; data transmission 13, interface system 14, radio channel 15. The start-stop clock of the slave station sessions works as follows. In the initial state, the start / stop trigger 2 is in the stop state, the 4 clock pulse counter is zeroed and held in the zero state by a signal from the stop output of the old timer trigger 2, on the bit outputs of the decoder block 5 / session work cycle signal are missing. This condition of the chronizer corresponds to the wake-up mode of the waiting (duty) reception. The first address signal of the master station, received from the detector 1 of the address signal at the start input of the trigger trigger 2 via the third element OR 11, starts the chronizer, the 4 clock pulse counter begins to count as follows: the pulse of the generator 3 clock pulses, and the block 5 decoder generates operating cycles for data transmission terminal 13 and for the interfaced system a) I 14. Simultaneously, the synchronization depth determination unit 6 starts to work, the count counts the number of address signals received from; Detecting the 1 st address signal during the first operating cycle of the communication session — the receive cycle — determines the required time to reset the stagtop trigger 2 to the standby receive mode and sends a signal to the input of the corresponding AND element of the 7-AND-OR block, to another input the signal of one of the working cycles from the corresponding output of the bit output of block 5 decoders, after which the signal from the output of block 7 of the I-IL element through the second element of SH 10 10 start-stop trigger 2, and the entire chronism Torr, are translated in Hell conductive standby receive mode. If a reset is to be made at the beginning of the working cycle of the conjugated system, such a reset is not performed, and the signal of the corresponding synchronization depth from the output of the synchronization depth block 6 (block 6 for determining the synchronization depth is made in the form of sweat, therefore, connected start pulse counter with decoders, register and the element OR-NOT) and the signal of the working cycle of the conjugated system from the penultimate bit output of the block 5 of the decoders are fed to the second and third inputs, element 8, the first input of which connected to the output of the detector 1 address signal. If the phaser start of the chroniser is correct, from the true address signal of the master station, but in the reception cycle by the synchronization depth unit 6, the small synchronization depth is determined due to the omission of private address signals (for example, during link fades or if there is any organized interference), Then the working cycle of the matching system will be completed, thus increasing the synchronization stability of the associated system. A reset to the standby mode is provided. by applying the corresponding signal of the synchronization depth to the proper input of the block 7 of the elements I-ISC. If the phase start is not correct, from a false address signal, then the true address signal arriving during the operating cycle of the adjoining system (Fig. 2 a, b) through the first input of the And 8 element will first reset Start Stop 2 and reset the counter of 4 clocks through. the second element OR 10 (Fig. 2c), and then with some delay set by the delay unit 12, will re-enable Start-Stop trigger 2, and with it the entire clock through the third element IGSch 11 (Fig. 2d), i.e. boo-. The chronizer restarts and the new cycle of sessions begins, starting with the receive cycle (Fig. 2e). This is similar to the normal start of a clock, waiting for standby reception, so that the interfacial synchronization interference does not deteriorate. The delay in the delay block 12 is necessary to prevent the imposition of the table and start-up restart pulses, its value is At where is the duration of the start-up pulse (Fig. 20, d). IfC Т T, where T is the duration of the data receive cycle, which is almost always the case (or it can be provided by highlighting the leading edge of the start pulse), then the restart delay on & 4 does not affect the timing accuracy. Since the signal of the working clock of the contact system is not applied to the block of the I-ILY elements, the number of elements is AND in this block, 626 where nf is the number of bit outputs of the decoder block 5, since the AND-OR block is also not available and the signal from the first bit output of the block 5 is the decryption of rators. Thus, the start-stop chronizer of the slave station sessions, by introducing a specific waiting mode without stopping the chroniser, allows stable synchronization of both data transmission sessions and sessions of the associated systems, for example, in the combined inter-flight trajectory measurement and data transmission systems.

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Claims (1)

START-STOP CHRONIZER OF 'SLAVE STATIONS SESSIONS, containing an address signal detector, clock pulses and consecutively connected start-stop trigger, clock pulse counter and decoder unit, the corresponding bit outputs of which, except the first and penultimate bit outputs, are connected to the corresponding inputs of the AND-AND element block to the other corresponding inputs of which the outputs of the unit for determining the Depth of synchronization are connected, the penultimate and last outputs of which are connected to the first OR element, moreover, the output of the clock generator is connected to the counting input of the clock counter, and the detector output of the address signal and the first bit output of the decoder unit are connected respectively to the first and second inputs of the block for determining the synchronization depth, and with the fact that, in order to increase the stability of synchronization without reducing the noise immunity of the synchronization of data transfer sessions, the second and third OR elements, a delay unit, and the And element are introduced into it, to the first, second and the third inputs of which are connected respectively to the output of the detector of the address signal, the penultimate output of the block for determining the depth of synchronization and the penultimate bit output of the decoder unit, and the output of the And element is connected to the input of the delay unit and the first input of the second OR element, the second input of which is connected to the output of the And OR, and the output of the delay unit is connected to the first input of the third OR element, to the second input of which the output of the address signal detector is connected, while the outputs of the second and third electronic OR elements are connected respectively to the stop and start inputs of the start-stop trigger, and the output of the first OR element is connected to the corresponding input of the block of I-IPI elements. 1125702