RU63957U1 - SYSTEM FOR CHECKING THE KNOWLEDGE OF USERS OF AUTOMATED SYSTEMS OF A UNIFIED TRAINING CENTER - Google Patents

Abstract

The invention relates to computer technology, in particular, to a system for testing the knowledge of operators of automated systems of a single training center. The technical result is to increase the accuracy of the system by using multicriteria parameters to identify and correct errors. The technical result is achieved by the fact that the system contains a selection block for the base address of the control test, a control block for sampling the data of the control tests, a block for controlling the time periods for presenting test tasks, a memory block, a unit for identifying user responses, a block for selecting signs of received answers, and a unit for generating final estimates. 7 ill.

Description

The invention relates to computer technology, in particular, to a system for testing the knowledge of operators of automated systems of a single training center.

Known systems that could be used to solve the problem [1, 2].

The first of the known systems comprises a computing unit connected to functional input and logical processing input units, the outputs of which are connected to a memory unit, a display unit connected to the computing unit and to the decision unit [1].

A significant drawback of this system is its limited functionality, due to the fact that the description of input situations during training and quality control of knowledge is possible only in the space of a limited number of attributes, which leads to low efficiency of its use and low accuracy of assessing the quality of knowledge.

Another system is known that contains student data reception units, the outputs of which are connected to a memory unit and to a data processing unit, a time interval selection unit, the outputs of which are to a student responses evaluation unit, to a memory unit and to a data processing unit, the outputs of which are connected to one the inputs of the switching unit of the data output channels, the other inputs of which are connected to the time interval selection unit, and the outputs are the outputs of the system [2].

The last of the above technical solutions is closest to the described.

Its disadvantage lies in the low accuracy of identifying the quality of knowledge of ACS operators, due to the lack of the ability to control knowledge according to the multicriteria parameters used in the description of input situations in the space of functional features.

The purpose of the invention is to improve the accuracy of the system by using multicriteria parameters to identify and correct errors.

This goal is achieved by the fact that in the system containing the selection block of the base address of the control test, the information and synchronization inputs of which are the first information and synchronization inputs of the system, while the first information input of the system is intended for

receiving identification numbers of control tests, and the first synchronizing input of the system is designed to receive signals for entering identification numbers of control tests into the selection block of the base address of the control test, a memory block whose output is the first information output of the system intended for issuing tasks of control tests to automated workstations of operators , a unit for identifying user responses, one information input of which is connected to the output of a memory block, another information the ion input of the user response identification block is the second information input of the system designed to receive the operator response codes to the questions of control test tasks, and one synchronizing input of the user response identification block is the second synchronizing input of the system designed to receive the signals of entering the operator response codes to the questions of control tasks tests to the unit for identifying user responses, and the unit for generating final assessments, the group of outputs of which is I, as a group of evaluation outputs of the system, introduced a control test data selection control unit, the information input of which is connected to the information output of the control test base address selection selection block, and the first synchronizing input of the control test data selection control block is connected to the synchronizing output of the control test base address selection block, the address output of the control unit for the selection of data of control tests is connected to the address input of the memory block, the first synchronizing output of the block control data sampling control tests connected to the data read input

a memory block, and a second synchronizing output of the control test data sampling control unit is connected to a clock input of the user response identification unit, a time control unit for submitting test tasks, one information input of which is connected to a second information output of the control test data sampling control unit, and another information input of the block control of time periods for presenting test tasks connected to the information output block selection base address of the control test, and the first synchronizing input of the control unit for selecting data of control tests is connected to the first synchronizing output of the unit for identifying user responses, while one output of the control unit for selecting data of control tests is the first signal output of the system designed to give a signal about the end of work with tasks of the control test, and connected to the installation input of the control unit for the selection of data of control tests and with the synchronizing input of the unit for forming the final estimates, the input of which is connected to the second synchronizing output of the user response identification block, and the other output of the control test data sampling control unit is connected to the second synchronizing input of the control test data sampling control unit, and a feature selection block of received answers, the information input of which is connected to the information output of the response identification block users, the first synchronizing input of the selection block of signs of received responses is connected to the first synchronizing output ohm response identification block

users, the second synchronizing input of the selection block of signs of received answers is connected to the second synchronizing output of the block of identification of responses of users, the installation input of the block of selection of signs of received answers is connected to the first output of the control block for selecting data of control tests, the first and second control inputs of the block of selection of signs of received answers are the first and the second control inputs of the system, designed to set the operating mode of the system, while the information output d of the selection block of signs of the received answers is the second information output of the system intended for issuing the correct answers to the operator’s workstations, the first synchronizing output of the selection block of signs of the received answers is connected to the second synchronizing input of the block for monitoring the time periods for submission of test tasks, and the signal outputs of the selection block signs of the received responses are the second and third signal outputs of the system, respectively, designed to issue chi signals of confirmation of the correct answers and error messages of operators.

The invention is illustrated by drawings, where Fig. 1 is a structural diagram of a system, Fig. 2 shows an example of a specific structural embodiment of a selection block of a base address of a control test, Fig. 3 shows an example of a specific constructive execution of a control unit for selecting data of control tests, in Fig. 4 shows an example of a specific constructive implementation of the control unit for temporary periods of presentation of test tasks, figure 5 shows an example

specific constructive implementation of the unit for identifying user responses, Fig. 6 shows an example of a specific constructive implementation of the block for selecting features of the received answers, Fig. 7 shows an example of specific constructive execution of the unit for forming final estimates.

The system (Fig. 1) contains a block 1 for selecting the base address of the control test, a block 2 for controlling the selection of data for the control tests, a block 3 for controlling time periods for presenting test tasks, a memory block 4, a block 5 for identifying user responses, a block 6 for selecting signs of received answers, a block 7 formation of final assessments.

Figure 1 shows the first 10 and second 11 information inputs of the system, the first 12 and second 13 synchronizing inputs of the system, the first 14 and second 15 control inputs of the system, as well as the first 16 and second 17 information outputs, synchronizing the 18 outputs of the first 19 and second 20 signal output and group 21-23 evaluation outputs.

Block 1 (figure 2) selection of the base address of the control test contains registers 30, 31, a decoder 32, a memory unit 33, made in the form of read-only memory, elements 34-36 And, elements 37 and 38 of the delay. The drawing also shows information 40 and synchronizing 41 inputs, as well as information 42 and synchronizing output 43 outputs.

Block 2 (Fig.3) control data sampling of control tests contains a counter 45, adder 46, element 47 OR, elements 48-50 delay. The drawing shows the information input 52, the first 53 and second 54 synchronizing and counting 55 inputs, as well as the first 56 and second 57 information, and the first 58 and second 59 synchronizing outputs.

Block 3 (figure 4) control of time periods for presenting test items contains a comparator 65, triggers 66, 67, elements 68, 69 AND, element 70 OR, elements 72, 73 delays. The drawing shows the first 75 and second 76 information inputs, the first 77, second 78 and third 79 clock inputs, as well as the first 80 and second 81 outputs.

Block 4 (figure 1) memory is made in the form of random access memory having an address input 61, input 62 for reading test data and output 63.

Block 5 (figure 5) identification of user responses contains registers 84, 85, comparator 86, triggers 87, 88, elements 89, 90 AND, element 91 OR, elements 92, 93 delay. The drawing shows the first 96 and second 97 information inputs, the first 98 and second 99 clock inputs, as well as information 100, the first and second clock outputs.

Block 6 (Fig.6) selection of signs of the received answers contains triggers 105, 106, elements 107-109 AND, a group of 110 elements AND, element 111 OR. The drawing shows the information input 114, the first 115, the second 116 and the third 117 clock inputs, the first 118 and the second 119 control inputs, as well as the information 120, the first 121, the second 122 and the third 123 clock outputs.

Block 7 (Fig.7) contains a counter 125, a decoder 126, elements 127-129 I. The drawing shows a counting 130 and synchronizing 131 inputs, as well as a group of 21-23 evaluation outputs.

An automated workstation for controlling the knowledge of ACS operators includes a terminal having a screen for

play test tasks [3], and the keyboard of a personal computer.

Management of knowledge control is carried out from the server of the automated control system (not shown in the drawing).

Before the start of the next cycle of the system from the server to the input 10 of the system receives the code number of the control test, the tasks of which must be presented to the operator. This code through the input 40 of block 1 enters the input of the register 30 and is recorded in it by the server synchronizing pulse coming from the input 12 of the system through the input 41 of the block 1 to the synchronizing input of the register 30.

In addition, one of the two system operation modes is set from the server: the knowledge control system of the ACS operator or the self-control mode, implemented using the trigger 105 of block 6, controlled from the inputs 14 and 15 of the system.

If the trigger 105 of block 6 is in the initial ("zero") state, then it implements the knowledge control system of the ACS operator, in which the trigger 105 low potential from the direct output blocks the circuit issuing "tips" through elements 107, 108 and a group of elements 110 I.

If the trigger 105 of block 6 is transferred to a single state, this will mean the system is operating in the self-monitoring mode of ACS operators. At the same time, with a high potential from a single output of the trigger, the elements 107, 108 and the group of elements 110 And will be open for issuing prompts on the display screen.

The code of the control test number from the output 42 of the register 30 is fed to the input of the decoder 32, which decrypts this code and one of its outputs generates a high potential that opens one of the corresponding elements 34-36 I.

In parallel with this, the server clock signal from the input 41 of block 1 is delayed by the delay element 37 (for the time of the decryptor 30 operation and code setting in the register 30) and from the output of the delay element 37, having passed through one of the 34-36 AND elements open at the second input, to the read input of a fixed memory cell of a read-only memory 33.

In a fixed cell of this memory block, a code message is stored, the structure of which has the following form:

THE CODE THE CODE Starting address of the first test task The total number of tasks in this control test

The contents of the fixed cell of the ROM 33 are read into the input of the register 31, where it is entered by the synchronizing pulse coming from the output of the delay element 38 to the synchronizing input of the register 31. In this case, the code of the initial address of the first test task from the output 42 of block 1 through the input 52 of block 2 goes to one the input of the adder 46, and the code of the total number of tasks in this control test through the input 76 of block 3 is fed to one input of the comparator 65 of block 3.

The synchronizing pulse from the output of the delay element 38 of block 1 after entering the code in the register 31 through the output 43 of block 1 and the input 53 of block 2 passes through the element 47 OR to the input of the delay element 48, where it is delayed by the response of the register 31 and setting the code at the input of the adder 46 . Given that at this point the counter 45, the output of which is connected to another input of the adder 46, is in the initial "zero" state, then at one input of the adder there will be the contents of the code of the starting address of the first test task, and at the other input - the code corresponding to null value.

The synchronizing pulse supplied to the synchronizing input of the adder 46 from the output of the delay element 48, the output code 56 of the adder 46 will be fixed code initial address of the first test task, which should be displayed on the display screen of the ACS operator.

The same pulse delayed by the delay element 49 during transients in the adder 46, through the output 58 of block 2 is fed to the input 62 of the reading of the memory unit 4 and reads the contents of the cell with the starting address to the output 63 of the block 4.

The structure of the read code message is as follows:

THE CODE THE CODE Test Content The correct answer to the questions of the test task

After reading the contents of the test task is displayed on the display screen of the ACS operator through the system output 16, and the code for the correct answer to the questions of the test task from the output 63 of block 4 through the input 96 of block 5 goes to the information input of register 84, where they are entered by the synchronizing pulse coming from the output 59 block 2 (after a delay for the time of reading the code from the memory block 4 and installing it on the inputs of the register 84) through the input 98 of the block 5 to the synchronizing input of the register 84 ..

The ACS operator selects one of the answer options that he considers preferable and types the corresponding sign or symbol on the keyboard. The response code through the input 11 of the system and through the input 97 of block 5 enters the information input of the register 85, where it is entered by the synchronizing pulse from the input of the system 13 through the synchronizing input 99 of block 5.

At the same time, the same clock from the input 99 of block 5 is delayed by the delay element 92 for the time the code is written to register 85 and then fed to the synchronizing input of the comparator 86, the information inputs of which are sent to the codes of registers 84 and 85.

If the codes of the registers match, then the output 137 of the comparator 86 generates a signal that sets the trigger 87 to a single state. At which the high potential from the direct output will open the element 89 And, to the other input of which a synchronizing pulse is received from the output of the delay element 93, which delays the synchronizing pulse for the duration of the operation of the comparator and trigger 87.

The pulse from the output of the delay element 93 passes element 89 AND, and firstly, through the element 91 OR is delayed by the element 94 delay for the duration of the pulse and goes to the installation inputs of the triggers 87, 88, setting or confirming their initial state.

Secondly, the synchronizing pulse from the output of element 89 AND passes to the output 101 of block 5, from where it goes to input 115 of block 6 and then passes element 107 And, open by the high potential of trigger 105 in self-monitoring mode, to output 122 and then to signal output 19 system as a signal "CORRECT RESPONSE".

In addition, the synchronizing pulse from the output 101 of block 5 is fed to the input 78 of block 3, where the OR element 70 passes and is fed to the synchronizing input of the comparator 65, which compares the readings of the counter 45 of block 2 with a given number of tasks in the control test.

Considering the fact that the counter code 45 of block 2 is currently less than the number of tasks in the control test, a signal is generated at the output 136 of the comparator 65, setting the trigger 67 to a single state, in which the And element 69 will be open at one input. At the same time, the synchronizing pulse from the output of the OR element 70 is delayed by the element 72 for the duration of the comparator 65 and the trigger 67, and passes through the open element 69 AND to the output 81 of block 3, from where it, firstly, enters through the input 54 of block 2 both to the counting input of the counter 45, increasing its readings by one, and through the OR element 47 and the delay element 28 to the synchronizing input of the adder 46, fixing the fact of increasing the code at the address input of the memory unit by one.

Next, the following test task and the corresponding code of the correct answer are read into the register 84 of block 5 in the manner described above.

If, in the process of selecting the answer to the next test task, an incorrect answer is entered into the register 85, then this fact will be recorded by the comparator 86, by generating a signal at the output 138, which will set the trigger 88 to a single state. As a result of this, the 90 And element will be opened. The pulse from the output of the delay element 93 will pass through the 90 And element to the output 102 of block 5 and, firstly, through the input 116 of block 6 to the single input of the trigger 106, fixing the fact of error and opening one by one input elements 110 I.

Secondly, from the input 116 of block 6, it will pass through the And element 108, opened by the high potential of the trigger 105 in the self-monitoring mode, to the output 123 as a signal “WRONG RESPONSE”.

Considering that in the self-monitoring mode the trigger 105 opens 110 And elements on the second input, from the output of block 100 5, the correct answer code through the 110 And groups will be displayed on the display screen in the form of the “Correct answer” information.

Thirdly, the pulse from the output 102 of block 5 is fed to the input 130 of block 7 and then to the counting input of the counter 125, which counts the number of errors. The readings of the counter 125 are fed to the input of the decoder 126, which, depending on the readings of the counter 125, opens one of the elements 127-129 I. The outputs of the corresponding elements 127-129 And the possible knowledge assessments are issued that are output to the outputs 21-23 of the system.

Fourthly, the same pulse from the input 116 of block 6 is fed to one input of the 109 And element, the state of which is determined by the potential from the inverse output of the trigger 105. If at the moment the trigger 105 is in the self-monitoring mode, then the low potential from the inverse output of the trigger 105 is an element 109 And the continuation of the cycle of presenting the next test task will be closed only after re-entering the now correct prompted answer in register 85 of block 5.

In this case, the comparator 86 will record the fact of comparing the codes of the registers 84 and 85, so that the trigger 87 with high potential will open the element 89 And, through which the clock pulse from the output of the delay element 93 passes to the output 101 of block 5 and then through the input 78 of block 3 and element 70 OR to the clock input of the comparator 65

The comparator 65 generates a signal at the output 136, which sets the trigger 67 to a single state and thereby opens the element 69 I. As a result, the clock pulse from the output of the delay element 72 passes through the element 69 AND to the output 81 of the block 3 and then to the input 54 unit 2, where it passes both to the counting input of the counter 45, and through the OR element 47 and the delay element 48 to the synchronizing input of the adder 8.

Next, the following test task and the corresponding correct answer code are read in the manner described above to block 5.

If trigger 105 was in its initial state, which corresponds to the system operating mode in control mode, then element 109 I will be opened with high potential from the inverse output.

As a result of this, the pulse from the input 116 of block 6 passes through element 109 AND to the output 121 of block 6, from where it goes to the input 79 of block 3, where it passes the element 70 OR and goes to the synchronizing input of the comparator.

Given that the number of completed test tasks is much less than their specified number, block 3 again gives a signal at output 81, from where it again goes to input 54 of block 2.

The described process will continue until the comparator 65 of block 3 fixes the equality of codes at its inputs. As soon as the comparator 65 fixes the equality of the codes of the counter 45 of block 2 and the register 31 of block 1, then at the output of the comparator 137 a signal sets the flip-flop 87 to a single state, in which the flip-flop 87 opens the 89 And element with a high potential, to the other input of which there is a synchronizing pulse with output element 93 delay.

The synchronization pulse passes through the 89 And element, and through the output 101 of block 5 it enters, firstly, both output 18 as a signal to the server about the completion of the presentation of test tasks, and the installation inputs of block 2, returning the counter and adder to its original state.

Secondly, the same pulse through the input 131 of block 7 goes to the inputs of the elements 127-129 I, and passes to the output of the one that will be opened by the corresponding output of the decoder 126, which determines the type of evaluation that the tested operator deserves according to the results of work.

Thirdly, the same pulse through the input 117 of block 6 is fed to the input of the OR element 111 and then to the installation input of the trigger 105, setting it to its original state, which corresponds to the knowledge control mode.

Thus, the introduction of new nodes and constructive relationships has significantly improved the accuracy of assessing the knowledge of students in all sections of the studied subject areas.

Sources of information taken into account:

1. US Patent No. 0,005,651 M. cl. G06F 13/40, 13/38, 1992

2. US Patent No. 5129083 M. cl. G06F 12/00, 15/40, 1992 (prototype).

Claims (1)

A knowledge testing system for operators of automated systems of a single training center, which contains a selection block for the base address of the control test, the information and synchronizing inputs of which are the first information and synchronizing inputs of the system, while the first information input of the system is designed to receive identification numbers of control tests, and the first synchronizing input of the system it is intended for receiving signals of entering identification numbers of control tests into the selection block of the base addresses of the control test, a memory block, the output of which is the first information output of the system, intended for issuing tasks of control tests to automated workstations of operators, a user response identification unit, one information input of which is connected to the output of the memory block, another information input of the user response identification block is the second information input of the system, designed to receive codes of operator answers to questions of tasks of control tests, and one sync the lowering input of the user response identification block is the second synchronizing input of the system intended for receiving signals of entering the operator response codes to the questions of the control test tasks into the user response identification block, and the final assessment generation unit, the output group of which is a group of evaluation system outputs, characterized in that a control unit for the selection of control test data was introduced into the system, the information input of which is connected to the information output of the selection block the base address of the control test, and the first synchronizing input of the control unit for sampling the data of the test tests is connected to the synchronizing output of the selection block of the base address of the control test, while the address output of the control unit for selecting the data of the test tests is connected to the address input of the memory unit, the first synchronizing output of the control unit for sampling data control tests is connected to the input of data reading of the memory block, and the second synchronizing output of the control unit for fetching control data of tests is connected to the clocking input of the unit for identifying user responses, a unit for monitoring time periods for submitting test tasks, one information input of which is connected to the second information output of the control unit for sampling data of test tests, another information input for controlling time periods for presenting test tasks is connected to the information output of the selection unit the base address of the control test, and the first clock input of the control unit for the selection of data of control tests connected to the first synchronizing output of the user response identification block, while one output of the control test data sampling control unit is the first signal output of the system designed to give a signal about the end of work with control test tasks, and connected to the installation input of the control test data sampling control unit and with a synchronizing input of the final grading unit, the counting input of which is connected to the second synchronizing output of the response identification unit users, and the other output of the control test data sampling control unit is connected to the second synchronizing input of the control test data sampling control unit, and a feature selection selection block, the information input of which is connected to the information output of the user response identification unit, the first synchronizing input of the feature response selection block connected to the first synchronizing output of the user response identification block, the second synchronizing input of the selection block the signs of the received responses is connected to the second synchronizing output of the user response identification block, the installation input of the selection block of the signs of the received answers is connected to the first output of the control block for selecting data of control tests, the first and second control inputs of the selection block of the signs of received answers are the first and second control inputs of the system to set the operating mode of the system, while the information output of the selection block of the signs of the received answers is WTO the first information synchronizing output of the system for selecting signs of received answers is connected to the second synchronizing input of the unit for monitoring the time periods for presenting test tasks, and the signal outputs of the block for selecting signs of the received answers are the second and third signal system outputs, respectively, designed to issue confirmation signals of correct answers and messages about ibkah operators.