RU1793552C - Device for determination of boundaries of digital information packets - Google Patents

Abstract

The invention relates to the transmission of digital information and may find application in communication systems with temporary channel multiplexing and in serial interfaces for transmitting data with relative phase shift keying. The aim is to increase the accuracy of identifying parcel boundaries. The device comprises a clock generator 1, a trigger 2, a block 3 for selecting the edges of the pulses, the first, second and third delay elements 4-6, the first and second counters 7, 8 pulses, a memory unit 9, an OR element 10, the first and second registers 11 , 12, the first and second digital comparators 13, 14, the first and second elements AND 15, 16. The device provides high accuracy of highlighting the borders of the gutter. 3 IL, -: - -; ..,.;.:

Description

f

3

- HOZ

Start-e

 YU

you ate

The invention relates to the transmission of digital information and may find application in communication systems with temporary channel multiplexing and in serial interfaces for transmitting data with relative phase shift keying.

A device for extracting signal bursts is known, comprising a clock, first and second counters, a memory unit, a first register, first and second elements I. A disadvantage of this device is the low accuracy of determining the information transfer rate with relative phase shift keying (OFM). since during OFM, fragments of a digital sequence that are different in structure (sequence 1 and O in the general data stream) during transmission at different speeds can have an identical form, which causes a decrease in the purity of the selection of the borders of the signals.

Closest to the proposed is a device for highlighting the boundaries of the packages of digital information containing a clock, pulse counter, memory unit, trigger and elements.

A disadvantage of the known device is the low accuracy of the allocation of the boundaries of the packages of digital information with relative phase shift keying (OFM). This drawback is due to the fact that, with ordinary FM, information on the duration of the elementary package (and, accordingly, on the information transfer rate) can be extracted from any two adjacent time intervals limited by three phase transitions, but for OFM: there is no such strict correspondence. The reason here lies in the specificity of the signal with the OFM, in which the appearance of an entire sequence of identical, elementary premises may not lead to a change in the phase of the current oscillation, i.e., the analysis of any two adjacent time intervals limited by three phase transitions cannot be adequate true baud rate; ;;;;:; ::; ;. ; ..; :.:

The purpose of the invention is to increase the accuracy of the allocation of boundaries of packages of digital information.

In FIG. 1 is a structural electrical diagram of a device; Fig. 2 is an example of a specific implementation of a pulse edge extraction unit; in FIG. 3 - time diagrams explaining the operation of the device.

A device for extracting the boundaries of digital information packages contains a clock generator 1, a trigger 2, a block 3 for selecting the edges of the pulses, elements

4 .... 6 delays, first and second counters 7 and 8, memory unit 9, OR element 10, first and second registers 11 and 12. first and second digital comparators, AND elements 15 and 16.

The pulse edge extraction unit 3 (Fig. 2) comprises single vibrators 17, 18 and an OR element 19.

Timing diagrams (Fig. 3) reflect: .- -. . .-:.

a) source digital information;

b) clock pulses from the output of the generator 1 clock pulses;

c) an enable signal at the control input of the pulse edge extraction unit 3; ; . ; ..

d) digital information with OFM at the input of the device;

e) pulses at the output of the pulse edge extraction unit 3;

e) changing the binary code at the outputs of the first counter 7;

g) the output signal of the element And 15;

h) the signal at the output of the element And 16;

i) code changes at the outputs of the register

eleven; ,:.;: ;;. D ..; .-,;:, .. ..

j) changing the binary code at the outputs of the second counter 8;

k) the overflow signal of the second counter 8; - - -. -. ...- ..

m) change the speed code at the outputs of the register 12 (at the output of the device).

In the device (Fig. 1), the output of the clock generator 1 is connected to the counting output of the first counter 7, the information outputs of which are connected to the address inputs of the memory unit 9. The transfer output of the first counter 7 is connected to

account authorization entry. The input of the device is connected to the input of the pulse edge extraction unit 3, the control input of which is connected to the output of the trigger 2. The inverse output of the trigger 2 through the first delay element 4 is connected to the input of the OR element 10 and to the input of zeroing the counter 7 and directly to the first inputs of the first and second elements And 15 and 16. The outputs of the memory unit 9 are connected to the information inputs of the register 11 and the first groups of inputs of the first

and second digital comparators 13 and 14,

the second groups of inputs which are combined with the inputs of the register 12 and connected to the outputs of the register 11. The outputs of the first and second, digital comparators 13 and 14, respectively, are connected to the second inputs of the elements And 15 and 16, the outputs of which are connected, respectively, with the second input of the element OR 10 and the clock counter 8 input. Counter overflow output 8 is connected to the write control input of register 12 and through the third delay element 6

- with the reset input of trigger 2. The output of the AND element 15 is connected to the control input of the register 11. The output of the OR element 10 is connected to the reset input of the trigger 2,

. A device for highlighting the boundaries of the packages of digital information operates as follows,

In the initial state, the trigger 2 is zeroed, and there is no trigger enable signal for the pulse edge extraction unit 3, at the output of which there are no pulse signals. Counter 7 is full and the maximum possible binary code is present at its output. Register 11 is kept in a zero state, as is counter 8.

When the device is started, the pulse that appears at the S-input of trigger 2 puts it in a log state. 1 (Fig. 3c), which enables the operation of the pulse edge extraction unit 3. The digital sequence arriving at the input of the device (Fig. 3, a) after the OFM has the form indicated in Fig. 3 g. Block 3 of the selection of the fronts of the pulses upon the appearance of each phase transition in the sequence g (Fig. 3) forms a short odd at the output. a night pulse whose duration is much shorter than the duration of the time interval between adjacent phase transitions at the highest transmission rate from the a priori of the set speed set. Thus, at the output of the pulse edge extraction unit 3, an impulse sequence of the form e is formed (Fig. 3). . The operation of the device is based on the fact that the time interval characterizing the transmission rate of digital information with OFM is the time interval between phase transitions caused by the appearance of a combination of symbols of type 00 in the digital sequence. The essence of the operation of the device is to search for such a characteristic interval and static accumulation the number of its occurrences in the observation time interval.

Previously, before the operation of the device, the number of possible values of the digital information transmission rates is established, the binary code of the digital information transmission rate is determined and entered into the memory unit 9. In this case, the address code of such a code corresponds to a binary code for the duration of the characteristic interval. After the device is started by pulses from the output of the block 3, the edges of the pulses delayed in time of the delay elements 5 are reset to counter 7. The clock is reset.

pulses (b, Fig. 3), coming from the output of the Tenerator 1 clock pulses to the counting input of the counter 7, fills the time interval between two adjacent

pulses from the output of the pulse edge extraction unit 3. Thus, immediately before the appearance of each subsequent reset pulse, a binary code is generated at the outputs of counter 7, proportional to the duration between adjacent phase transitions in the input digital sequence, i.e., a duration-to-code conversion is performed (Fig. 3e).

5 The received code is the address code of the memory unit 9, at the outputs of which, in accordance with the address, the information transmission speed code, the code of the speed of input to the digital comparators

0 13 and 14 is compared with the speed code stored in register 11. The signal at the output of digital comparator 13 appears if the code from the output of memory unit 9 is larger than the code stored in register 11.

5 i.e., if the next time interval characterizes a higher transmission rate than the previous one. The signal at the output of the digital comparator 14 appears if the codes from the outputs of the memory unit 9

0 and register 11 are equal. The output signals of the digital comparators are gated by pulses from the output of the pulse edge extraction unit 3, and at the output of the element And 15 an impulse sequence of the form g is formed (Fig. 3), and at the output of the element And the 16-form is z (Fig. 3).

When a pulse appears at the output of the AND t5 element, a new speed code is entered in register 11, which is most likely than

0 previous (Fig. 3, and), and also counter 8 is reset, counting the number of occurrences of the most likely speed code in the observation interval.

When a pulse appears at the output of element And 16, the contents of register 11 are not changed, and the contents of counter 8 are increased by one (Fig. 3, k), i.e., the number of occurrences of the same speed codes in the observation interval is counted.

Thus, the device provides the selection and storing of the desired speed code and calculates the number of occurrences of the code of the expected desired speed of 5 at a given interval.

As soon as the number of occurrences of the speed code exceeds a threshold value, a signal appears at the output of counter 8 (Fig. 3, l), according to which the code stored in register 11 is transferred to register 12 (Fig. 3, m),

the output of which, therefore, is the code for the desired digital information transfer rate. The same signal (Fig. 3, l) triggers trigger 2, which practically turns off the device; In the event of a need for a redefinition of the speed code, trigger 2 is switched by the start signal to the log state. 1, and the operation of the device is repeated in the order described above ...

To prevent false capture of the device, a counter for the duration of the observation interval / cyclic and counting pulses, for example, arriving at its counter input from the output of the clock generator 1, can be used. At the same time, the output of the indicated counter corresponding to the end of the observation interval can be connected to the reset input of trigger 2 through an additional device. Formula of the invention A device for extracting the boundaries of digital information packages containing a clock generator, a first pulse counter, a memory unit, a first register, a trigger , the first and second elements AND, characterized in that, in order to improve the accuracy of the selection of the boundaries on the basis of, introduced the block selection of the edges of the pulses, the first, second and third delay elements, the element OR, second the first register, the second pulse counter, the first and: the second digital comparators, to the first groups of inputs of which the outputs of the memory block are connected, the outputs of the memory block are connected to the information inputs of the first register, the outputs of which are connected to the information inputs of the second register, the outputs of which are the device outputs, and to the second groups of inputs of the first and second digital comparators, the outputs of which are connected to the first inputs of the first and second elements And, respectively, to the second inputs of which and the input of the second element e delays connected to the output pulse edges separating unit having an information input. is the input of the device, while the output element is OR, to the second input of which the output of the delay element 6 should be connected (while, accordingly, the connection between the delay elements b and the input

trigger 2 reset should be excluded). Thus, the device provides a determination of the transmission rate of digital information received in the OFM code. : -, j.:-- :. .

The use of the device provides an increase in the degree of autonomy of digital information receiving units and serial interface units, and determines the creation of unified tools,

with automatic tuning to the required operating mode, which significantly reduces the amount of control information on setting up peripheral devices for a specific operating mode.

 ;;; u., ..,.; . .

the clock pulse generator is connected to the clock input of the first pulse counter, to the zero input of which the output of the second delay element is connected, and the overflow output of the first pulse counter is connected to the overflow input of the first pulse counter, connected to the resolution enable input of the first pulse counter, whose information outputs are connected to the address the inputs of the memory unit, and the direct and inverse outputs of the trigger are connected respectively to the control input of the block of selection of the edges of the pulses and the first delay element is to the input of resetting the first register and the first input of the OR element, the output of which is connected to the input of zeroing the pulse counter, the output of the 1st bit of which is connected to the recording control input of the second register and through the third delay element to the input of zeroing the trigger, input set to 1 which is the start input of the device, while the output of the first AND element is connected to the control input of the second register, and the second input of the OR element, and the output of the second AND element is connected to the clock input of the second o pulse counter.

§ lllllinillilllillllinillllflillllllllininllllHIllllllllillllllHIIIIIIIIIIIIIIIIIIIKIIIIIIIIII

  i - -: -U- ;:; - -U .----- g - ;: fi n fi fl

3L

3

N fl

LL

/

US

II p. 1

P P

pa