SU1141583A1 - Start-stop reception device - Google Patents

Abstract

A START-UP COMPOSITION DEVICE, containing a pulse generator, an AND block, a trigger, the first and second AND elements, an OR element and a counter, the counting input of which is connected to the output of the first AND element, the first input of which is combined with the first input of the trigger By the fact that, in order to increase its noise immunity in case of edge distortions, two ring registers, a trigger block, the third element I, an inverter and a code generator, whose outputs are connected to the information inputs of the counter, are entered into it ka, the pre-recording input of which is combined with the clock input of the first ring register and with the first output of the second ring register, the second and third outputs of which are connected respectively to the inputs of the OR element and to the combined inputs of the second and third elements AND, the installation input of the first ring register with the output of the second element And, the first, second and third outputs of the first ring register are connected respectively to the second input of the trigger, to the combined first inputs of the trigger block and ne In the first inputs of the AND block, the combined second inputs of the AND block are connected to the output of the third element AND, the outputs of the AND block are connected to the second inputs of the trigger block, the codes of which and the fourth output of the first ring switch are the output of the device. the counter is connected to the second input of the third element And through an inverter with the second input of the second element AND, the output of the element OR is connected to the second input of the first element AND, inverse 4; i and the direct outputs of the trigger are connected respectively It is connected with the input of the second ring register and with the control input of the pulse00 generator, whose output is connected to the clock input BTojJoro of the ring register, and the third input of the second element AND is connected to the second output of the first ring register.

Description

V. The invention relates to telecommunications and can be used to receive start-stop signals. A start-stop device is known that contains a distributor connected to a block of AND elements, a sequentially included element OR and three ger, as well as a master oscillator, a frequency divider and a drive Cl3. However, this device has low noise immunity in the presence of edge distortions, since, when registering single powders, it leads to discrete integration over the entire length of parcels, including their boundaries, where there are high distortions. The closest to the invention to the technical essence is a start / stop receiving device comprising a pulse generator, an AND block, a trigger, a first and second AND elements, an OR element and a counter, the counting input of which is connected to the output of the first And element, the first input of which is combined with the first the trigger input and is the device input, a serial-to-parallel code converter, a decryption and printing unit, and delay elements t2j. In the known device, it uses the principle of matching the frequency with the duration of a single interval of the received signal. At the same time, during the operation of a single element of a digital start-stop signal, the pulse generator produces 2-1 pulses, where K / 2 is an integer. The determination of the moment of termination of a single element of the start-stop signal is made after the counter has registered a specified number of pulses. This leads to a reduction in noise immunity, especially in the presence of edge distortions. The purpose of the invention is to increase the noise immunity at edge distortions. To achieve the goal, the start / stop receiver contains a pulse generator, an AND block, a trigger, first AND second AND elements, an OR element and a counter, the counting input of which is connected to the output of the first AND element, the first input of which is combined with the first trigger input and the device input, two ring registers, a trigger block, a third element And an inverter, and a code generator, whose outputs are connected to the information inputs of the counter, whose pre-recording input is combined with the clock input of the first first ring register and the first output of the second ring register, the second and third outputs of which are connected respectively to the inputs of the OR element and to the combined inputs of the second and third elements AND, the installation input of the first ring register connected to the output of the second element AND, first, second and second the third outputs of the first ring register are connected respectively to the second input of the trigger, to the combined first inputs of the trigger block and the first inputs of the AND block, the combined second inputs of the AND block ineny with the output of the third AND gate, the outputs of the AND unit connected to the second inputs of the trigger block, and which outputs the fourth output of the first annular register are merged and output devices | the output of the counter is connected to the second input of the third element I and through an inverter with the second input of the second element I, the output of the element SH is connected to the second input of the first element I, the inverse and direct trigger outputs are connected respectively to the installation input of the second ring register and to the control the input of the pulse generator, the output of which is connected to the clock input of the second ring register, the third input of the second element And is connected to the second output of the first ring register. Introduction of the proposed blocks and links allows to increase the pseh-resistance of the start-stop signals reception in the presence of edge distortions by discrete integration of the signal in the area free from edge distortions. The drawing shows a functional diagram of the device. Start-stop receiver includes a generator 1 pulses, a block of 2 elements And, trigger 3, first 4 and second 5 elements And, element 6 OR and a counter 7, the counting input of which is connected to the output of the first element 4 And, the first input of which is combined with the first input of the trigger 3 and is with the input of the device. Device

also contains two ring registers 8 and 9, a block of 10 flip-flops, a third element 11 I, an inverter 12 and a code generator 13, the outputs of which are connected to the information inputs of the counter 7, the pre-recording input of which is combined with the clock input of the first ring register 8 and with the first the output of the second ring register 9, the second and third outputs of which are connected respectively to the inputs of the element 6 OR and to the combined inputs of the second 5 and third 11 elements AND, and the installation input of the first ring register 8 is connected to the output of the second el 5 and the first, second and third outputs of the first ring register 8 are connected respectively to the second input of the trigger 3, to the combined first inputs of the 10 trigger block and the first inputs of the 2 And block, the combined second inputs of the 2 And block are connected to the output of the third element 11 I. The outputs of block 2 of the elements AND are connected to the second inputs of the block of 10 flip-flops, the outputs of which and the fourth code of the first ring register 8 are the output of the device, while the output of the counter 7 is connected to the second input of the third element 11 And through and Ver | torus 12 to a second input of the second AND element 5, an output of OR 6 is connected to the second input of the first. element 4 And, the inverse and direct outputs of the trigger 3 are connected respectively to the installation input of the second ring register 9 and to the control input of the pulse generator 1, the output of which is connected to the clock input of the second ring register 9, and the third input of the second element 5 I is connected the second output of the first ring register 8.

Start-stop receiver device operates as follows.

In the initial state, trigger 3 at the second input is a single logical level from the first output; the first ring register 8 is set to zero. At the outputs of the second ring register 9 and the counter 7, there is a zero logic level. When a single signal appears at the input of the device, the trigger 3 goes into one state, in which, by switching on the generator 1 of pulses at the clock input of the second ring register 9, a sequence of clock pulses appears. The frequency of the pulse generator 1 is such that for a period of a separate element of the input signal, the specified number of pulses is lost.

Under the action of a clock sequence in the second ring register 9, the signal logical 1 is advanced from the first bit in after

blowing When it appears at the first output to the counter 7, a constant code is written from the generator 13 of the code through the inputs of the preliminary recording, and the logical unit 1 is shifted from the first output of the first ring register 8 to the second code. At the output of the OR element 6, connected by its inputs to the odd bits of the second ring register 9, a packet of a predetermined number of pulses appears. At the first element 4 I, the input signal is gated, and the single value of the input signal causes the appearance of pulses at the output of the first element 4 I. The constant number recorded in counter 7 is such that the arrival of more pulses to its counting input contained in the packet of pulses at the output of element 6 OR, causes the appearance of a single logical level at the output of the counter 7. With a smaller number of pulses at the output of the counter 7, the | Zero logic level remains. Thus, the information value of the separate element of the input signal is determined by the state at output 1 of the counter 7.

In the event that the first signal arriving at the input of the device was not recorded as a single element (false start), the pulse from the output of the second element 5 was returned to the initial state at the installation input. At the same time, the signal of the logical unit at its first output causes the return of trigger 3, and to the zet and the second ring register 9 to the initial state. In the case of fixation of the starting element, the return of these elements to the initial state does not occur.

I The value of a separate element of the input signal is determined by the third element 11 And the pulse from the third output of the second ring register 9 and through one of the elements of the block 2 elements AND is entered into the corresponding cell of the 10 trigger module connected to the output of the device. After all the signal elements are received, the first ring register 8 returns to the initial state, thereby causing the reset of the trigger 3 and the creative register 9 to 9. The decision on the value of the signal element is made depending on the number of pulses ma. the counting input of the counter 7. For deciding the ambiguity when making a decision, the generated packet of pulses must contain an odd number of pulses. In this case, the decision on the unit value of the signal element is made if the number of pulses received at the input of the counter 7 is greater than or equal to fl + 1 2

. The number d that is written

in counter 7 before receiving each element of the signal is determined by the equality

where m is the number of bits of counter 7, not less than). So, for p 5, 1P "3,.

Thus, the proposed device gates the input signal and then discretely integrates the gating result. At the same time, at the borders of elements where there are large distortions, signal gating is not performed due to the displacement of packets of gating pulses relative to the borders of the signal elements, which increases the accuracy of integration and increases the noise immunity of receiving start-stop signals.

Practical testing of the device showed its high noise immunity under the conditions of influence of edge distortions and distortions such as crushing.

Claims (1)

. A START-STOP RECEIVER, containing a pulse generator, a block of AND elements, a trigger, a first and second AND element, an OR element and a counter, the counting input of which is connected to the output of the first And element, the first input of which is combined with the first input of the trigger and is the device input, characterized in that, in order to make it noise-resistant during edge distortions, two ring registers, a trigger block, a third AND element, an inverter and a code generator, the outputs of which are connected to the counter information inputs, are introduced into it d pre-recording of which is combined with the clock input of the first ring register and with the first output of the second ring register, the second and third outputs of which are connected respectively to the inputs of the OR element and to the combined inputs of the second and third elements And, and the installation input of the first ring register is connected to the output of the second element And, the first, second and third outputs of the first ring register are connected respectively to the second input of the trigger, to the combined first inputs of the trigger block and the first inputs of the bl As AND elements, the combined second inputs of the AND element block are connected to the output of the third AND element, the outputs of the AND element block are connected to the second inputs of the trigger block, the outputs of which and the fourth output of the first ring register are combined and are the device output, while the counter output is connected to the second input of the third element And and through the inverter with the second input of the second element And, the output of the OR element is connected to the second input of the first element And, the inverse and direct outputs of the trigger are connected respectively to the installation input in orogo annular register and control instructions input of the pulse generator, whose output is connected to the clock input of the second ring register, and the third input of the second AND element is connected to the second output of the first annular register.