RU1781648C - Outfit for testing of logic printed circuit units - Google Patents

Abstract

The device contains five triggers, delay element 3, element And 8, integrator 12, element 2 AND-OR-NOT 17, element AND 18, 19 „20 and 21, register 22, the first and second keys 23 and 24, nine input buses (5, 7, 9, 13,14, 15, 25, 26, 27), two output buses (2, 16) with corresponding connections 1 il

Description

The invention relates to techniques for building blocks of electrical equipment, in particular to devices for controlling logic blocks, and may find application for software control of printed circuit boards

A device for monitoring logic blocks containing an error signal driver connected to the output bus of the control signal and to the output bus of the test signal

A disadvantage of the known device for monitoring logic blocks is a significant error in the result of monitoring

It is also known a device for monitoring logic blocks containing a first trigger, a direct output connected to the first output bus of the device, a second trigger, the input t is connected to the first of the input buses of the device, the third trigger, the input of which is connected to the second input bus of the device, the fourth and p the first triggers, the inverter, the delay element and the second output bus of the device

The disadvantage of such a device for controlling logic blocks is limited functionality, since it does not provide

impacting the selected contacts of the controlled logic block with a high-frequency code sequence, the possibility of creating a cyclic code sequence of arbitrary duration on the input contact of the controlled logic block and the possibility of using a unified control block to set the impact on the input contacts of the controlled logic block and receiving response signals from the output contacts of the controlled logic block

An object of the invention is to expand the functionality of a device for monitoring logic blocks.

To this end, to the device for monitoring logic blocks, comprising a first trigger, a direct output connected to the first output bus of the device, a second trigger, the input of which is connected to the first of the input buses of the device, a third trigger, the input of which is connected to the second input bus of the device, the fourth and fifth triggers, an inverter, a delay element, and a second output bus of the device, an AND element, an AND-OR-NOT element, a first, second, third and fourth AND-NOT elements are introduced,

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register, and the first and second keys, and the output of the 2AND-OR-NOT element is connected to the input of the first trigger, the direct output of which is connected to the other input of the third trigger, the output of which is connected to the first input of the first AND-NOT element, the second input of which is connected to the output of the fourth trigger, the third input is with the third input bus of the device, and the output of the first element is NOT connected to the second output bus of the device and the first output of the second key, the second output of which is connected to the first output of the first key, the second output of which is connected n with the first input of the register, the second input of which is connected to the fourth input bus of the device and with the first input of the AND element, the second input of which is connected to the fifth input bus of the device, and the output - with the first input of the element 2 AND OR NOT, the second input of which is connected to the input of the fourth trigger and the sixth input bus of the device, the third input of the 2I-OR-NOT element is connected to the seventh input bus of the device, and the fourth to the second output bus of the device, the other input of the first trigger is connected to the output of the delay element, the input of which is connected connected to the second input bus of the device, the first input of the second AND element is NOT connected to the direct output of the second trigger, the other input of which is connected to the input of the fifth trigger and the output of the third AND element, the first input of which is connected to the third input of the second AND element and the fifth input bus of the device, the second input bus is connected to the second input of the second AND-NOT element, the output of which is connected to another input of the fourth AND-NOT element, the second input of which is connected to the eighth input bus of the device, and the output to the third input th register fourth input coupled to an output of the inverter whose input is connected to the inverted output of the fifth flip-flop fifth input register is connected to the sixth input bus device connected to the output of register joint pin key and the other input of the fourth flip-flop is connected to the ninth input bus device

One of the possible variants of the proposed device for controlling logic blocks is shown in the drawing.

The device comprises a first trigger 1, a direct output connected to the first output bus 2 of the device, which is the output bus of the control signal, a second trigger 3, the input of which, which is the inverse input of the unit, is connected to the first input bus of the device, which is the first input control signal bus, third trigger 5, the input of which, which is a synchronization input, is connected to

the second input bus b of the device, which is the first input control bus, the fourth and fifth flip-flops 7 and 8, the inverter 9, the delay element 10, the second output bus 11 of the device, which is the output

0 the test signal bus, and the third, fourth, fifth, sixth, seventh, eighth and ninth input buses of the device 12, 13, 14, 15, 16, 17 and 18, while the third, fourth, fifth and sixth input buses 12 ,

5, 13, 14, and 15 of the device are, respectively, the input bus of the presence of influence, the second input bus of control, the input bus of the commands and the input data bus, and the seventh eighth and ninth input buses

0 16, 17 and 18 of the device, respectively, the input bus of the polling signal, the input bus of the clock signal and the input bus of the receive signal

The device also contains an element And

5 19 element 2 AND-OR-NOT 20, first, second, third and fourth elements AND 21, 22 23 and 24, register 25 and first and second keys 26 and 27 The output of element 2 AND-OR-NOT 20 is connected to the input of the first trigger 1,

0 the direct output of which is connected to another input of the third trigger 5 The direct output of the third trigger 5 is connected to the first input of the first AND-NOT 21 element, the second input of which is connected to the direct output

5 of the fourth trigger 7. The third input of the first element AND-HE 21 is connected to the third input bus 12 of the device. The output of the first element AND-HE 21 is connected to the second output bus 11 of the device and the first

0 by the output of the second key 27. The second output of the second key 27 is connected to the first output of the first key 26, the second output of which is connected to the first input of the register 25, which is the input of the sequential record. The second input of the register 25, which is the write control input, connected to the fourth input bus 13 of the device and to the first input of the element And 19 The second input of the element And 19

0 is connected to the fifth input bus 14, and the output is connected to the first input of the 2-OR-NOT element 20. The second input of the 2-OR-NOT element is connected to the input of the fourth trigger 7, which is an information input, and

5 by the wire of one of the pairs of the sixth input bus 15 of the device The third input of the element 2 AND-OR-NOT 20 is connected to the seventh input bus 16 of the device, and the fourth input is connected to the second output bus 11 of the device Another input of the first trigger 1 is

the inverse input of the installation is zero, connected to the output of the delay element 10, the input of which is connected to the second input bus 6 of the device. The first input of the second AND-NOT element 22 is connected to the direct output of the second trigger 3. The other input of the second trigger 3, which is the inverse input of the zero setting, is connected to the input of the fifth trigger, which is the inverse input of the zero setting, and with the output of the third AND element NOT 23. The first input of the third AND-NOT 23 element is connected to the third input of the second AND-NOT 22 element and to the fifth input bus 14 of the device. The second input bus 6 of the device is connected to the second input of the third AND-NOT element 22, the output of which is connected to another input of the trigger trigger 8, which is the inverse input of the unit setting. The direct output of the fifth trigger 8 is connected to the first input Ohm of the fourth AND-NOT element 24. The second input of which is connected to the eighth input bus 17 of the device, and the output to the third input of register 25, which is an inverse synchronization input. The fourth input of the register 25, which is the enable input, is connected to the output of the inverter 9, the input of which is connected to the inverse output of the fifth trigger 8. The fifth input of the register 25, which consists of parallel recording inputs, is connected to the wires of all pairs of the sixth input bus 15 of the device . The output of the register 25. The output of the register 25 is connected to the combined second output of the second key 27 and the first output of the first key 26 and the other input of the fourth trigger 7. Which is an inverse synchronization input, is connected to the ninth input bus 18 of the device. In this case, the second input of the third element AND 23 is connected to the seventh input bus 16 of the device.

The operation of the proposed device for monitoring logic blocks is as follows.

If the input contact of the monitored logic unit is connected to the device, the fourth trigger 7 is set to a single state by a signal on the ninth input bus 18 of the device. In this case, the fourth trigger 7 controls the output state of the first NAND element 21. The single state of the fourth trigger 7 corresponds to the open state of the output of the first NAND element E 21, and the zero state of the fourth trigger 7 corresponds to the currentless high-impedance state of the output of the first element AND NOT 21.

If the signals coincide on the fourth and fifth input buses 13 and 14 of the device, the element 2-OR-NOT gates the signal.

coming from one of the pairs of the sixth input bus 15 of the device. As a result, the first trigger 1 is set to a single state at a low signal level and not 5. is set at a high signal level.

The signal supplied through the second input bus 6 of the device, provides a rewrite of the state of the first trigger 1 in

0 third trigger 5 and reset the first trigger 1 through the delay element 10.

According to the signal supplied to the third input bus 12 of the device, through the first element AND-NOT 21 to the second output bus

5 11 device receives a test signal.

If the output contact of the controlled logic unit is connected to the device, then the signal on the ninth input bus 18

0 of the device, the fourth trigger 7 is set to a zero state; which corresponds to a currentless high-impedance state of the output of the first AND-NOT element 21. The signal from the output of the first AND-NOT element

5 21 goes to the second output bus 11 and to the element 2I-OR-NOT 19, through which it passes a signal on the seventh input bus 16 of the device to the first trigger 1, acting on the first output bus

0 2 devices.

If the input of the controlled logic block must be affected by a high-frequency code sequence, then the fourth trigger

5 7 are set to the zero state, which enables the third trigger 5 and the first AND-21 element to be disconnected from the second output bus 11 of the device. In this case, the second key 27 is set to the closed state, providing the connection of the output of the register 25 to the second output bus 11 of the device. Recording a high-frequency code sequence via the sixth input bus 15

5 of the device, the register 25 is produced by a signal supplied to the fourth input bus 13 of the device.

The signal supplied through the first input bus 4 of the device is supplied to the second

0 trigger 3, acting on the second AND-NOT element 22, to which signals are also fed through the second and fifth input buses 6 and 14 of the device. Upon conjunction, the second AND-HE 22 element 5 activates the fifth trigger 8. The signal from the inverse output of the fifth trigger 8 passes through the inverter 9 to the fourth input of the register 25, which is switched to the open state upon the output. The signal from the direct output of the fifth trigger 8 is supplied

to the fourth AND-NOT element through which the high-frequency clock signal passing through the eighth input bus 17 passes to the third input of the register 25. When signals are received via the fifth and seventh input buses of the device, the third AND-NOT element 23 provides a reset of the second and fifth triggers 3 and 8, which causes the register 21 to transition to a high impedance exit state.

If it is necessary to supply a cyclic code sequence to the input of the controlled logical unit, the first and second keys 26 and 27 are closed, which ensures the connection of the output of register 25 to the second output bus 11 of the device and the connection of the output of register 25 with its first input. When a high-frequency clock signal arrives at the third input of register 25, a test signal is output in the form of a high-frequency cyclic sequence to the second output bus 11 of the device. The length of the entire sequence is determined by the time interval from the leading edge of the signal arriving on the second input bus 6 of the device and the leading edge of the signal arriving on the seventh input bus 16 of the device

Claims (1)

SUMMARY OF THE INVENTION A device for monitoring printed logic blocks, comprising a first trigger, a direct output connected to the first output bus of the device, a second trigger whose inverse input is connected to the first input control bus of the device, a third trigger, the C-input of which is connected to the second input bus of the device , fourth and fifth triggers, inverter, delay element, first and second output buses of the device, characterized in that. in order to expand the functionality, an AND element, an AND-OR element - NOT, a first, second, third and fourth AND-NOT element, a register, a first and second keys are introduced into it, and the output of an AND-OR-NOT element is connected to an input the first trigger, whose direct output is connected to the input of the third trigger, the output of which is connected to the first input of the first AND-NOT element, the second input of which is connected to the output of the fourth trigger, the third input to the second device bus, and the output of the first AND-NOT element is connected to the second output bus of the device and the first output of the second key whose second output is connected to the first output of the first key, the second output of which is connected to the first input of the register, the second input of which is connected to the third input of the device and to the first input of the AND element, the second input of which is connected to the fourth input bus of the device, and the output - to the first input of the 2AND-OR-NOT element, the second input of which connected to the direct input of the fourth trigger and the fifth input bus of the device, the third input element 2I-OR-Н Е is connected to the sixth input bus of the device, and the fourth to the second output bus of the device, the inverse input of the first trigger is connected to the output of the element delays, the input of which is connected to the seventh input the device bus and the C-input of the third D-trigger, the first input of the second AND element is NOT connected to the direct output of the second trigger, whose inverse input is connected to the inverse input of the fifth trigger and the output of the third AND-NOT element, the first input of which is connected to the third input of the second AND-NOT element and the fourth input bus of the device, the sixth input of which is connected to the second input of the third the NAND element, the output of which is connected to the direct input of the fifth trigger, the direct output of which is connected to the first input of the fourth NAND element, the second input of which is connected to the eighth input bus of the device, and the output - to the third input of the register, the fourth input which is connected to the output of the inverter, the input of which is connected to the inverse output of the fifth trigger, the fifth input of the register is connected to the fifth input bus of the device, the output of the register is connected to the combined terminals of the keys, the C-input of the fourth D-trigger is connected to the ninth input bus of the device. 8 f7