JP2003035750A - Semiconductor integrated circuit testing apparatus, testing board, and semiconductor integrated circuit testing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To test a semiconductor device speedily. SOLUTION: The semiconductor integrated circuit testing apparatus for testing the operation of a plurality of semiconductor devices X in parallel by supplying a testing signal to the plurality of semiconductor devices X simultaneously packages a plurality of IC sockets 4 for fitting the semiconductor devices X, and comprises a testing board 1 where an opening/closing switch 6 is provided in the middle of a signal line L for transmitting the testing signal to the IC socket 4, and a line selection control section 3d for controlling the opening/closing switch 6.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit test device, a test board, and a semiconductor integrated circuit test method.

[0002]

2. Description of the Related Art As one type of semiconductor integrated circuit test equipment,
There is a test burn-in system. This test burn-in apparatus is an apparatus for performing a burn-in (aging) of a semiconductor device (device under test) to be tested in an operating state under a predetermined temperature environment, and making a pass / fail judgment. In burn-in using such a test burn-in device, a plurality of semiconductor devices are mounted on a test burn-in board (test board) via IC sockets, and a plurality of such test burn-in boards are stored in the test burn-in device. To be tested. Each semiconductor device is electrically connected to the test burn-in device via a circuit pattern formed on the test burn-in board, receives power from the test burn-in device and various test signals, and outputs the test signals. Output a response signal to the test burn-in device.

[0003]

By the way, the test burn-in board performs a parallel test on a plurality of semiconductor devices by supplying a test signal to each of the mounted semiconductor devices in parallel. That is, each signal line formed on the test burn-in board is connected in parallel to a plurality of semiconductor devices. For this reason, the driver of the test burn-in device that supplies a test signal to a plurality of semiconductor devices via such a signal line has an input capacitance of the input terminal of each semiconductor device and an input capacitance of each terminal of the IC socket. A relatively large capacity load consisting of an electric capacity and an electrostatic capacity proportional to the wiring distance of the signal line and the like is connected.

Since such a large capacitive load distorts the test pulse signal so as to prolong the rise time and fall time of the test pulse signal output from the driver,
Restricting the supply of high frequency test pulse signals to semiconductor devices. Although it is possible to realize a high-speed test of a semiconductor device by increasing the frequency of the test signal, in the conventional test burn-in board, since the maximum frequency of the test signal is limited by the large capacitive load, High speed test could not be realized.

The present invention has been made in view of the above-mentioned problems, and aims at the following points. (1) Realize high-speed testing of semiconductor devices. (2) A high-speed test of a semiconductor device is realized without significantly changing the configuration of the test board. (3) One test board is used by switching between a relatively low speed test and a relatively high speed test.

[0006]

In order to achieve the above object, the present invention relates to a semiconductor integrated circuit test apparatus according to a first aspect.
In the semiconductor integrated circuit test apparatus for simultaneously testing a plurality of semiconductor devices (X) by simultaneously supplying a test signal to the plurality of semiconductor devices,
A test board in which a plurality of IC sockets for mounting semiconductor devices are mounted, and circuit opening / closing means is provided in the middle of a signal line for transmitting a test signal to the IC sockets;
A means including a line selection control section for controlling the circuit opening / closing means is adopted.

As the second means relating to the semiconductor integrated circuit test apparatus, the means for providing the circuit opening / closing means for each test group in the first means is adopted.

As a third means relating to the semiconductor integrated circuit testing device, in the above first or second means, in the case where the semiconductor device is a digital integrated circuit operating on the basis of a clock, a signal line for transmitting the clock is used. A means of providing a circuit opening / closing means is adopted.

As a fourth means relating to the semiconductor integrated circuit testing device, in any one of the first to third means,
The method applied to the test burn-in system is adopted.

On the other hand, according to the present invention, as the first means relating to the test board, it is housed in the semiconductor integrated circuit test apparatus for simultaneously testing the operation of a plurality of semiconductor devices, and the semiconductor devices are mounted. A test board in which a plurality of IC sockets are mounted and a test signal is supplied in parallel to semiconductor devices mounted in the respective IC sockets, and the test board is provided in the middle of a signal line for transmitting the test signal. A means of providing a circuit opening / closing means is adopted.

As a second means relating to the test board,
The first means employs a means of providing circuit opening / closing means for each test group.

As a third means relating to the test board,
In the first or second means, when the semiconductor device is a digital integrated circuit which operates based on a clock, a means for providing a circuit opening / closing means on a signal line for transmitting the clock is adopted.

As a fourth means relating to the test board,
In any one of the first to third means, the semiconductor integrated circuit testing device is a test burn-in device.

Further, according to the present invention, as a first means relating to the semiconductor integrated circuit test method, a semiconductor integrated circuit test for simultaneously testing a plurality of semiconductor devices in parallel by supplying a test signal to the plurality of semiconductor devices at the same time. In the method, when performing a high-speed test, a signal line for transmitting a test signal is connected / disconnected at a predetermined portion to an IC socket in which a semiconductor device is mounted, and the signal line is connected to a signal line in the undisconnected connection state. Adopt a method of mounting a semiconductor device in each IC socket and performing an operation test

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a semiconductor integrated circuit test device, a test board and a semiconductor integrated circuit test method according to the present invention will be described below with reference to the drawings. The present embodiment relates to a case where the present invention is applied to a test burn-in device.

FIG. 1 is a block diagram of the main part of a test burn-in system according to this embodiment. In this figure, reference numeral 1
Is a test burn-in board (test board), 2 is a connector, and 3 is a control board. The test burn-in board 1 is a relatively large printed board, and a plurality of IC sockets 4 for mounting the semiconductor devices X are mounted on the test burn-in board 1.
Although a small number of IC sockets 4 are illustrated in FIG. 1 for simplification, the actual test burn-in board 1 has, for example, 272 IC sockets 4 mounted thereon. Is a large printed circuit board on which a large number of such IC sockets 4 can be mounted.

On such a test burn-in board 1, a plurality of signal lines L for transmitting various test signals to each IC socket 4 and a power supply line for power supply (not shown).
Are patterned. The signal line L and the power supply line are commonly wired to predetermined terminals of each IC socket 4. For example, the clock input terminal of the IC socket 4 has a clock signal line L for transmitting a clock.
Is wired.

The signal line L for the clock is commonly wired to the clock input terminals of all the IC sockets 4, and therefore the clock is supplied in parallel to the clock input terminals. Further, one ends of the signal line L and the power supply line are connected to an edge connector 5 formed at one end of the test burn-in board 1. The edge connector 5 fits into the connector 2.

Further, an opening / closing switch 6 (circuit opening / closing means) is provided in the middle of the signal line L. The open / close switch 6 is, for example, a relay having a mechanical contact, and connects / disconnects the signal line L based on a drive signal input via the signal line L. An IC directly connected to the edge connector 5 via a part of the signal line L without passing through the open / close switch 6.
A test signal is supplied to the socket 4 regardless of the open / close state of the open / close switch 6, but the IC socket 4 connected to the edge connector 5 via the open / close switch 6
The test signal is supplied only when the open / close switch 6 is closed. That is, the open / close switch 6 limits the IC socket 4 that supplies the test signal.

The connector 2 is fitted to the edge connector 5 and supplies the test signal inputted from the control board 3 to the signal line L and the power source inputted from the control board 3 to the power source line. To supply. The control board 3 generates various test signals and a power supply having a predetermined voltage and outputs the test signals to the test burn-in board 1. The control board 3 includes a driver 3a that buffers the drive signals and outputs the test signals to the test burn-in board 1, drivers 3b and 3c that buffer various test signals and outputs the test signals to the test burn-in board 1, and the test board. It is composed of a control circuit 3d (line selection control unit) for generating a signal and a drive signal.

Next, the test of the semiconductor device X using the test burn-in system thus constructed will be described.

As described above, in the present test burn-in system, the open / close switch 6 supplies the test signal to the IC.
It has a function of limiting the socket 4. By using such a function, when the semiconductor device X is tested at a high speed, the open / close switch 6 is set to the open state by outputting a drive signal from the driver 3a, and the open / close switch for the edge connector 5 is opened. 6 disconnects the signal line L and the IC socket 4 located at the rear stage of the driver 6.
The capacity load of b and 3c is reduced. As a result, a high-speed pulse signal as a test signal can be supplied to the semiconductor device X of the IC socket 4 located in front of the open / close switch 6 with respect to the edge connector 5, and a high-speed test is performed.

In this case, the number of semiconductor devices X that can be tested at the same time is limited, but the semiconductor devices X can be tested faster than before. On the other hand, for such a high-speed test, when the open / close switch 6 is set to the closed state, the test signal can be supplied to all the IC sockets 4, so that the semiconductor devices X are supplied to all the IC sockets 4. Can be implemented and tested. That is,
By properly setting the open / closed state of the open / close switch 6,
It is possible to switch between a high-speed test for a small number of semiconductor devices X and a low-speed test for a large number of devices X.

FIG. 2 is a circuit diagram of the test burn-in board 1'used for testing the memory X '. In this case, a plurality of open / close switches 6a1, 6a2, 6a3 to 6an are inserted in the signal line L'of the clock CLKn having the highest operating frequency. The open / close switches 6a1, 6a2, 6a3 to 6an are provided for each SCAN number set by the SCAN signal SCANAm, that is, for each test group of the memory X '. A test signal is simultaneously supplied to a plurality of memories X'having the same SCAN number to check the operation. In this way, by providing the open / close switches 6a1, 6a2, 6a3-6an for each SCAN number,
The memory X ′ to be tested at high speed can be set in SCAN number units.

Although the present embodiment relates to the case where the present invention is applied to the test burn-in device, the present invention is not limited to the test burn-in device. The present invention can be applied to various test apparatuses that simultaneously test a plurality of semiconductor devices X in parallel. Further, in the above embodiment, the mechanical opening / closing switch 6 is adopted as the circuit opening / closing means, but a semiconductor switch may be used.

[0026]

As described above, according to the present invention,
Connecting and disconnecting a signal line for transmitting a test signal to a respective IC socket in which the semiconductor device is mounted at a predetermined portion, and mounting the semiconductor device in the IC socket connected to the signal line in the undisconnected connection state. As a result, it is possible to reduce the capacitive load caused by the semiconductor device, the signal line, and the IC socket, and therefore a high-speed test of the semiconductor device can be realized.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a main part of a test burn-in device according to an embodiment of the present invention.

FIG. 2 is a circuit diagram of a test burn-in board according to an embodiment of the present invention.

[Explanation of symbols]

1, 1 '... Test burn-in board (test board) 2 ... Connector 3 ... Control boards 3a to 3c ... Driver 3d ... Control circuit (line selection control unit) 4 ... IC socket 5 ... Edge Connector 6, 6a1, 6a2, 6a3 to 6an ...... Open / close switch (circuit open / close means) L, L '... Signal line X ... Semiconductor device X' ... Memory

Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) G01R 31/28 Y

Claims (9)

[Claims] 1. A semiconductor device (X) by simultaneously supplying a test signal to a plurality of semiconductor devices (X).
A plurality of IC sockets (4) in which the semiconductor devices (X) are mounted, and the test signal is transmitted to the IC sockets (4). A test board (1) provided with a circuit opening / closing means (6) in the middle of the signal line (L), and a line selection control section (3d) for controlling the circuit opening / closing means (6). Characteristic semiconductor integrated circuit test equipment. 2. The semiconductor integrated circuit testing device according to claim 1, wherein the circuit opening / closing means (6) is provided for each test group. 3. When the semiconductor device (X) is a digital integrated circuit which operates based on a clock, a circuit opening / closing means (6) is provided on a signal line (L) for transmitting the clock. Item 3. A semiconductor integrated circuit test device according to item 1 or 2. 4. The semiconductor integrated circuit test device according to claim 1, which is applied to a test burn-in device. 5. A semiconductor integrated circuit tester for accommodating a plurality of semiconductor devices (X) at the same time so that the semiconductor devices (X) can be tested simultaneously. A plurality of IC sockets (4) for mounting the semiconductor devices (X) are mounted. A test board for supplying test signals in parallel to the semiconductor devices (X) mounted in the respective IC sockets (4) and transmitting the test signals to the IC sockets (4). A circuit opening / closing means (6) is provided in the middle of the signal line (L)
A test board characterized by the following. 6. The test board according to claim 5, wherein circuit opening / closing means (6) is provided for each test group. 7. When the semiconductor device (X) is a digital integrated circuit operating on the basis of a clock, a circuit opening / closing means (6) is provided on a signal line (L) for transmitting the clock. Item 5. A test board according to item 5 or 6. 8. The semiconductor integrated circuit test apparatus is a test burn-in apparatus for burn-in and operation testing a semiconductor device (X).
7. The test board according to any one of 7. 9. A semiconductor device (X) by simultaneously supplying a test signal to a plurality of semiconductor devices (X).
Is a semiconductor integrated circuit test method for testing a plurality of devices in parallel, and when performing a high-speed test, a signal line (for transmitting a test signal to an IC socket (4) to which each semiconductor device (X) is mounted ( IC connected to the signal line (L) in a connected state in which L) is disconnected and connected at a predetermined portion
A semiconductor integrated circuit test method comprising mounting a semiconductor device (X) in a socket (4) and performing an operation test.