RU1775850C - Pulse shaper - Google Patents

Abstract

A pulse shaping apparatus relates to a pulse technique and may find application in digital transmission systems. An object of the invention is to increase the accuracy of pulse shaping by reducing the effect of load changes on the result of pulse shaping. To this end, in a device containing four transistors 1, 5. 6, 7, resistors 2, 3. 11, 12, 14, 15, 16. 17, 18. 19, 20.31, 32, diodes 4, 8. 9 10, transformer 21, capacitors 27, 28, 29 are introduced. 30. Resistors 13.16, bus U 22.23 are inputs, and bus 26 is the output of the device. 1 ill. 2 26 23 (L 00 eat about

Description

The invention relates to pulsed technology, in particular to pulse shaping devices, and may find application in digital transmission systems.

An object of the present invention is to increase the accuracy of pulse shaping by reducing the effect of load changes on the result of pulse shaping.

The drawing shows a diagram of a device for generating pulses.

The device contains the first, second, third and fourth transistors 1, 2, 3 and 4, the first, second, third and fourth diodes 5, 6, 7 and 8, the first, second, third, fourth, fifth, sixth, seventh, eighth , ninth, tenth, eleventh and twelfth resistors 9. Yu, 11, 12, 13, 14, 15, 16, 17, 18, 19 and 20, the first and second input buses 21 and 22, the output bus 23, the bus 24 power supply and common bus 25. The bases of the first and second transistors 1 and 2, respectively, through the first and second resistors 9 and 10 are connected to a common bus 25. The collectors of the first transistor 1 are connected to one of the terminals of the third p resistor 11 .. The collector of the second transistor 2 is connected to one of the terminals of the fourth resistor 12. The base of the third transistor 3 is connected to the first terminals of the fifth and sixth / resistors 13 and 14. The base of the fourth transistor 4 is connected to the first terminals of the seventh and eighth resistors 15 and 16 The other terminals of the fifth and sixth resistors 13 and 15 are connected to the power bus 24. The cathodes of the first and second diodes 5 and 6 are connected to the bases of the first and second transistors 1 and 2, respectively.

The device also contains a transformer 26, first, second, third and fourth capacitors 27, 28, 29 and 30 and the thirteenth and fourteenth resistors 31 and 32. The first input bus 21 is connected to the cathode of the third diode 7 and to the second output of the sixth resistor 14. The second input the bus 22 is connected to the cathode of the fourth diode 8 and to the second terminal of the eighth resistor 16. The first input bus 21 is connected through the first capacitor 27 to the base of the transistor 2, and through the ninth resistor 17 to the power bus 24. The second input bus 22 is connected through the second capacitor 28 to the base of the transistor 1, and through the tenth resistor 18 to the power bus 24. The anodes of the first and second diodes 5 and b are connected respectively to the anodes of the third and fourth diodes 7 and 8. The anodes of the first and second diodes 5 and 6 are connected respectively through the eleventh and twelfth resistors 19 and 20 with the bus 24

nutrition. The emitters of the first and second transistors 1 and 2 are connected to each other and to a common bus 25. The collectors of the third and fourth transistors 3 and 4 are connected respectively through the thirteenth and fourteenth resistors 31 and 32 with the second terminals of the third and fourth resistors 11 and 12 connected with the primary winding of the transformer 26. Secondary winding

0 of the transformer 26 is connected to the output bus 23 by one terminal and a common bus 25 by the other terminal. The emitters of the third and fourth transistors 3 and 4 are connected to the power bus 24,

5 The principle of operation of a pulse shaping apparatus is as follows.

Digital pulse sequences are received on the first and second input

0 buses 21 and 22 from the TTL outputs of open collector circuits, for which the ninth and tenth resistors 17 and 18 serve as load resistors. These pulse sequences correspond to

5 positive and negative pulses of a bipolar sequence of pulses supplied to the output bus 23. To such a bipolar sequence of pulses are hard

0 requirements for duration, amplitude and shape, as well as for the identity of pulses of positive and negative polarity. In addition, as a rule, a condition of agreement with

5 load.

A feature of the device is that the first, second, third and fourth transistors 1, 2, 3 and 4 operate in a key mode. The latter allows comparatively simple formation of output pulses in the output bipolar sequence of pulses of the required amplitude and duration supplied to the output bus 23, as well as the necessary

5, the identity of the pulses of positive and negative polarity, since the scatter of the parameters of the first, second, third, and fourth transistors 1, 2, 3, and 4 operating in the key mode does not affect the output parameters, which depend mainly on the supply voltage and load resistance, the output impedance of the device is determined by pairing the third, fourth, thirteenth and

5 of the fourteenth resistors 3. 12, 31 and 32 to the primary winding of the transformer 26 through the currently open transistors.

If there are no pulses on the first and second input buses 21 and 22, then from that

and ten resistors 17 and 18 are supplied with a logical TTL level O, opening the third and fourth transistors 3 and 4, which allows the base current to flow through the sixth and eighth resistors 14 and 16, respectively. In this case, the first and second transistors 1 and 2 are closed, since current switches made on the eleventh resistor and the first and third diodes 5 and 7 and on the twelfth resistor 20 and the second and fourth diodes 6 and 8 deprive these transistors of the base currents.

If pulses of logic level 1 TTL are present on the first input bus

21and are absent on the second input bus

22, the second and third transistors 2 and 3 are closed, and the first and fourth transistors 1 and 4 are open and saturated. At the same time, the beginning of the primary winding of the transformer 26 is connected through the third resistor 11 to the common bus 25, and its end - through the fourteenth resistor 32 to the power bus 24. As a result, a current appears in the primary winding of the transformer 26, causing a pulse of negative polarity to form on the output bus 23.

If pulses are present on the second input bus, 22 and are absent on the first input bus 21, then the first and fourth transistors 1 and 4 are closed, and the second and third transistors 2 and 3 are open and saturated. At the same time, the beginning of the primary winding of the transformer 26 is connected through the thirteenth resistor 31 to the power bus 24, and its end through the fourth resistor 12 to the common bus 25. As a result, a current appears in the primary winding of the transformer 26, causing a pulse of positive polarity to form on the output bus

23. Thus, when each

pulse on the first input bus 21, a negative polarity pulse is formed on the output bus 23, and when each pulse appears on the second input bus

22, a positive polarity pulse is generated on the output bus 23, which enables the formation of a bipolar pulse train on the output bus 23.

The first, second, third and fourth capacitors 27, 28, 29 and 30 serve to accelerate the process of opening and closing the first, second, third and fourth transistors 1, 2, 3 and 4, and the first, second, fifth and seventh resistors 9, 10.13 and 15 to bypass their emitter junctions.

The device can work when received on its first and second input buses 21 and 22 of inverse pulse sequences,

The technical and economic efficiency of the device is associated with an increase in the accuracy of pulse formation by reducing the effect of load changes on the result of pulse formation.

Claims (1)

The claims The device for generating pulses containing four transistors, the base of the first and second transistors respectively connected through the first and second resistors to a common bus, and the collectors, respectively, with one of the terminals of the third and fourth resistors, the base of the third and fourth transistors respectively connected to the first conclusions the fifth and sixth resistors and the seventh and eighth resistors, other terminals of the fifth and seventh resistors are connected to the power bus, four diodes, cathodes of the first and second diodes are connected to the basics of the respective first and second transistors, a transformer, ninth, tenth, eleventh and twelfth resistors, input and output buses, characterized in that, in order to increase the accuracy of pulse shaping by reducing the effect of load changes on the result of pulse shaping, four capacitors and thirteenth and fourteenth resistors, the first and second input buses being connected respectively to the cathodes of the third and fourth diodes, to the second terminals of the sixth and eighth resistors, through the second and second capacitors - with the bases of the first and second transistors, through the third and fourth capacitors - with the bases of the third and fourth transistors, and through the ninth and tenth resistors - with the power bus, the anodes of the first and second diodes are respectively connected to the anodes of the third and fourth diodes, and through the eleventh and twelfth resistors - with a power bus, the emitters of the first and second transistors are connected to a common bus, the collectors of the third and fourth transistors are connected respectively through the thirteenth and fourteenth ezistory with second terminals of the third and fourth resistors connected to the primary winding of the transformer, the secondary winding of which one terminal is connected to the output bus and the other output - to the common bus, the emitters of the third and fourth transistors are connected to the power bus.