KR900007603B1 - Integrated circuit chip assembly - Google Patents

Abstract

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Description

Integrated circuit chip assembly

The field name relates to integrated circuit technology.

Background of the Invention

In order to meet the ever-increasing demands of computational and data processing power in terms of processing speed and memory capacity, computer designs have evolved in the direction of compact components and assembly devices. IB M Journal of Research and Development May 1982 Volume 26 NO. 3, pp. PP 297-305. F. Attention has been paid to the number of so-called package levels (packages are defined as structurally similar parts or assemblies) as "Advanced Printed Circuit Board Design for High Efficiency in Computers" published by Bossier et al.

In addition, attention has been paid to how the parts and assemblies are interconnected. That is, the MBM Journal of Research and Development, May 1982, volume 26 NO. 3, W. in PP 287-296. Hoh et al. "Thin Film Modules as Highly Efficient Semiconductor Packages" describe multi-chip modules of silicon chips attached to thin film transfer lines. One of the proposals to be an efficient device in silicon technology is avoided. It has been proposed by Crenac et al., And the technique was published in 1968 9 Will volume ED-15, NO. 9, PP. A large-scale integrated wafer-chip assembly, published in 660-663. Here the silicon chip is bonded "face down" on the silicon wafer.

Summary of the Invention

Integrated circuit chips are assembled on a single crystal carrier substrate and electrically coupled to each other. Silicon is a suitable substrate material.

In accordance with one concept of the present invention, the positioning is made such that at least one chip on the carrier substrate is directed to a beveled sidewall of the at least one chip that is juxtaposed with a wall in the carrier substrate such as a wall, groove or opening in the carrier substrate. .

The substrate and chip materials may be crystallographically compatible, and single crystal materials are essential and it is essential that they be the same. The inclined walls are crystallographically produced by anisotropic etching and the etching acts at different rates in different crystallographic directions. Thus, an angle different from 90 ° is formed between the etched surface and the surface that is not exposed to etching. Typically, the chip arrangement includes a match pressure between two or four pairs of inclined surfaces when the chip is placed in a groove or four side wall.

The electrical connection can be affected by the point of contact on the inclined wall. In a variant, the connection can be formed by one or multiple conductive passages that analyze the chip and the substrate.

In another concept of the invention, the assembly is made with at least one integrated circuit chip whose surface is activated with respect to the top surface of the wafer. The conductive pad is located in the center of the top surface of the upright chip. All parts except the top of the wafer and the periphery of the attached chip are coated with an etch resistant layer. In addition, each chip is etched to form inclined ends between the active regions of the device. By using standard integrated circuit fabrication techniques, conductive patterns are formed on the top surface of the wafer or connected to at least one inclined end or to conductive terminals located along the periphery of the wafer for connecting the chip pads to pads on other chips. To be formed. The fabricated wafer sized assembly can thus be processed and fabricated in a conventional manner (eg, encapsulated) and used as a monolithic component exhibiting good performance and cost saving properties. In another embodiment of the invention, one chip of the type described above is installed on each side of the wafer. In addition, the connection is made between chips provided on two surfaces of the wafer. In this way, particularly compact and dense wafer size assemblies are produced.

According to another concept of the invention the assembly is made with at least one chip installed on the bottom of the wafer. The conductive pad is located in the center of the chip upper surface. The wafer is formed to form an inclined wall passage opening coinciding with the center portion so as to coincide with the conductive pad of each upstanding chip. By using standard integrated circuit fabrication techniques, the conductive pattern is formed by overlapping the top surface of the wafer and connects the conductive pads of each chip to another chip or to another chip on a sloped wall or around the terminals. It is formed by connecting to a conductive terminal on the upper surface of the wafer. Thus, the wafer-sized assembly is reprocessed in a conventional manner (eg, encapsulation) and thus can be used as a monolithic component for inclusion in an electronic system.

details

The following terms are used remarkably in the description of the present invention, and the meanings of the terms are as follows.

The substrate is a material body having a surface that can act as a support for the material object, which material material is insufficiently fixed in the absence of the support, and their spatial arrangement depends on the presence of the support. The substrate is typically relatively thin compared to the planar size.

The carrier substrate and chips are mutually defined as substrates of relatively large and small dimensions so that a plurality of chips can be attached to the carrier substrate.

Integrated circuits are miniaturized electrical circuits supported by a substrate.

Selective etching or crystallographic anisotropic etching is essentially a chemical process that removes surface material at different rates depending on the crystallographic orientation in the single crystal material.

In view of positioning the chip on the carrier substrate to facilitate electrical interconnection of the circuit on the chip and the substrate, selective etching may be applied to at least one portion of the substrate material and at least one portion of the chip material. The portion is designated herein as a body portion, and the substrate and chip may include portions different from the body portion, such as, for example, devices, circuits, and accessory parts.

1 is the same as when the chip 1, the integrated circuit 2 with the contact pads 3, the insulating layer 4, for example consisting essentially of Ti-Pd-Au or Cr-Cu-Au alloy The metal contact 5, the solder metal 6, on which wettable soldering takes place is shown. The sloped portion of the chip 1 preferably has a depth that is at least 5.1 × 10 ⁻³ (2 mils).

FIG. 2 is used as an electrical ground electrode and is heavily doped on the surface of the carrier substrate 7, the insulating oxide layer 8, the power supply metal conductor 9, the Y-signal metal conductor 10, and the X-signal metal The conductor 11 stripe metal contact portion 12, the polymer insulating layer 13, for example, a cap layer 14 made of silicon nitride, and a brazing metal filler 15 are shown. The materials of the conductors 9, 10 and 1l are typically aluminum and the material of the metal contact 12 is for example essentially the same as when composed of Ti-Pd-Au or Cr-Cu-Au alloys. It is preferably lead-wettable. The metallization 9, oxide layer 8 and substrate 7 are in the form of metal-oxide-semiconductor decoupling capacitors. Electrical stripe contacts 12 may be connected to X-conductor 10 as shown, and other stripe contacts (not shown) may be connected to power source 9 or Y-conductor 13.

3 shows a wafer 7, a ground metallization layer 16, and a power metallization layer 17 for use as a carrier substrate for the chip 1. Each chip is easily accessed from ground and power metallization, and more sophisticated metallization patterns, for example, narrow strips of ground and power metallization, are at least around the chip so that any one side of the chip has easy access to ground and power. May be used as needed, at least when partially expanded.

The ground metallization layer 16 is electrically connected to the thickly doped silicon substrate 7, and the power layer 17 is deposited on a thin insulator layer, for example, layer 8 as shown in FIG. 2. do.

The materials of the carrier substrate 7 and the chip 1 in FIGS. 2 and 3 are essentially the same as the single crystal material essentially with selective etching. Silicon is a first example of such a material, and potassium hydroxide is conveniently etched in this case (etching of silicon for mask alignment is described in US Pat. No. 4,470,875). Other suitable materials are III-V semiconductor mixtures such as, for example, gallium arsenide and gallium arsenide indium phosphide.

In a preferred embodiment, an unpacked silicon chip is installed on a silicon wafer used as a carrier substrate. The chip-to-chip connection is provided by two levels of signal nets with conductive paths of 5 to 15 widths, the power and ground planes. In order to insulate the plates, photodefinable polymers (eg, photosensitive polyamides) with low inductances are used.

Methods for connecting the chip and the wafer to each other include, for example, techniques such as wire bonding, tape auto bonding or "flip chip" solder balls on solder pads. In addition, as shown in FIGS. 1 and 2, self-aligned microstripes of solder metal on the chip can be used to connect to similar stripes on the wafer.

According to a preferred embodiment of the present invention, in the case of silicon wafers and chips, it has a squared face (111) face which is elaborately oriented by anisotropic wet etching of the wafer with the surface plate 100, and as a result It is possible to assemble a chip having a squared surface at an angle of 54 to 55 resulting. It can be inserted into a matching visualized groove in a silicon wafer and has an angle of about 126 to 125 between the slope and the wafer plane.

The micro-solder stripe across the squared oxide of the chip and groove is defined as CVD deposited, evaporated or sputtered resistance, for example Ag _2.0 Se / Ge _0.15 Se _0.85 to allow non-planar lithography. Can be. After the squared chip has fallen into a corresponding groove in the wafer, the wall of the groove and the needle-shaped micro-solder stripe can be fused by reflowing the solder.

Active components such as resistors, capacitors, and crystal oscillators may be incorporated into silicon wafers by installing on similarly squared silicon plugs into grooves in the wafer.

The square silicon face can also be used for interconnect modification or ordering. There may also be space through the thickness of the entire wafer for interconnection, modification or repair on the circuit.

If 10.2 cm or 12.7 cm (4 inch or 5 inch) silicon wafers are used, the printed wiring board forming the subsystem or system may be latched into one wafer. This is advantageous because the high chip mounting density accepts only average interconnect length, only lead time and low capacities and low power consumption. The co-switching noise induced by the inductance of the bonding wires is eliminated.

Self-aligned micro solder stripe techniques provide input and output of 400 to 800 I / O channels per chip without violating chip mounting density. All proposed silicon systems alleviate the reliability problems of the present invention due to thermal mismatch between silicon, ceramics and printed circuit board materials and minimize the risk of overheating of components due to high thermal conductivity of silicon.

An embodiment of the application is a "memory pack" consisting of a set of wafers stacked together, each wafer having an array of high density memory chips. These packs provide the speed of random access memory and the disk's standby capacity.

The entire system is designed by existing computer aided design processes and computer aided tests can be performed. The proliferation in I / O capabilities and chip mounting density opens new opportunities for system architecture. Since violations of the chip "go" are eliminated, less is needed to increase the number of circuits per chip. As the size of the chip decreases, production will increase. Moreover, shrinking the size of the chip allows fabrication of circuits that better adapt to the submicron design rules.

4, 5 and 6 show an integrated circuit 21 having a substrate 18, a chip 19, an insulating filter 20, and a contact 22. As shown in FIG.

5 and 6 also show the planarized insulating layer 23, the electrical conductor 24 and the contact 25.

6 also shows the planarized insulating layer 26 and the electrical conductor 27.

The substrate 18 and the chip 19 shown in FIGS. 4-6 are made of the same essentially single crystal material that is susceptible to selective selective etching, and silicon is a preferred embodiment of such material.

In particular, in the case of silicon, a chip having an inclined side (i.e., (111) face) that is precisely oriented by anisotropic wet etching of the (100) face having a slope occurring at an angle of 54 to 55 degrees is produced. It is possible to do The mating slope space in the Si wafer may coincide with an angle of 126 to 125 ° between the slope side and the wafer surface. In the figure, the angle of 54 to 55 degrees is between the top surface of the chip 19 and the slope of the chip, and the angle of 126 to 125 degrees is between the top surface of the wafer 18 and the slope of the wafer.

The following sequential steps can be used to assemble the assembly in accordance with the present invention. That is, the circuit is fabricated on the chip size of the substrate in a conventional manner by layer deposition and photolithography patterning. A silicon nitride layer is deposited on the front and back sides of the silicon wafer, a layer of photoresist material is deposited on the silicon nitride on the back side, and a pattern corresponding to the desired chip or hole is optically projected onto the photoresist layer. The exposed photoresist is developed and the developed pattern is simulated in the silicon nitride layer, for example by reactive ion etching. Selective etching of the exposed portions of the silicon wafer is conveniently carried out with the use of potassium hydroxide as a caustic agent, for example using a silicon nitride mask, and the etching can be performed in part within the wafer or through the entire thickness of the wafer. The corrosion rate is typically such that a 51 × 10 ⁻³ cm (20 mm) wafer is corroded for 7 to 8 hours.

Corroded chips are inserted into correspondingly corroded grooves, spaces or holes in the wafer and are easy to attach by means of insulating adhesive. The surface of the inserted chip is suitably essentially flush with the wafer surface.

Layers of planarization material such as, for example, polyimide or other sensitive polymers are deposited on the assembly, and the underlying circuit contact and corresponding holes are corroded by photolithographic patterning represented by reactive ion etching. Metallization, such as, for example, aluminum metallization, is patterned by reactive ion etching.

Among the suitable chip and wafer materials other than silicon are group III-V semiconductor compounds such as, for example, gallium arsenide and gallium arsenide indium phosphide.

The advantages of the new isolated circuit assembly are: In other words,

1. The new method eliminates wire bonding operation.

2. The new scheme eliminates independent mounting levels, for example called DIP or chip carrier.

3. All chips in an electronic system or subsystem are mounted in one operation.

4. The circuit design is facilitated by metallized contacts that can be located anywhere inside the chip.

5. Multilayer metallization can be made by repeated deposition, metallization and patterning of insulating layers.

6. The interconnection length between chips can be minimized with a suitable arrangement of chips on the substrate, which will reduce parasitic inductance and resistance. Parasitic capacitance is reduced by increasing the thickness of the insulating layer.

7 shows a wafer 28 that constitutes an integral part of an assembly made in accordance with the principles of the present invention. Advantageously, wafer 28 has a disk having a diameter of 75 to 150 mm and a thickness t of about 0.5 mm. In the illustration, the wafer 28 includes a single crystal silicon wafer.

8 shows an enlarged view of a portion of the wafer 28 described above. 8 shows a minimizing device, for example a silicon integrated circuit chip 29, adhered to the top of the wafer 28 by means of the bonding layer 31. In one example, layer 31 includes an adhesive material, such as a conventional polyamide material or silicon dioxide layer. Illustratively, layer 31 is spun to about 0.1-10 μm thick on the bottom surface of chip 29 before needle 29 is placed in contact with wafer 28.

In accordance with the principles of the present invention, one or more minimizing devices, such as chips 29, are secured to the top side of the wafer 28 shown in FIG. Chip 29 comprises, for example, a rectangular top surface of about 0.25 to 0.75 mm in thickness and about 6 mm on the side. In certain applications of Applicants' invention, more than 100 devices of various designs and types are mounted on the top side of the wafer 28.

Advantageously, the device mounted on wafer 28 is formed of chips cut from a single crystal silicon wafer, the top and bottom surfaces of which are the parallel 100 crystal planes of the silicon structure. Thus, the top and bottom surfaces of each chip mounted on wafer 28 are also on the (100) plane. The reason for selecting this particular orientation will be described in detail when the optional ethanol steps included in the manufacturing sequence of the assembly are described.

In accordance with Applicants' principles of the invention, multiple designs and forms of composite devices are installed on top and bottom of wafer 28. This is shown in FIG. 8, in which the device 30 shown is installed on the bottom side of the wafer 28 by the adhesive layer 32. As shown in FIG.

The top of the chip 29 and the bottom of the chip 30 shown in FIG. 8 each constitute its so-called active side. Included on the active side of each chip are standard devices such as transistors (not shown), positioning marks (not shown), and the like. Also included therein is a composite conductor pad with a relatively small area. Three pads 33, 35 and 37 on the chip 29 and three pads 34, 36 and 38 on the chip 30 are depicted schematically in FIG. do. For example, each pad has a square surface area of about 2.5 to 10 micrometers on its side.

Importantly, the small area pads included on the chips 29 and 30 (FIG. 8) are located anywhere in the central area of their top surface. In other words, this pad is not limited to being located along the periphery of the central area. Thus, as shown in FIG. 8, some of the pads are located in or towards the middle region of the central region. This is advantageous because it reduces the total lead length required on the chip. As a result, losses and delays caused by signals spreading from the chip to the associated circuits are reduced. In addition, the combination of reduced lead lengths and small area pads is further achieved in active regions useful for other devices. As a result, a very dense integrated design consists of it.

For the sake of clarity of the drawings, the importance below in relation to the description of FIGS. 9 to 13 will be determined in the assembly in which the signal device (chip 29) is installed on the top side of the wafer 28. However, what is described with respect to the process of the chip 29 is also suitable for the process of one or more accessory devices installed on the top side of the wafer 28 and also installed on the bottom side of the wafer 28 (eg, the eighth). And at least one additional device (such as chip 30 in FIG. 30).

In accordance with Applicants' inventive features, beveled edges are formed in each device installed on wafer 28. This inclined edge extends from the periphery of the center region of each device to the side of the wafer on which it is installed. Advantageously, these edges are formed in a particularly well defined etching step in which each chip installed on the wafer 28 is well etched to exhibit a (111) plane that constitutes a predetermined sloped edge. Thus, as shown in FIG. 9 by the reference lines 39 and 40 (showing the assembly portion taken along line 43 in FIG. 10), each edge to be formed on the chip 29 is defined by the chip ( As shown in FIG. 29, each edge to be formed on the chip 29 will be inclined at an angle of 54 ° to 50 ° with respect to the top surface of the chip 29. In this way, the peripheral zone of the top surface of the chip 29 will be removed by etching (of course, this zone should not be continued or closed. In fact, in some cases, with only one inclined edge per chip, the object of the invention To meet the requirements). In one particular embodiment, the width W (FIG. 9) of the band is about 300 to 1000 micrometers.

Advantageously, the contour of the inclined edge chip 29 shown in FIG. 9 is formed by selectively masking the top surface of the chip 29 and then by exposing the chip to a wet caustic such as dissolution of potassium hydroxide. do. Suitable etch resistant masks for such corrosive agents consist, for example, of silicon nitride. Layer 41 of silicon nitride, modeled by conventional lithographic techniques, is shown in FIG.

In addition, when the wafer 28 of FIG. 9 is made of silicon, or of another material etched with potassium hydroxide dissolution, the etch resistant layer also preferentially wafers rather than defining the preceding inclined edges on the installed chip. Is formed on the top surface of the. By way of example, layers 41 and 42 are each approximately 200 mm thick.

The silver caustic for forming the leading beveled edge on chip 29 (FIG. 2) consists of approximately 250 grams of potassium hydroxide dissolved in 0.8 liters of water and 0.2 liters of propanol. Etching for 3 to 10 hours with this melting furnace is effective to form a predetermined beveled edge. As a result, the silicon nitride masking layers 41 and 42 can be removed by etching the tissue of thermophosphoric acid, for example, as is known in the art. In the manufacturing sequence, the assembly constructed in accordance with the applicant's invention appears as shown in FIG.

The preceding slope to the edge of the chip 29 is not critical. Sloping edges only facilitate the formation of conductor runners. As described above, good etching is one method that is convenient and beneficial for achieving such sloped edges. However, other techniques can also be used to form slanted edges on the chip.

As in FIG. 11, the next step in Applicant's invention fabrication sequence is to form an insulating layer 44 on the entire top surface of the illustrated assembly. As an example, this layer 44 consists of a layer with silicon dioxide attached that is about 1 micrometer thick.

Only one conductor pad 35 on the chip 29 is shown in FIG. 11 for the sake of clarity. However, in the applicant's invention, it can be seen that 1000 or more small area pads are actually embedded on a conventional chip.

Layer 44 is then etched in a standard form using conventional integrated circuit modeling techniques to provide an opening in layer 44 that is consistent with conductor pad 35. In that way, the top surface of the conductor pad 35 is exposed as shown in FIG.

Next, a conductor layer approximately 1 micrometer thick, for example made of aluminum, is attached over the entire top surface of the assembly shown in FIG. The conductor layer is then shaped with suitable slab technology (e.g., using germanium selenide preservatives) to form a good line runner, which is runner is inclined one or more slopes of each chip coated with oxide from the chip pad. It extends down the edge and onto the main top surface of the assembly. Alternately, these runners extend to relatively large area pads disposed around the conductor pads or chip wafer assemblies contained on the other chips that were mounted.

Only one conductor runner 45 is shown in FIG. This runner 45 is inclined with one pad of the chip 29 to contact the pad 35 on the chip 29 and to be coated over the silicon dioxide layer 44 which constitutes the main top surface of the illustrated assembly. Extend to the bottom edge.

In accordance with the applicant's invention, an additional alternating insulation and conductor layer (not shown) is attached on top of the assembly shown in FIG. In that way, a multistage conductor model is formed in the assembly. In some embodiments, it is advantageous to form one or more conductor steps as a large area planar body. Such planar conductors are used, for example, as low resistance, low inductance ground or power supply.

FIG. 14 is the top form of an assembly constructed in accordance with the principles of the present invention (a suitable standard encapsulant is advantageous for this assembly but is not shown in FIG. 14). Just for this purpose, it is pointed out that four chips are included in the assembly shown. The three chips 46, 47, and 48 shown are coated on top of the wafer 28 and one chip 49 is installed on the bottom of the wafer 28 (150). For millimeter wafers, it may be desirable to include 1000 chips placed on top and bottom of the wafer In an embodiment, each such chip typically has a number of leads (eg, 100 or more) extending therefrom. However, for the sake of clarity of Fig. 14, each chip mounted at the top is shown in this simple manner including at least three leads which are less than five leads.

Thus, for example, the chip 47 provided in FIG. 14 has five leads connected thereto. The lead 50 of the chip 47 extends to the adjacent chip 46. Leads 51 and 52 interconnect chips 47 and 48. In addition, leads 53 and 54 extend between chip 47 and peripheral conductor pads 55 and 56, respectively.

In one measurement embodiment of Applicant's invention, each interconnected lead shown in FIG. 14 is approximately 1 to 10 microns wide. By way of example, each peripheral pad shown therein is about 1.25 x 1.25 millimeters. With various prior arts, it is a relatively easy matter to make electrical connections between such large area peripheral pads and similar assemblies or other elements included in the overall electronic system.

It will be appreciated that the foregoing construction and processing techniques are merely illustrative of the principles of the present invention. In accordance with this principle, many modifications and variations can be made by those skilled in the art without departing from the spirit and scope of the invention. For example, in accordance with Applicant's invention, it is easy to selectively interconnect peripheral pads or device pads on the top and bottom of the wafer by forming conductors that extend through the holes in the wafer. Furthermore, it is easy to fabricate a composite chip wafer assembly that implements the concepts described herein. In such composite assemblies, warp wall chips and straight wall chips pass through holes and are placed on both sides of the wafer, including the warp walls.

It can also be seen that the wafer 28 is made of a material other than silicon. In selecting alternating materials, factors such as matching the thermal properties of a wafer to the thermal properties of a combined chip are recognized.

Figure 15 shows a wafer 57 that constitutes the entire portion of an assembly made in accordance with the principles of the present invention. Advantageously, the wafer 57 is made of single crystal, and the diameter having a thickness of about 0.5 mm is cut into a disc shape of about 75 to 150 mm. According to an advantageous feature of the invention, the top and bottom surfaces of the wafer 57 are parallel and lie in the crystal plane of the silicon structure. The reason for choosing this particular direction becomes apparent later on when the good etching steps included in the fabrication order for the assembly are described.

For example, the corrosion protection layer 58 shown in FIG. 16 is located on the entire lower surface of the wafer 57. For example, layer 58 has silicon nitride positioned to a thickness of about 10 mm.

FIG. 17 is an enlarged view of a portion of the above-described wafer 10 and layer 58. In addition, FIG. 17 shows a microelement such as a silicon composite circuit chip 59 bonded to the bottom of layer 58 by an adhesive layer 60, for example. For example, layer 60 includes an adhesive material, such as a conventional layer of silicon dioxide or standard polyimide material. For example, layer 60 is made by rotating on the top surface of the chip 59 to a thickness of about 0.1 to 10 mm before the chip 59 is placed in contact with the layer 58.

In accordance with the principles of the present invention, one or more microelements, such as chip 59, are in contact with the lower end of wafer 57 shown in FIG. For example, the chip has a square top surface that is about 0.25 to 0.75 mm thick and about 6 mm on one side. In some applications of the present invention, more than 100 devices of various designs and shapes are disposed at the bottom of the wafer 59.

The upper end of the chip 59 shown in FIG. 7 forms a so-called active surface of the chip. Included on the active side of the chip are transistors (not shown), alignment indicators (not shown), and many other standard devices. Also included on the chip are a plurality of relatively small area conductive pads. Three pads 61, 62 and 63 located in the center area of the active surface of the chip are shown in FIG. Each pad has, for example, a square top surface that is only about 2.5-10 mm on one side.

Importantly, the small area pads included on the chip 59 may be located anywhere in the central area of the top surface. In other words, the pad is not limited to being located around the central area. Therefore, as shown in FIG. 17, some pads may be located in the middle of or toward the central area. This is beneficial because the total lead length required for the pad is reduced on the chip. As a result, the losses and delays caused by the signal from the chip to the provision circuit are reduced. Moreover, the combination of reduced lead length and small area pads makes other devices use more active area. As a result, a compact combination circuit design is thereby made possible.

In accordance with a feature of the present invention, a very contoured through-hole with four inclined walls is formed in the wafer to match the central region of each disposed element, such as chip 59. Advantageously, the hole is formed with a special wet etching step in which the wafer 57 is inherently well etched to represent the plane that constitutes the desired inclined wall. Therefore, as shown in FIG. 18 by reference lines 64 and 65, each wall formed in wafer 57 penetrates the wafer and inclines at an angle of 35 degrees to 36 degrees relative to the vertical wall.

The lower or smaller opening of each penetrating sloping wall hole in the wafer 57 is designed to lie only in the center region of the combined chip. In that way, the peripheral band of the chip that does not contain a conductive pad remains attached to the bottom of the wafer. In a particular embodiment, the width W (FIG. 18) of this band is for example about 10 to 250 mm. Of course, these bands do not have to be continuous, enclosed or constant in width.

의 물과 0.2

의 프로패놀내에 용해된 약 250g의 수산화포타지움을 구비한다. 그러한 용해제를 갖고 약 3、내지 10시간동안 에칭은 여기서 규정된 웨이퍼(57)내에 바람직한 경사벽 구멍을 형성하는데 효과적이다. 다음에, 상단 실리콘 질화물 마스킨 층(66) 및 구멍의 작은 개구에 직접 놓이는 하단 실리콘 질화물 마스킹 충(58)의 부분은 주지된 바와 같이 예를 들어 강인산내에서 구조물을 에칭함으로써 제거될 수 있다.Advantageously, the through-holes outlined in FIG. 18 are formed by selectively masking the top surface of the wafer and exposing it to a wafer by wet etching, such as dissolution of potassium hydroxide. Suitable anti-etch masks for such etching are made of silicon nitride, for example. A silicon nitride layer 66 formed by conventional lithography techniques is shown in FIG. For example, layer 66 is about 200 mm thick. An advantageous etching to form the above through hole in the wafer 57 is 0.8

With water of 0.2

Approximately 250 g of potassium hydroxide dissolved in propanol. Etching for about 3 to 10 hours with such a solvent is effective to form the desired inclined wall holes in the wafer 57 as defined herein. Next, the portion of the bottom silicon nitride masking layer 58 that lies directly in the top silicon nitride masking layer 66 and the small openings in the holes can be removed, for example, by etching the structure in strong phosphoric acid.

In the state of fabrication order, an assembly fabricated in accordance with the present invention is shown in FIGS. 19 and 20. In the perspective view of FIG. 20, the adhesive layer 60 has been partially cut to show some small area conductive pads included on top of the chip 59. These include the pads 61, 62 and 63 previously defined. The entire exposed portion of the adhesive layer 60 shown in FIG. 20 can be removed by using a standard etch for the layer. In contrast, it is advantageous to leave only the layer 60 intact, etching only the small region openings through the wafer as opposed to the conductive pads assembled on the chip 59. At another stage of production described below, the choice of this approach is defined.

As shown in FIG. 21, the next step in the fabrication sequence of the present invention is to form an insulating layer 67 over the entire top surface of the illustrated assembly. For example, layer 567 has a deposition layer of about one thickness of silicon dioxide.

Only one conductive pad 62 is shown in FIG. 21 on the chip 59 so that the drawing is not overly complicated. However, according to the present invention, it can be seen that more than 1000 small area pads are actually included on several chips. Etching of layer 67 is then performed in a standard manner that utilizes conventional integrating circuit molding techniques to provide openings in layer 67 that match conductive pads 62. In one of the same or subsequent etching steps where the layer 67 is etched, a matching opening is formed in the adhesive layer 60. In that way the top surface of the conductive pad 62 is exposed as shown in FIG.

Next, an about 1 μm thick conductive layer made of aluminum, for example, is deposited over the entire top surface of the assembly shown in FIG. The conductive layer then uses a suitable lithography technique (e.g., germanium selenite caustic) to form a thin line runner that extends from the chip pad above the main top surface of the assembly and over one or more inclined walls of the holes associated with each chip. ) These runners, in turn, extend a relatively large area pad disposed in a different arrangement around the chip and chip wafer assembly.

The single conductive runner 68 is shown in FIG. Runner 68 contacts pads 62 on chip 59 and extends one inclined wall of the apertures shown to lie in silicon dioxide layer 67, which constitutes the major top surface of the assembly as shown. .

According to the present invention, an additional alternating insulating and conductive layer (not shown) is deposited on top of the assembly shown in FIG. In that way, multilevel conductive circles are formed in the assembly. In some embodiments, it is beneficial to form one or more conductivity levels, such as large area planar conductors. However, planar conductors are used, for example, in low resistance, low inductance ground or on the power supply side.

FIG. 24 shows the top of a portion of an assembly made in accordance with the principles of the present invention (closing the capsule to a suitable size for the assembly is beneficial, although not shown in FIG. 24). For display purposes, 24 chips are indicated as included in the illustrated assembly (with 150 chips placed in a 150 mm wafer). In practice, each such chip typically has a number of leads (eg, 100 or more) that extend from the chip. However, each arranged chip is simply shown as including at least one, but at most seven, so that FIG. 24 is not overly complex.

Thus, the upright chip 81 in FIG. 24 is represented by seven leads connected to the chip. Leads 82 and 83 of chip 81 extend to adjacent chips 69 and 70, respectively. Leads 71 to 75 also extend between the chip 81 and the peripheral conductive pads 76 to 80.

In one particular embodiment of the present invention, each of the mutual coupling leads shown in FIG. 24 has a width d of 1 to 10 micrometers. By way of example, each of the peripheral pads shown here is about 1.25 x 1.25 millimeters. In the prior art, it is a relatively easy way to make electrical connections between the peripheral pads in such a large area or other components included in an electrical system.

The foregoing structure and processing techniques merely describe the principles of the present invention. In accordance with the above principles, many modifications and substitutions may be made by those skilled in the art without departing from the spirit and scope of the invention. As an example, it is convenient to assemble a synthetic chip-wafer assembly that implements the above-described concepts. In the composite assembly, the inclined wall chip and the straight wall chip are provided on both sides of the wafer including the inclined wall passing through the opening.

In some cases it is actually important that wafer 57 is made of a material different from silicon. In selecting the material to be replaced, factors in matching the thermal properties of the wafer with those of the associated chip and the ability of the wafer to be properly etched are considered. However, of course, a technique other than etching is used to form the pass-opening described above. The inclination of the wall of the opening is not determined. Inclined walls are used only to utilize the slides on the walls. Appropriate etching as described above is one convenient method for producing the inclined wall opening.

1 is a cross-sectional view of a circuit chip portion.

2 is a cross-sectional view of a wafer portion.

3 is a scaled illustration of an integrated circuit assembly showing a ground metallization layer and a power metallization layer deposited side by side.

4, 5, and 6 are cross-sectional views of integrated circuit assemblies at different stages of manufacture.

7-14 show portions of particular illustrative assemblies, not shown in scale.

15 through 14 illustrate portions of particular illustrative assemblies, not shown in scale.

Claims (35)

A device comprising a substrate consisting essentially of a single crystal material and at least one integrated circuit chip electrically connected to an electrical circuit defined by lithography, wherein the substrate is inclined from a crystallographic anisotropic etch. Having a surface depression with a wall (hereinafter referred to as depression), wherein the chip has an inclined edge formed from a crystallographic anisotropic etching, the inclined edge and the inclination are configured to be parallel so that the chip is positioned on the substrate. Integrated circuit chip assembly. 2. The integrated circuit chip assembly of claim 1, wherein the chip has a circuit support surface facing a recess in the wafer. 3. The integrated circuit chip assembly of claim 2, wherein contact is made to the circuit by at least one strip conductor on the sidewalls of the depression. 4. The integrated circuit chip assembly of claim 1,2 or 3, comprising a plurality of chips, the chips being electrically interconnected by electrical conductors on the wafer. 5. The integrated circuit chip assembly of claim 4, wherein the electrical conductor is separated by a photosensitive polymer material. 2. The integrated circuit chip assembly of claim 1, comprising at least one passive element mounted on the chip. The integrated circuit chip assembly of claim 1, wherein at least one optical fiber terminates on the chip. 2. The integrated circuit chip assembly of claim 1, wherein the electrical circuit comprises a ground conductor and a power conductor and includes a decoupling capacitor between the ground conductor and the power conductor. The integrated circuit chip assembly of claim 8, wherein the decoupling capacitor is a metal oxide semiconductor capacitor. 10. The integrated circuit chip assembly of claim 9, wherein the capacitor comprises the substrate, an oxide layer on the substrate, and a metal layer on the oxide layer. 2. The device of claim 1, comprising a wafer and at least one circuit transfer chip, wherein the material of the wafer is formed essentially of a single crystal, and the material of the chip is formed essentially of a single crystal, such as the wafer, A first side wall forming a first angle to have a first surface and a first surface, the angle being formed at 90 degrees or less by etching of the material of the chip, and the wafer forming a second angle having a second surface And a second side wall and a second surface, the second angle being formed by etching of the wafer material to be essentially complementary to the first angle, wherein the chip is the result of registration between the first side wall and the second side wall. And a portion of the wafer, the chip being aligned with respect to the wafer, wherein the chip comprises an integrated circuit and a planar layer located in the circuit, and electrical connection to the circuit is provided for metallization over the planar layer. The integrated circuit chip assembly, characterized in that it is formed. 12. The integrated circuit chip assembly of claim 11, comprising two or more planar layers and a metal. 13. The integrated circuit chip assembly of claim 12, wherein the material of the planar layer is a photosensitive material. 12. The integrated circuit chip assembly of claim 11, wherein the material of the body portion of the substrate and the material of the body portion of the chip have the same crystallographic structure. 12. The integrated circuit chip assembly of claim 11, wherein the material of the body portion of the substrate is essentially the same as the material of the body portion of the chip. 16. The integrated circuit chip assembly of claim 15, wherein said material is a semiconductor material. 17. The integrated circuit chip assembly of claim 16, wherein the material is essentially silicon. A device comprising a substrate consisting essentially of a single crystal material and at least one integrated circuit chip electrically connected to an electrical circuit defined by lithography, wherein the substrate is a wafer having an upper and a lower surface. The wafer has a conductive terminal portion along a boundary spanning the top surface, the chip mounted on one surface of the wafer including a conductive element at a central portion or at the top surface, at least one of the circuit chips being the Mounted on a surface, the conductive element including a conductive element in a central portion of the chip, wherein the conductive pattern is connected to an element in which the element of the mounting chip is included on a selected chip or at least another one of the terminal portions; When placed on an unmounted surface of the chip, each chip supports a wafer mounted at the center of the chip. Having at least one inclined edge extending toward the surface, when the conductive element is disposed on the mounting surface of the chip, the wafer has at least one opening wall inclined toward the wafer surface against support of the needle from the chip, Wherein the pattern is associated with a mounting chip and is disposed on at least one wafer inclined wall and covers the opposite inclined surface of the wafer. 졔 18. The integrated circuit chip assembly of claim 18, wherein one of the chips is mounted on a top or bottom or top and bottom layers of the wafer. 20. The integrated circuit chip assembly of claim 18 or 19, wherein the chip comprises single crystal silicon on top and bottom surfaces in the (100) crystal plane. 21. The integrated circuit chip assembly of claim 20, wherein the inclined surface lies on a (111) crystal plane of the silicon chip. 19. The integrated circuit chip assembly of claim 18, wherein the mounting means on the wafer includes a sticking tooth disposed between each element and the wafer. 、 19. The substrate of claim 18, wherein the substrate has a relatively wide surface and has terminal pads, wherein the plurality of semiconductor chips contact a surface of the substrate with its front surface comprising a plurality of conductive pads within the chip that provide an external connection to the circuit elements. Having a back side and a back side, each chip having an inclined edge extending from its front side to the substrate, the inclined side of the chip and the surface of the substrate such that the conductive passages interconnect the terminal pads and other chips on the substrate with the chips; An integrated circuit chip assembly, extending from a conductor pad along an edge. 19. The device of claim 18, wherein the plurality of semiconductor chips have a plurality of conductive pads on the top surface to provide electrical connection to the circuit elements within the chip, and the cap member is coupled to a portion of the top surface of the plurality of chips separated from the surface. And the cap member includes an inclined wall opening to allow access to the conductive pad, the conductive passage extending over the opposite surface of the cap member and extending along the inclined side wall of the opening to contact the conductive pad and interconnect the chips. Integrated circuit chip assembly, characterized in that. 19. The integrated circuit chip assembly of claim 18, wherein the means for mounting each chip on each surface of the wafer comprises an adhesive layer disposed around the mounting surface of each chip. 19. The integrated circuit chip assembly of claim 18, wherein the electrical circuit comprises a ground conductor and a power conductor, wherein a decoupling capacitor is disposed between the ground conductor and the power conductor. 27. The integrated circuit chip assembly of claim 26, wherein the decoupling capacitor is a metal-oxidation-semiconductor capacitor. 28. The integrated circuit chip assembly of claim 27, wherein the capacitor comprises the substrate, an oxide layer on the substrate, and a metal layer on the oxide layer. 19. The device of claim 18, wherein the chip comprises an integrated circuit and a planar layer located in the circuit and a portion of the wafer, wherein an electrical connection to the circuit is formed by metallization over the planar layer. Integrated circuit chip assembly. 30. The integrated circuit chip assembly of claim 29, comprising water or more planar layers and a metal. 30. The integrated circuit chip assembly of claim 29, wherein the material of the planar layer is a photosensitive material. 19. The integrated circuit chip assembly of claim 18, wherein the material of the body portion of the substrate and the material of the body portion of the chip have the same crystallographic structure. 33. The integrated circuit chip assembly of claim 32, wherein the material of the body portion of the substrate is essentially the same as the material of the body portion of the chip. 34. The integrated circuit chip assembly of claim 33, wherein the material is a semiconducting material. 35. The integrated circuit chip assembly of claim 34, wherein said material is essentially silicon.

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