KR900004764B1 - Signal processing circuit - Google Patents

Abstract

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Description

Signal processing circuit

1 is a circuit diagram showing the structure of a conventional gain control amplifier circuit.

2 and 3 are characteristic diagrams showing the characteristics of the gain control amplifier circuit shown in FIG. 1, respectively.

4 is a circuit diagram showing the structure of a conventional gain control amplifier circuit.

5 is a circuit diagram showing a structure of a gain control amplifier circuit according to the first embodiment of the present invention.

6 and 7 are characteristic diagrams each showing characteristics of the gain control amplifier circuit shown in FIG.

8 through 10 are circuit diagrams each showing a modified example of the first embodiment of the present invention.

11 is a circuit diagram showing a structure of a gain control amplifier circuit according to the second embodiment of the present invention.

12 and 13 are characteristic diagrams each showing characteristics of the gain control amplifier circuit shown in FIG.

14 is a circuit diagram showing a modification to the second embodiment of the present invention.

FIG. 15 is a circuit diagram showing a modification of the gain control amplifier circuit shown in FIG.

16 and 17 are cross-sectional views each illustrating a structure in which the gain control amplifier circuit shown in FIG. 15 is integrated into pellets.

* Explanation of symbols for main parts of the drawings

1: Input terminal 2: Terminal

3: Gain control terminal 4: Output terminal

11,12,21,61,73: MOSFET (Insulated Gate Field Effect Transistor)

13,14,22,41,42,51,52,71,72: Bipolar Transistor

23: input side tuning circuit 24: gain control circuit

25: output side tuning circuit 31,53: resistance

32,43,62,74: Capacitor 44,45: Diode

The present invention relates to a signal processing circuit in which a field effect transistor and a bipolar transistor are connected in series, and more particularly, to a signal processing circuit that can be effectively applied to a gain control amplifier circuit.

The gain controlled amplifier circuit (Gain Controled Amplifier) used in the high frequency amplifier stage which is part of the tuner is generally composed of the circuit shown in FIG. 1 or 4, the circuit configuration as shown in FIG. The circuit configuration shown in FIG. 4 is published in Japanese Patent Application Publication No. 67-160170, for example, on pages 556 to 569 of the book Integrated Electronice published by McGraw-Hill. It is.

That is, in the circuit configuration shown in FIG. 1, the MOSFET (insulated gate field effect transistor: 11) provided at the front end and the other MOSFET 12 provided at the rear end are formed in series connection. In addition to the DC bias signal and the input signal supplied to the gate of the input side tuning circuit (not shown) through the input terminal 1, the source of the MOSFET 11 is provided with a constant voltage (Vo: normal ground) through the terminal 2. On the other hand, a voltage for gain control is applied to the gate of the MOSFET 12 through the gain control terminal 4, and the output terminal 4 is connected to the drain of the MOSFET 12. .

On the contrary, in the circuit configuration shown in Fig. 4, the NPN transistor 14 disposed at the rear end is connected to the NPN transistor 13 disposed at the front end in series connection. Not only is the input terminal 1 connected to the base, but also the terminal 2 to which a constant voltage is applied to the emitter of the transistor 13 is connected, while the gain control terminal is connected to the base of the NPN transistor 14 provided at the rear end. In addition to being connected to (3), the collector is connected to the signal output terminal (4).

Therefore, the circuit configuration shown in FIG. 1 amplifies a signal applied to the input terminal 1 in a state in which a predetermined operating current flows through the MOSFET 11 at the front end and the MOSFET 12 at the rear end. There is a drawback that the signal distortion component, especially the third-order distortion component, for the input / output characteristics becomes large. This is because the equivalent resistance is large in the structure and operation principle of the MOSFET.

In detail, the DC input / output characteristics (that is, the voltage V ₁₂ of the input terminal 1 and the terminal 2 and the output terminal) in a state where a predetermined gain control voltage is supplied to the gate of the MOSFET 12 is provided. 4) and the current I ₄₂ of the terminal 2) are as shown in FIG. 2 shows the voltage V ₃₂ between the gain control terminal 3 and the terminal 2 (gain control voltage) as a variable while the voltage V ₄₂ between the output terminal 4 and the terminal 2 is 6 V as an example. This is a characteristic diagram when it is fixed. Therefore, the region where the characteristics of the MOSFET 11 disposed at the front end dominates (that is, the region where the output current I ₄₂ is small) and the region where the characteristics of the MOSFET 12 disposed at the rear stage dominate (that is, the region where the output current I ₄₂ is large). The magnitude of the equivalent resistance is related to the magnitude of the third-order distortion component of the output current I ₄₂ near the boundary of. When the input / output characteristic shown in FIG. 2 is differentiated once, the characteristic of the forward transfer admittance | Y _f | (= ΔI ₄₂ / ΔV ₁₂ ) with respect to the input voltage V ₁₂ is obtained. In this case, the curve change point shown in FIG. 3 corresponds to the third-order distortion component of the input / output characteristic described above, but in the characteristic view of FIG. 3, the curve change point having a large change rate exists within the change range of the input voltage V ₁₂ . It can be seen that there is a large third-order distortion component in the characteristics shown in the figure.

In addition, when the gain control voltage V ₃₂ is lowered, two curve transition points are generated within the variation range of the input voltage V ₁₂ , thereby increasing the third-order distortion component.

On the other hand, since the equivalent resistance between the collector and the emitter of the NPN transistor 13 is much smaller than the equivalent resistance of the MOSFET, the circuit configuration shown in FIG. There is a drawback that the distortion component becomes large.

The present invention has been made in view of the above circumstances, and an object thereof is to provide a signal processing circuit having a small signal distortion, in particular, a third-order distortion component, in input / output characteristics.

In order to achieve the above object, the signal processing apparatus according to the present invention includes a means (1) for receiving a first signal and a gate connected to the means (1) for receiving the first signal and a predetermined end of the current path. An insulated gate field effect transistor (MOSFET) 21 to which a potential is applied, a means 3 for receiving a second signal, a means 4 for outputting an output signal, and the other end of the current path of the MOSFET 21. One end of the collector-emitter passage is connected to the other end of the collector-emitter passage to the output means 4, the base of which is connected to the means 3 for receiving the second signal and the second signal. And a NPN-type bipolar transistor 22 whose base current is controlled by the second signal supplied from the means 3 receiving the signal, and processing the first signal based on the second signal. , Especially small third-order distortion It is to have input / output characteristics.

Hereinafter, a first embodiment of the present invention will be described with reference to the accompanying drawings.

5 is a circuit diagram of the gain control amplifier circuit according to the first embodiment of the present invention, in which the source of the N-channel growth-type MOSFET or the depletion / growth-type MOSFET 21 has a constant potential (normal ground potential). It is connected to the terminal 2 to be applied, and the gate of the MOSFET 21 is connected to the input side tuning circuit 23 via the input terminal 1. Then, the emitter of the NPN transistor 22 is connected not only to the drain of the MOSFET 21 but also to the gain control circuit 24 via the gain control terminal 3, and to the base of the transistor 22. The collector is connected to the output side tuning circuit 25 via the signal output terminal 4.

Referring to the operation of FIG. 5 configured as described above, the input side tuning circuit 23 applies, for example, a high frequency signal obtained by receiving a VHF vs. television broadcast signal to the signal input terminal 1 together with a DC bias signal as necessary. In addition, the gain control circuit 24 supplies the gain control voltage signal to the terminal 3, thereby sequentially outputting the output terminal 4 and the transistor 22 from the operating power supply of the output side tuning circuit 25. A predetermined operating current flows to the terminal 2 through the collector-emitter passage and the current passage of the MOSFET 21. Accordingly, the transistors 21 and 22 amplify the input signal with a gain corresponding to the gain control voltage supplied to the base of the transistor 22 in the state where the operating current flows.

FIG. 5 the circuit input voltage of the configuration shown in (that is, the input terminal 1 and the voltage between the terminal (2)) V ₁₂ and the output current (that is, the output terminal (4 current between) the terminals (2)) I ₄₂ As shown in FIG. 6, the relationship with the current becomes a direct current characteristic. In FIG. 6, the MOSFET 21 having good high frequency characteristics is used, while the frequency characteristic of the current amplification factor hfe as the transistor 22 is, for example, about 1 GHZ. The control voltage (i.e., the voltage between the gain control terminal 3 and the terminal 2) V ₃₂ is maintained by maintaining the maximum value up to a collector current (about 80 mA) with the current amplification factor hfe large. It shows a graph with variables. In addition, the operating voltage (ie, the voltage between the output voltage 4 and the terminal 2) V ₄₂ is set to 6V. The characteristics of the forward transfer admittance │Y _f │ (O = ₄₂ / V ₁₂ ) for the input voltage V ₁₂ obtained by differentiating the input / output characteristics shown in FIG. 6 once are shown in solid lines in FIG. In the characteristic of forward transfer admittance Y _f │ (O = I ₄₂ / V ₁₂ ) shown in Fig. 8, the rate of change near the curve change becomes smooth and the curve change point becomes 1 even in the region where the control voltage V ₁₂ is small. That is, the third-order distortion component in the input / output characteristic for the circuit configuration shown in FIG. 5 is reduced compared to the third-order distortion component in the input / output characteristic for the conventional circuit configuration shown in FIG. Therefore, as can be seen from FIG. 6, since the linearity of the input / output characteristics is good, the primary distortion component and the secondary distortion component are also smaller than in the conventional case, and the power gain varies according to the control voltage V ₁₂ . In this state, the gain control amplifier circuit of the present embodiment can obtain an output signal with less distortion than that of the prior art.

In addition, when a high frequency input signal is obtained by receiving, for example, UHF vs. television broadcast waves, it is preferable to use a good high frequency characteristic (e.g., f _T = 3 GHz) as the characteristic of the transistor 22 provided at the rear end.

A modification of the gain control amplifier circuit according to the first embodiment of the present invention will now be described with reference to FIGS. Here, since the basic configuration of the modified example of the gain control amplifier circuit is the same as that shown in FIG. 5, the same parts as those shown in FIG. 5 are given the same reference numerals as in FIG. 5, and the description thereof is omitted. Only the differences in FIG. 5 from the configuration will be mainly described.

8 shows a first modification of the gain control amplifier circuit according to the first embodiment of the present invention. The characteristics of the gain control amplifier circuit are characterized by the base and the gain control terminal 3 of the transistor 22 arranged behind. The high-frequency grounding capacitor 32 is connected between the base of the transistor 22 and the gain control terminal 3 while the resistor 31 for base current adjustment and base protection is inserted between and. In such a gain control amplifier circuit, the characteristic of the forward transfer admittance | Y _f | is represented by a dotted line in FIG. 7, and the gain control amplifier circuit shown in FIG. 8 can be seen from FIG. In the third order distortion component is improved compared to the conventional example.

9 shows a second modified example of the gain control amplifier circuit in accordance with the first embodiment of the present invention. The gain control amplifier circuit is characterized by an NPN transistor having Darlington connection instead of the transistor 22 in the rear stage. 41 and 42 are used, a high frequency grounding capacitor 43 is connected between the base of the transistor 41 and the gain control terminal 3. The capacitor 43 may be connected between the source of the MOSFET 21 and the base of the transistor 41.

FIG. 10 shows a third variation of the gain control amplifier circuit according to the first embodiment of the present invention. The characteristics of the gain control amplifier circuit are characterized by (1) a NPN transistor having Darlington connection instead of the transistor 21 provided at the rear end. (51) and (52) are used, ② the base current adjusting resistor 53 is inserted between the base of the transistor 52 and the gain control terminal 3, and ③ the base and the gain control terminal of the transistor 51. The high frequency grounded condenser 54 is connected between (3).

The gain control amplifier circuit according to the second embodiment of the present invention will be described with reference to FIG.

The difference between the gain control amplifier circuit shown in FIG. 11 and the gain control amplifier circuit shown in FIG. 11 is that the drain of the N-channel growth-type MOSFET 61 for gain control is connected to the collector of the transistor 22 arranged behind. The source of the MOSFET 61 is connected to the base of the transistor 22 while the gate of the MOSFET 61 is connected to the gain control terminal 3 as well as the base and the gain control of the transistor 22 provided at the rear end. The high frequency grounded capacitor 62 is connected between the terminal 3. It is preferable that the capacitance between the drain and the source of the MOSFET 61 is small so that no extra capacitance is added between the collector and emitter of the transistor 22. As a result, the MOSFET 61 has a high sensitivity (higher mutual conductance) having the same high frequency characteristics as the MOSFET 21.

In the gain control amplifier circuit of FIG. 11, the base current of the transistor 2 is controlled as the gate voltage of the control MOSFET 61 is controlled to control the drain current of the MOSFET 61. The gain shown in FIG. input-output characteristic is the other hand, the forward transmission admittance │Y _f │ characteristic represented as illustrated in the Figure 12 of the control amplifier circuit is indicated as shown in FIG. 3. Thus, as can be clearly seen in FIGS. 12 and 13, gain control is enabled and the signal distortion component is further reduced compared to the gain control amplifier circuit shown in FIG.

FIG. 14 shows a variation of the gain control amplifier circuit according to the second embodiment of the present invention, which is different from FIG. 11 except that the NPN transistor 71 having Darlington connection instead of the bipolar transistor 22 provided at the rear end thereof. While 72 is used, the current path of the control MOSFET 73 is connected to the collector of the transistor 72 and the base, while the high frequency ground is connected between the base of the transistor 71 and the gain control terminal 3. The capacitor 74 is connected. In the gain control amplifier circuit, when the control MOSFET 73 has a good direct current characteristic, it is possible to obtain good characteristics of the same aspect as the embodiments of the present invention as described above.

In the above-described embodiments, while applying a high frequency input signal to the input terminal 1 (the gate of the transistor 21), a gain control voltage signal is applied to the control terminal 3 to convert the high frequency input signal to the control signal. Although the present invention has been described as amplifying with a corresponding gain, the present invention is not limited thereto, and the input signal may be any one of a low frequency signal and a normal frequency signal as well as a high frequency signal.

In addition, in the above-described embodiment of the present invention, the case in which the input signal applied to the input terminal 1 is amplified to a gain corresponding to the gain control voltage signal applied to the gain control terminal 3 has been described. The present invention is not limited thereto, but the first signal and the second signal are input to the gain control terminal 3 while the first signal is input to the input terminal 1 of the gain control amplifier circuit shown in FIG. It is also effective when mixing.

The gain control amplifier circuit according to the embodiment of the present invention may be an integrated circuit configuration by bipolar / MOS integrated processing or an individual component configuration, but can also be used in compound semiconductors such as GaAs.

As an example, the gain control amplifier circuit shown in FIG. 15, in which the gain control amplifier circuit shown in FIG. 9 is partially modified, is integrated into one pellet by bipolar / MOS processing using silicon. The cross-sectional structure formed is as follows. Here, the difference from the gain control amplifier circuit shown in FIG. 9 among the gain control amplifier circuit shown in FIG. 15 is that one end of the capacitor 43 is connected to the source of the MOSFET 21, and The bidirectional diode of protective diodes 44 and 45 connected in series in the reverse direction for gate input protection is added between the gate and the source.

FIG. 16 shows an example in which the gain control amplifier circuit shown in FIG. 15 is formed using a p-type silicon substrate, and FIG. 17 shows a gain control amplifier circuit shown in FIG. 15 using an n-type silicon substrate. For example.

In FIG. 16, the P-type epitaxial layer 110B is formed on the P-type silicon substrate 110A, and the n-type high concentration (at a predetermined position between the silicon substrate 110A and the epitaxial layer 110B) is formed. n ⁺ type) buried layer 113 is formed. Subsequently, an n-type well region 114 and an n ⁺ -type region 115 are formed adjacent to the epitaxial layer 110B on the n ⁺ buried layer 113, and the surface region of the well region 114 is formed. P-type regions 116 and 117 are formed at regular intervals, and n-type regions 118 and 119 are formed in the surface regions of the P-type regions 116 and 117, respectively. An oxide film 120A is formed on the surface of the epitaxial layer 110B, and the oxide film 120A on the n ⁺ type region 115, the P type regions 116, 117, and the n type region 118, 119. In the connection hole is formed.

On the oxide film 120A, the wiring electrode 121 to be connected to the n ⁺ type region 115 and the wiring electrode 122 to be connected to the P type region 117 are connected to the P type region 116 and the n type region 119. A wiring 124 for connecting the wiring 123 and the n-type region 118 and the n-type region 125 corresponding to the drain D of the MOSFET 21 described later is formed. These wirings are made of aluminum.

The n-type well region 114, the P-type region 116, and the n-type region 118 correspond to the collector, base, and emitter of the transistor 41 provided at the front end in FIG. 15, respectively, and the n-type well region ( 114, the P-type region 117, and the n-type region 119 correspond to the collector, the base, and the emitter of the transistor 42 provided at the rear end, respectively, and the wiring electrodes 121 and 122 are output during FIG. Corresponds to terminal 4 and gain control terminal 3, respectively.

The n-type regions 125, 126 and 127 and the P ⁺ type region 128 are formed in the other surface regions of the epitaxial layer 110B, and the surface regions of the n-type region 127 are formed. The P ⁺ type region is formed in the P ⁺ type region 130, and the P ⁺ type region 130 is formed over the epitaxial layer 110B and the n type region 127. A gate electrode 131 is formed on an oxide film (gate (oxide film) 120B) between the n-type regions 125 and 126, and an aluminum electrode is formed through a thin oxide film 120B on a portion of the P ⁺ type region 128. A film 132 is formed An oxide film in which n-type regions 125 and 126, P ⁺ -type regions 128 and 130, and a gate electrode 131 are formed on the surface of the epitaxial layer 110B. Connection holes are formed in the 120. On the oxide film 120A, the wiring electrodes 124 connected to the n-type regions 118 and 125 and the wiring electrodes 133 connected to the n-type region 126, Wiring electrodes 134, 135, 136, and 137 connected to the P ⁺ type regions 128, 129, 130, and the gate electrode 131, respectively, are formed. These wirings are formed of aluminum.

Here, the n-type regions 125 and 126 and the gate electrode 131 correspond to the drain, source, and gate of the MOSFET 21 in FIG. 15, and the wiring electrodes 137 and 133 are connected to the input terminal 1 ( 2), and the wiring electrodes 132 and 134 correspond to the electrodes of the capacitor 43, respectively. The wiring electrodes 132 and 134 are respectively connected to the wiring electrodes 123 and 133 by aluminum wiring (not shown). The wiring electrodes 135 and 136 correspond to the anodes of the diodes 44 and 45, respectively, and the wiring electrodes 137 and 133 are connected by wiring electrodes (not shown).

The gain control amplifier circuit shown in FIG. 15 is fixed on a lead frame by a gold silicon process or resin bonding on a lead frame, in which the input terminal 1, the gain control terminal 3, and the signal output terminal 4 are used. The wiring electrodes 137, 122, 121 and lead terminals corresponding to the terminals 1, 3, 4 are connected by wire bonding, and the electrodes (MOSFETs) corresponding to the terminals 2 are connected. 21 is connected to the source of 21) by wire bonding to the lead frame.

An example of a process of manufacturing an integrated circuit having the structure of FIG. 16 will be described below.

An oxide film is formed on the surface of the P-type silicon substrate 110A doped with boron having a concentration of, for example, 4 × 10 ¹⁴ Cm ⁻³ , and patterned corresponding to the buried layer 113 on the oxide film, and then using the oxide film as a mask. N ⁺ buried layer 113 is formed by diffusing antimony to a concentration of 5 x 10 ¹⁵ Cm ^-3 on the substrate 110A. Thereafter, a silicon epitaxial layer including boron having a concentration of 1.8 × 10 ¹⁵ Cm ⁻³ is formed on the substrate 110A at a thickness of about 7-8 μm.

Next, an oxide film is formed on the epitaxial layer 110B, and the oxide film is patterned to form the layers 114, 115, and 127. Using the patterned oxide film as a mask, phosphorus is accelerated to 150KeV, 1 × 10 ¹⁵ Cm ⁻² to form layers 114 and 127, and 50KeV and 9 × 10 ¹⁵ Cm ⁻² to form layers 115. Ion implantation into the epitaxial layer (110B) with an excessive dose.

PSG (Polly Silicon Glass) is deposited in the openings in the oxide film, and thermal diffusion is performed for 15 hours in a nitrogen gas atmosphere at 1,200 ° C. By this process, the n-type well region 114, the n ⁺ -type region 115, and the n-type region 127 are formed. Subsequently, an oxide film was formed to a thickness of 180 nm, and the oxide film was patterned to form regions 116, 117, 128, 129, and 130, and then 50 KeV, 1 × 10 ¹⁴ Cm using the oxide film as a mask. P-type regions 116 and 117 are formed by ion-implanting boron into the epitaxial layer 110B with an acceleration voltage of ^-2 and a dose amount, and thermally diffusing for 30 minutes in a nitrogen gas atmosphere at 1,000 ° C. Using the oxide film as a mask, ion is implanted into the epitaxial layer 110B with an acceleration voltage of 50 KeV, 1 × 10 ¹⁵ Cm ⁻² , and a dose amount, followed by thermal diffusion for 30 minutes in a nitrogen gas atmosphere at 1,000 ° C. ^After forming the ⁺ type regions 128, 129 and 130, the gate oxide film 120B and the capacitor forming oxide film 120C are formed, and the gate electrode 131 is made of molybdenum silicide (MoSi) of 1.5 mu m in width, for example. To form. Subsequently, using the gate 131 as a mask, arsenic is ion-implanted into the epitaxial layer 110B at an acceleration voltage and dose of 3.5KeV, 1 × 10 ¹⁵ Cm ⁻² , and 30 at a nitrogen gas atmosphere of 900 ° C. Thermal diffusion is performed for a minute to form n-type regions 125 and 126. In addition, arsenic is ion-implanted into the P-type regions 116 and 117 at an acceleration voltage of 35 KeV, 1 × 10 ¹⁵ Cm ⁻² , and an amount of dose, and thermally diffused in nitrogen gas at 1,000 ° C. for 20 minutes to form an n-type region 118. To form 119.

Subsequently, the oxide film is patterned to form a connection hole, the oxide film 120A is formed by thermal oxidation, and an aluminum film is formed on the oxide film 120 to pattern the film, thereby forming the wiring electrodes 121-124 and 132-137. To form.

As a result of actually manufacturing a gain control amplifier circuit having the structure shown in FIG. 16 and measuring its characteristics, the capacitor 43 is about 50 PF, and the MOSFET 21 is a front end of a conventional dual gate MOSFET (FIG. 1). It has the same high frequency characteristics as the MOSFET installed in it, and the current characteristic of the front-side transistor 41 of the Darlington-connected bipolar transistor is about ffe, and the frequency characteristic is about f _T = 1GHZ, and the current characteristic is the collector current. Was maintained to about 50 mA.

Also, the current amplification of each of the darlington connected bipolar transistors 41 and 42 was about 100 hfe. In this case, since the base current for gain control is extremely small and does not require a base input resistance for base current control, a bad effect of the base input resistance (the base potential is changed in a direction that obstructs it when the collector current increases). This reduces the concern that the apparent equivalent resistance of the bipolar transistor is increased. Accordingly, it was confirmed that the third-order distortion component of the input / output characteristic was further improved than the characteristic of the circuit of FIG. 8 shown by a dotted line in FIG.

On the other hand, the gain control amplifier circuit shown in FIG. 17 uses a 1n-type silicon substrate 150 as compared with the gain control amplifier circuit of FIG. 16, and the P-type for the base region of the bipolar transistor on a part of the surface of the second substrate 150. The regions 156 and 157, the anode regions P ⁺ type regions 158 and 159 of the bidirectional diode, and the P ⁺ region 160 for one electrode of the capacitor 143 are formed on the three substrates 150. P-type well region 165 is formed to form n-type regions 166 and 167 for MOSFET source and drain regions in the well region 165, and (4) V (vanadium), for example, on the pushing surface of the substrate 150. A metal layer base 168 having a four-layer structure of -Ni (nickel) -AuGeSb (gold germanium antimony) -Au (gold) is different. Since otherwise, it is the same and attaches | subjects the same code | symbol as FIG. 16, and abbreviate | omits description.

As described above, when the signal processing circuit according to the present invention is used as a gain control amplifier circuit, for example, the third order distortion component of the input / output characteristic can be significantly reduced, and the high frequency amplification gain controlled by AGC (Automatic Gein Control) feedback voltage It can be used suitably for a circuit. In addition, even when used in a mixed circuit and the like, there is an advantage that the output signal is particularly small with the third distortion.

Claims (10)

Means (1) for receiving a first signal, a first transistor connected to the means (1) for receiving a first signal, means (3) for receiving a second signal, and means (4) for outputting an output signal And a second transistor connected to the first transistor in series and supplied with a second signal and a second transistor connected to the output means 4 to process the first signal based on the second signal. In the signal processing circuit, the first transistor is a MOSFET (insulated gate type field effect transistor: 21) to which a predetermined potential is applied to one end of a current path while a gate is connected to the means 1 for receiving the first signal. The second transistor is connected to one end of the collector emitter bus to one end of the other current path of the first transistor 21 while the other end of the collector-emitter passage is connected to the output means 4, The base is the second signal input means ( 3) an NPN type bipolar transistor (22) connected to said 3 < 2 > to control a base current by the second signal. 2. The gain control according to claim 1, wherein the signal processing circuit amplifies the first signal applied to the gate of the MOSFET 21 with a gain corresponding to a second signal applied to the base of the NPN transistor 22. A signal processing circuit characterized in that it can be applied to the amplifier circuit. The signal processing circuit of claim 1, wherein the signal processing circuit is applicable to a mixing circuit for mixing a first signal applied to the gate of the MOSFET 21 and a second signal applied to the base of the NPN transistor 22. Signal processing circuit, characterized in that. The signal processing circuit according to claim 1, wherein the MOSFET (21) is an N-channel growth type MOSFET. The signal processing circuit according to claim 1, wherein said MOSFET (21) is a depletion / growth MOSFET. The signal processing circuit according to claim 1, wherein said NPN type transistor (22) is a Darlington transistor comprising at least two transistors (41) (42) connected by Darlington. 7. The signal processing circuit according to claim 6, wherein the NPN transistor (41) and the MOSFET (21) are formed using the same bipolar / MOS common processing on the same semiconductor pellet. 8. The two NPN transistors 41 and 42 have n-type regions 114 and 115 formed on the P-type silicon substrates 110A and 110B as common collectors. The two P-type regions 116 and 117 formed in the regions 114 and 115 are respectively bases, and the second n-type regions 118 and 119 formed in the two P-type regions 116 and 117 Each of the two emitter regions is an emitter region, and the base of one of the two NPN transistors 41 and 42 and the emitter of the other NPN transistor 42 are connected by a wiring 123. The MOSFET 21 is also formed on the P-type substrates 110A and 110B, and the drain of the MOSFET 21 and the emitter of the NPN transistor 41 are connected by a wiring 124. Signal processing circuit, characterized in that. 2. The terminal of claim 1, wherein one end of the collector current path of the NPN transistor 22 is connected, the other end of the current path is connected to the base of the NPN transistor 22, and a gate is supplied with the second signal. And a MOSFET (61) connected to the means (3) to control the base current of the NPN transistor (22) based on the second signal. 2. The NPN transistor 22 has two NPN transistors 71 and 72 connected thereto, and one end of the current path is connected to the collector connection point of the two NPN transistors 71 and 72. The other end of the current path is connected to the base of the NPN transistor 72 and the gate is connected to the means 3 for receiving the second signal, and the NPN is based on the second signal applied to the gate. And a MOSFET (73) for controlling the base current of the type transistor (72).

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