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KR860006137A - 반도체 집적회로 - Google Patents

반도체 집적회로

Info

Publication number
KR860006137A
KR860006137A KR1019860000085A KR860000085A KR860006137A KR 860006137 A KR860006137 A KR 860006137A KR 1019860000085 A KR1019860000085 A KR 1019860000085A KR 860000085 A KR860000085 A KR 860000085A KR 860006137 A KR860006137 A KR 860006137A
Authority
KR
South Korea
Prior art keywords
integrated circuit
semiconductor integrated
semiconductor
circuit
integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
KR1019860000085A
Other languages
English (en)
Other versions
KR890004958B1 (ko
Inventor
다까야스 사꾸라이
데즈야 이즈까
Original Assignee
가부시끼가이샤 도오시바
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 가부시끼가이샤 도오시바 filed Critical 가부시끼가이샤 도오시바
Publication of KR860006137A publication Critical patent/KR860006137A/ko
Application granted granted Critical
Publication of KR890004958B1 publication Critical patent/KR890004958B1/ko
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1057—Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1084—Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption
    • H03K19/0013—Arrangements for reducing power consumption in field effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00315—Modifications for increasing the reliability for protection in field-effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00346—Modifications for eliminating interference or parasitic voltages or currents
    • H03K19/00361—Modifications for eliminating interference or parasitic voltages or currents in field effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
    • H03K19/0948—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET using CMOS or complementary insulated gate field-effect transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Logic Circuits (AREA)
  • Electronic Switches (AREA)
  • Dram (AREA)
KR1019860000085A 1985-01-26 1986-01-09 반도체 집적회로 Expired KR890004958B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP60013068A JPH0738583B2 (ja) 1985-01-26 1985-01-26 半導体集積回路
JP60-13068 1985-01-26

Publications (2)

Publication Number Publication Date
KR860006137A true KR860006137A (ko) 1986-08-18
KR890004958B1 KR890004958B1 (ko) 1989-12-02

Family

ID=11822824

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019860000085A Expired KR890004958B1 (ko) 1985-01-26 1986-01-09 반도체 집적회로

Country Status (5)

Country Link
US (2) US4740713A (ko)
EP (1) EP0190027B1 (ko)
JP (1) JPH0738583B2 (ko)
KR (1) KR890004958B1 (ko)
DE (1) DE3688088T2 (ko)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113835007A (zh) * 2020-06-08 2021-12-24 长鑫存储技术有限公司 热载流效应耐受度的测试方法

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JPH0738583B2 (ja) * 1985-01-26 1995-04-26 株式会社東芝 半導体集積回路
US4709162A (en) * 1986-09-18 1987-11-24 International Business Machines Corporation Off-chip driver circuits
US4736117A (en) * 1986-11-14 1988-04-05 National Semiconductor Corporation VDS clamp for limiting impact ionization in high density CMOS devices
JP2585599B2 (ja) * 1987-06-05 1997-02-26 株式会社日立製作所 出力インタ−フエ−ス回路
US4806801A (en) * 1987-08-27 1989-02-21 American Telephone And Telegraph Company, At&T Bell Laboratories TTL compatible CMOS input buffer having a predetermined threshold voltage and method of designing same
US4782250A (en) * 1987-08-31 1988-11-01 International Business Machines Corporation CMOS off-chip driver circuits
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JPH01233755A (ja) * 1988-03-14 1989-09-19 Nec Corp 半導体集積回路装置
JPH0716158B2 (ja) * 1988-05-13 1995-02-22 日本電気株式会社 出力回路およびそれを用いた論理回路
IT1225607B (it) * 1988-07-06 1990-11-22 Sgs Thomson Microelectronics Circuito logico cmos per alta tensione
JPH07109859B2 (ja) * 1988-09-03 1995-11-22 日本電気株式会社 Ｍｏｓ型半導体集積回路装置
US5057715A (en) * 1988-10-11 1991-10-15 Intel Corporation CMOS output circuit using a low threshold device
JPH02159818A (ja) * 1988-12-13 1990-06-20 Toshiba Corp 半導体集積回路
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US5089728A (en) * 1989-09-06 1992-02-18 National Semiconductor Corporation Spike current reduction in cmos switch drivers
US4963771A (en) * 1989-09-12 1990-10-16 Samsung Semiconductor TTL/CMOS level translator
JPH03214659A (ja) * 1990-01-18 1991-09-19 Mitsubishi Electric Corp 電界効果形半導体装置の電源電圧設定部
US5239237A (en) * 1990-02-14 1993-08-24 Zilog, Inc. Control circuit having outputs with differing rise and fall times
US5187686A (en) * 1990-02-14 1993-02-16 Zilog, Inc. Control circuit having outputs with differing rise and fall times
US5214602A (en) * 1990-04-06 1993-05-25 Mosaid Inc. Dynamic memory word line driver scheme
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DE4103309A1 (de) * 1991-02-04 1992-08-06 Mikroelektronik Und Technologi Schaltungsanordnung zur ansteuerung von wortleitungen in halbleiterspeichern
EP0571512A1 (en) * 1991-02-12 1993-12-01 Analog Devices, Inc. Gain linearity correction circuit for mos circuits
JP3556679B2 (ja) 1992-05-29 2004-08-18 株式会社半導体エネルギー研究所 電気光学装置
JPH04341009A (ja) * 1991-05-17 1992-11-27 Nec Corp 半導体集積回路装置
KR940009696B1 (ko) * 1991-10-08 1994-10-15 현대전자산업주식회사 열 캐리어 방지 회로
US5274276A (en) * 1992-06-26 1993-12-28 Micron Technology, Inc. Output driver circuit comprising a programmable circuit for determining the potential at the output node and the method of implementing the circuit
US5389842A (en) * 1992-08-10 1995-02-14 Nippon Steel Semiconductor Corporation Latch-up immune CMOS output driver
US5486778A (en) * 1993-03-10 1996-01-23 Brooktree Corporation Input buffer for translating TTL levels to CMOS levels
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US5406140A (en) * 1993-06-07 1995-04-11 National Semiconductor Corporation Voltage translation and overvoltage protection
DE4334513C1 (de) * 1993-10-09 1994-10-20 Itt Ind Gmbh Deutsche CMOS-Schaltung mit erhöhter Spannungsfestigkeit
US5465054A (en) * 1994-04-08 1995-11-07 Vivid Semiconductor, Inc. High voltage CMOS logic using low voltage CMOS process
JP3407975B2 (ja) * 1994-05-20 2003-05-19 株式会社半導体エネルギー研究所 薄膜半導体集積回路
US5682116A (en) * 1994-06-07 1997-10-28 International Business Machines Corporation Off chip driver having slew rate control and differential voltage protection circuitry
US5418476A (en) * 1994-07-28 1995-05-23 At&T Corp. Low voltage output buffer with improved speed
KR0124141B1 (ko) * 1994-12-29 1998-10-01 김광호 반도체 메모리장치의 데이타 출력 버퍼회로
US5835970A (en) * 1995-12-21 1998-11-10 Cypress Semiconductor Corp. Burst address generator having two modes of operation employing a linear/nonlinear counter using decoded addresses
US5903174A (en) * 1995-12-20 1999-05-11 Cypress Semiconductor Corp. Method and apparatus for reducing skew among input signals within an integrated circuit
US6411140B1 (en) 1995-12-20 2002-06-25 Cypress Semiconductor Corporation Method and apparatus for reducing skew between input signals and clock signals within an integrated circuit
US6043684A (en) * 1995-12-20 2000-03-28 Cypress Semiconductor Corp. Method and apparatus for reducing skew between input signals and clock signals within an integrated circuit
US5604449A (en) * 1996-01-29 1997-02-18 Vivid Semiconductor, Inc. Dual I/O logic for high voltage CMOS circuit using low voltage CMOS processes
KR100396831B1 (ko) * 1996-02-26 2003-11-17 주식회사 하이닉스반도체 절전형인버터회로
GB2349998B (en) * 1996-05-28 2001-02-28 Altera Corp Techniques of fabricating integrated circuits having interfaces compatible with different operating voltage condotions
US6147511A (en) 1996-05-28 2000-11-14 Altera Corporation Overvoltage-tolerant interface for integrated circuits
US5874836A (en) * 1996-09-06 1999-02-23 International Business Machines Corporation High reliability I/O stacked fets
JP4036923B2 (ja) * 1997-07-17 2008-01-23 株式会社半導体エネルギー研究所 表示装置およびその駆動回路
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113835007A (zh) * 2020-06-08 2021-12-24 长鑫存储技术有限公司 热载流效应耐受度的测试方法
CN113835007B (zh) * 2020-06-08 2022-09-20 长鑫存储技术有限公司 热载流效应耐受度的测试方法

Also Published As

Publication number Publication date
EP0190027A2 (en) 1986-08-06
DE3688088T2 (de) 1993-07-29
KR890004958B1 (ko) 1989-12-02
JPH0738583B2 (ja) 1995-04-26
DE3688088D1 (de) 1993-04-29
US4740713A (en) 1988-04-26
EP0190027A3 (en) 1988-09-28
JPS61172435A (ja) 1986-08-04
US4857763A (en) 1989-08-15
EP0190027B1 (en) 1993-03-24

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