KR20130125000A - Apparatus and method for implementation of aes encryption using shared pipeline - Google Patents

Abstract

The present invention relates to an AES encryption implementation method and apparatus therefor sharing a pipeline. The AES encryption implementation method includes a plurality of high-speed WLAN encryption hardware in consideration of hardware requirements such as processing speed, driving frequency, or hardware size. Efficient cryptographic hardware design that enables high-speed data processing while reducing hardware logic size by using a mixture of a pipeline structure that uses hardware to process different data at each stage, and a shared structure that processes data by using one hardware in common do.

Description

Apparatus and method for implementation of AES encryption using shared pipeline}

The present invention relates to an implementation technology and a device of AES (Advanced Encryption Standard), which is a fundamental technology of a GCM (Galois / Counter Mode) encryption method used to provide a security function of a high-speed WLAN system.

Currently, the commonly used WLAN uses the 2.4GHz band and provides a maximum speed of 150Mbps. In the early years, WLANs have made rapid leaps compared to 11MHz, but the amount of data sent and received over the network is increasing exponentially as IT technology advances. As the use of wireless LAN becomes more common due to the ease of use, the 2.4GHz band is saturated, and the amount of data transmitted through the wireless LAN increases as network usage increases, such as cloud computing and video data transmission. The transmission rate required for this is also increasing. In addition, the importance of security is increasing as the amount of personal information transmitted over the network increases. As a result, new wireless LAN standards are being created to support strong security and high-speed data communication. The 2.4GHz and 5GHz bands used in the past are saturated by devices using wireless LANs and other standards to improve data transmission speed. As the limits are raised, new frequency bands are needed for high-speed data communications.

In addition, the CCS (Counter Mode with Cipher Block Chaining Message Authentication Code) encryption method based on AES (Advanced Encryption Standard) used in the existing wireless LAN has a driving frequency to increase the data processing speed due to the algorithm structure in which output data is fed back to the input. In the hardware implementation, the driving voltage must be increased in order to increase the driving frequency. The power consumption increases because the power consumption increases in proportion to the driving frequency and increases in proportion to the square of the driving voltage. In addition, power consumption increases in proportion to the hardware logic size, and standby power consumption and production price increase together. Therefore, the hardware logic size must be reduced while the driving frequency must be lowered.

As the frequency band used in the wireless LAN is saturated as described above, a new standard for a new high-speed wireless LAN using a new frequency range of 60 GHz is newly standardized. Since the AES-based CCM encryption method is not suitable for high-speed data encryption, low power and high speed In order to support data communication, AES-based GCM encryption method that can apply pipeline structure is used.

GCM encryption method based on AES has the disadvantage of increasing the hardware size by using a pipelined structure to achieve high-speed data processing without increasing the driving frequency, but not sharing the same hardware logic.

Embodiments of the present invention provide a method and apparatus for implementing AES encryption sharing a pipeline.

In the embodiment of the present invention, a hardware logic size is used by using a mixture of a pipeline structure for processing different data at each stage by using a plurality of hardware and a shared structure for processing data using a single hardware in common. The present invention provides a method and apparatus for designing an efficient encryption hardware capable of reducing data speed and processing at high speed.

Embodiments of the present invention provide a method and apparatus for configuring hardware in a hardware size optimized for hardware requirements.

According to an embodiment of the present invention, a method for implementing AES encryption sharing a pipeline includes: identifying hardware requirements, setting a number of round processing units that satisfy the hardware requirements, and performing rounding required for AES encryption. Checking the number and setting the number of rounds to be processed by each of the round processing units if the required number of rounds is larger than the number of round processing units.

An apparatus for implementing AES encryption sharing a pipeline according to an embodiment of the present invention includes a requirement confirmation unit for confirming hardware requirements, a scale setting unit for setting a number of round processing units that satisfy the hardware requirements, and an AES. And a round setter for checking the number of rounds required for encryption and a shared setter for setting the number of rounds processed by each of the round processors if the number of rounds required is larger than the number of rounds.

The AES encryption device sharing a pipeline according to an embodiment of the present invention receives the round processing units and the encryption key sharing a predetermined number of round processing, generates an encryption key corresponding to each round, and generates the generated encryption. And a key development unit providing a key to a round processing unit for processing a corresponding round, wherein the round processing units are connected in a pipeline structure according to the processing order of the rounds to be processed in each round.

The present invention relates to an AES encryption implementation method and apparatus for sharing a pipeline, and a pipeline structure for processing different data in each step using multiple hardware when configuring a high-speed WLAN encryption hardware, and one hardware in common It is possible to design efficient cryptographic hardware that enables high-speed data processing while reducing hardware logic size by using a shared structure that processes data using the same.

1 shows an example of an AES algorithm used for GCMP encryption,
2 is a diagram illustrating a configuration of an AES encryption device based on shared hardware;
3 is a diagram illustrating a configuration of a pipeline-based AES encryption device;
4 is a diagram illustrating a configuration of a shared pipeline based AES encryption device that shares round logic twice in accordance with an embodiment of the present invention;
5 is a diagram illustrating a configuration of a shared pipeline based AES encryption apparatus that shares round logic four times according to an embodiment of the present invention;
6 is a flowchart illustrating a process of designing an AES encryption device according to hardware requirements in an AES encryption implementation device according to an embodiment of the present invention;
7 is a diagram illustrating a configuration of an AES encryption apparatus based on a shared pipeline according to an embodiment of the present invention;
8 is a diagram illustrating a configuration of an AES encryption implementation apparatus according to an embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The AES encryption algorithm is a block encryption algorithm that processes a set of blocks of a certain number of bits at once. In order to encrypt a long plain text, the AES encryption algorithm repeatedly converts the entire plain text into a cipher text.

There are various methods of generating cipher text using AES encryption algorithm. In conventional wireless LAN, CCMP (Counter Mode with Cipher Block Chaining Message Authentication Code Protocol) is used, but as it does not allow high-speed data processing as described above, 802.11ad and Likewise, the Galois / Counter Mode Protocol (GCMP) is used in systems that require high-speed data processing of several Gbits or more.

In the present invention, the AES algorithm used for GCMP encryption includes an AddRoundKey function for adding an input plaintext block and an encryption key, a SubBytes function for substituting a predetermined table value and input data, and shifting the data in units of rows. ShiftRows function, MixColumns function that mixes column by column through matrix operation. As shown in Fig. 1, only the addition function is used in the initial round, and 4 functions are used during the 1-9 rounds. All are applied, and in the final round three functions are applied except for the blend function.

1 is a diagram illustrating an example of an AES algorithm used for GCMP encryption.

Referring to FIG. 1, when the AES encryption device receives the plain text block in step 110, the AES encryption device performs an addition function of adding an encryption key corresponding to each round to the plain text block received in step 112 corresponding to the initial round.

In addition, the AES encryption apparatus performs a round once by performing a substitution function of 114 steps, a shift function of 116 steps, a mixing function of 118 steps, and an addition function of 120 steps.

Then, the AES cryptography apparatus checks whether the next round is the last round in step 122, and if not the last round, repeats step 120 in step 114 and consequently performs the ninth round in the first round.

In addition, the AES encryption apparatus performs a substitution function of 124, a shift function of 126, and an addition function of 128 in the final round.

The present invention relates to a method for implementing AES for encryption processing in a high speed communication system requiring AES-based encryption of high-speed data of several Gbits or more. Pipeline structures that use more than one round logic and reuse the round logic on the pipeline more than once to reduce hardware size.

In hardware implementation of the AES encryption algorithm, the AddRoundKey function, SubBytes function, ShiftRows function, and MixColumns function, which are used repeatedly, are called round logic. When using a shared hardware structure that is implemented and repeated as a function of, the hardware logic size is reduced, but the high frequency should be increased to increase the data rate. However, the complex internal structure places a limit on increasing the driving frequency. In order to overcome the limitation of driving frequency, a pipelined structure that uses a round logic in parallel to increase the data processing speed without increasing the driving frequency is adopted. However, in the pipelined structure, the hardware size increases and power consumption increases.

According to the present invention, which takes advantage of the pipeline structure that can lower the driving frequency and the shared hardware structure that can reduce the hardware size, the driving frequency can be lowered and the hardware logic size can be reduced compared to the pipeline structure compared to the shared hardware structure. .

Hereinafter, a shared pipeline method will be described in detail with reference to the accompanying drawings, taking an AES implementation for implementing GCMP used in the 802.11ad standard as an example.

2 is a diagram illustrating a configuration of an AES encryption apparatus based on shared hardware.

Referring to FIG. 2, the AES encryption apparatus 200 based on shared hardware includes a key deployment unit 210 and a round logic 220 for receiving an encryption key and generating an encryption key corresponding to each round. Since the AES encryption apparatus 200 uses one round logic 220 repeatedly from the initial round to the last round, after the 128-bit plain text data block is input once, no more plain text blocks are input until the final cipher text block is output. Can't. If one clock is consumed after one round, the 128-bit plaintext block entered will go through 11 rounds and the next data plaintext block can be entered after 11 clocks output by the ciphertext. Same as>

[Equation 1]

Data rate = frequency / 11 (clock) * 128 (bit)

Therefore, the AES encryption device 200 should operate at 580.65MHz, although the operating frequency of the AES encryption device 200 should be 580.65MHz in order to support 6756.75Mbps, which is the highest data rate in the IEEE 802.11ad ultra high-speed wireless LAN standard.

3 is a diagram illustrating a configuration of a pipeline-based AES encryption device.

Referring to FIG. 3, the pipeline-based AES encryption apparatus 300 includes a key deployment unit 310 and eleven round logics 320-330 that receive an encryption key and generate an encryption key corresponding to each round. . Since the AES encryption apparatus 300 has separate hardware from the initial round to the final round, 128 bits of plain text data blocks can be input every clock, and the cipher text block is output 11 hours after the first 128 bits of plain text data blocks are input. At the beginning, the ciphertext can be output every clock. If one clock is consumed after one round, the 128-bit plaintext block is processed as 11 rounds and output as ciphertext, and the data plaintext block can be input for each clock. Is the same as

 &Quot; (2) "

Data throughput = frequency * 128 (bit)

Therefore, the AES encryption device 300 is 52.8MHz operating frequency of the operating frequency of the AES encryption device 300 in order to support the highest data rate 6756.75Mbps in the IEEE 802.11ad ultra-high-speed wireless LAN standard, but the driving frequency is low, but the hardware logic Its size is about 11 times larger than shared hardware architecture. In addition, the AES encryption device 300 can exhibit the best performance only when the plain text block input or cipher text output interface is 128 bits, and a 64 bit or 32 bit interface is suitable for a speed of 6756.75 Mbps due to hardware complexity.

4 is a diagram illustrating a configuration of a shared pipeline-based AES encryption apparatus that shares round logic twice in accordance with an embodiment of the present invention.

Referring to FIG. 4, the AES encryption apparatus 400 includes a key deployment unit 410 and six round logics 420-426 that receive an encryption key and generate an encryption key corresponding to each round.

AES encryption device 400 is a structure that uses a single round logic (421-426) twice twice without a separate hardware from the initial round to the final round, it is possible to input a 64-bit plain text data block every clock It collects two inputs internally and processes them in 128bit units. After all of the first 128-bit plaintext block is input, the ciphertext block starts to be output 11 hours later, and the ciphertext block can be output every 2 clocks. If one clock is consumed in one round, the 128-bit plaintext block is processed as 11 rounds and output as ciphertext, and the data plaintext block can be input every 2 clocks. Same as>

&Quot; (3) "

Data throughput = frequency * 128 (bit) / 2

Therefore, in order to support the highest data rate of 6756.75 Mbps in the IEEE 802.11ad ultra high-speed wireless LAN standard, the AES encryption device 400 needs to operate at an operating frequency of 105.6 MHz, resulting in low driving frequency and hardware logic size. Can be reduced to about 1/2 of the pipeline structure.

FIG. 5 is a diagram illustrating a configuration of a shared pipeline based AES encryption apparatus that shares round logic four times according to an embodiment of the present invention.

Referring to FIG. 5, the AES encryption apparatus 500 includes a key deployment unit 510 and four round logics 520-523 that receive an encryption key and generate an encryption key corresponding to each round.

The AES encryption device 500 is a structure that uses a single round logic (521-523) twice or four times and repeats a 32-bit plaintext data block every clock from the initial round to the final round without separate hardware. Input is possible, and four inputs are collected internally and processed in 128-bit units.

Therefore, the AES encryption device 500 using 32 bits increases the driving frequency required to process data of about 6756.75 Mbps to 210 MHz, but the hardware size is reduced to 1/4 compared to the pipeline structure.

4 and 5, the shared pipeline structure according to the present invention can be implemented in a hardware structure optimized for the system by adjusting the number of pipelines and the number of repetitions according to the amount of input / output data or the data transmission rate required by the system.

6 is a flowchart illustrating a process of designing an AES encryption device according to hardware requirements in an AES encryption implementation device according to an embodiment of the present invention.

Referring to FIG. 6, the AES encryption implementing apparatus checks hardware requirements at step 610. In this case, the hardware requirement may be at least one of processing speed, driving frequency, or size of hardware.

In operation 620, the AES encryption implementation apparatus sets the number of round processing units that satisfy hardware requirements.

For example, when the hardware requirement is a processing speed, the AES encryption implementer may set the number of round processing units to satisfy the processing speed and to have the lowest driving frequency and the smallest hardware size.

As another example, when the hardware requirement is hardware size, the AES encryption implementer may set the number of round processing units to satisfy the hardware size and to have the lowest driving frequency and the fastest processing speed.

As another example, when the hardware requirement is a driving frequency, the AES encryption implementer may set the number of round processing units to satisfy the driving frequency and to have the smallest hardware and the fastest processing speed.

As another example, the AES encryption implementer may set the number of round processing units to have the lowest driving frequency while satisfying the processing speed and the hardware size when the hardware requirement is the processing speed and the size of the hardware.

As another example, when the hardware requirements are hardware size and driving frequency, the AES encryption implementer may set the number of round processing units to satisfy the hardware size and driving frequency and achieve the fastest processing speed.

As another example, when the hardware requirement is a driving frequency and a processing speed, the AES encryption implementer may set the number of round processing units to satisfy the driving frequency and the processing speed and to have the smallest hardware.

In operation 630, the AES encryption implementing apparatus checks the number of rounds required for AES encryption. In general, the final round of AES encryption consists of 11 rounds.

In operation 640, if the number of rounds required is larger than the number of round processors, the AES encryption implementer sets the number of rounds processed by each of the round processors. At this time, the AES encryption implementation sets the minimum number of rounds processed by each of the round processing units.

The AES encryption implementation includes a cryptographic device comprising a key deployment unit that connects round processing units that share as many rounds as set in step 650 in a pipeline, and provides encryption keys corresponding to the rounds to each of the round processing units. Design as shown in 7.

7 is a diagram illustrating a configuration of an AES encryption apparatus based on a shared pipeline according to an embodiment of the present invention.

Referring to FIG. 7, the AES encryption apparatus 700 based on a shared pipeline includes a key deployment unit 710 and round processing units 720-722.

The key development unit 710 receives the encryption key, generates an encryption key corresponding to each round, and provides the generated encryption key to a round processing unit that processes the corresponding round.

The round processing units 720-722 share a predetermined number of round processings. In this case, the number of round processors 720 to 722 is designed to satisfy a hardware requirement including at least one of a processing speed, a driving frequency, or a size of hardware.

The round processing units 720-722 are connected in a pipeline structure according to the processing order of the rounds processed by each round processing unit 720-722.

At this time, the round processing unit 720 located first among the round processing units 720 to 722 may process only the initial round without using the sharing base. The initial round consists only of the addition function that adds the encryption key. Since the addition function is small in hardware size, the additional function is preferable to reduce the overall hardware size and improve the processing speed.

8 is a diagram illustrating a configuration of an AES encryption implementation apparatus according to an embodiment of the present invention.

Referring to FIG. 8, the AES encryption implementing apparatus 800 includes a requirement check unit 810, a scale setting unit 820, a round checking unit 830, a sharing setting unit 840, and a design unit 850. .

Requirements check unit 810 checks the hardware requirements. In this case, the hardware requirement may be at least one of processing speed, driving frequency, or size of hardware.

The scale setting unit 820 sets the number of round processing units 720-722 that satisfy the hardware requirements.

For example, when the hardware requirement is the processing speed, the scale setting unit 820 may set the number of round processing units 720 to 722 to satisfy the processing speed and to have the lowest driving frequency and the smallest hardware size.

As another example, when the hardware requirement is hardware size, the scale setting unit 820 may set the number of round processing units 720-722 to satisfy the hardware size and to have the lowest driving frequency and the fastest processing speed.

As another example, when the hardware requirement is the driving frequency, the scale setting unit 820 may set the hardware of the smallest size and the number of the round processing units 720-722 to have the fastest processing speed while satisfying the driving frequency.

As another example, when the hardware requirement is processing speed and the size of hardware, the scale setting unit 820 adjusts the number of round processing units 720-722 to satisfy the processing speed and the size of the hardware and have the lowest driving frequency. Can be set.

As another example, when the hardware requirements are hardware size and driving frequency, the scale setting unit 820 may set the number of round processing units 720-722 to satisfy the hardware size and driving frequency and to achieve the fastest processing speed.

As another example, when the hardware requirement is the driving frequency and the processing speed, the scale setting unit 820 may set the number of the round processing units 720 to 722 to satisfy the driving frequency and the processing speed and to have the smallest hardware. .

The round checker 830 confirms the number of rounds required for AES encryption. In general, the final round of AES encryption consists of 11 rounds.

If the number of rounds required is larger than the number of round processors 720-722, the sharing setting unit 840 sets the number of rounds processed by each of the round processors 720-722. The sharing setting unit 840 sets the minimum number of rounds processed by each of the round processing units 720-722.

The design unit 850 is connected to the round processing unit 720-722 sharing the set number of rounds in a pipeline, and the key deployment unit 710 providing an encryption key corresponding to the round to each of the round processing unit 720-722 Design an encryption device 700 consisting of).

The methods according to embodiments of the present invention may be implemented in the form of program instructions that can be executed through various computer means and recorded in a computer-readable medium. The computer-readable medium may include program instructions, data files, data structures, and the like, alone or in combination. The program instructions recorded on the medium may be those specially designed and constructed for the present invention or may be available to those skilled in the art of computer software.

As described above, the present invention has been described by way of limited embodiments and drawings, but the present invention is not limited to the above embodiments, and those skilled in the art to which the present invention pertains various modifications and variations from such descriptions. This is possible.

Therefore, the scope of the present invention should not be limited to the described embodiments, but should be determined by the equivalents of the claims, as well as the claims.

Claims (20)

Identifying hardware requirements;
Setting a number of round processing units that satisfy the hardware requirements;
Identifying the number of rounds required for AES encryption; And
If the required number of rounds is larger than the number of round processing units, a sharing setting step of setting the number of rounds processed by each of the round processing units;
How to implement AES encryption sharing a pipeline.
The method of claim 1,
Designing an encryption device comprising a key deployment unit for connecting the round processing units sharing the number of rounds set in the sharing setting step by a pipeline, and providing an encryption key corresponding to the round to each of the round processing units. Containing
How to implement AES encryption sharing a pipeline.
The method of claim 1,
The above hardware requirements are:
At least one of a processing speed, a driving frequency, or a hardware size
How to implement AES encryption sharing a pipeline.
The method of claim 1,
Setting the number of round processing unit,
When the hardware requirement is the processing speed, the number of the round processing units is set to satisfy the processing speed and to have the lowest driving frequency and the smallest size hardware.
How to implement AES encryption sharing a pipeline.
The method of claim 1,
Setting the number of round processing unit,
When the hardware requirement is a hardware size, the number of the round processing unit is set to satisfy the hardware size and to have the lowest driving frequency and the fastest processing speed.
How to implement AES encryption sharing a pipeline.
The method of claim 1,
Setting the number of round processing unit,
If the hardware requirement is a driving frequency, the hardware of the smallest size while satisfying the driving frequency and the number of the round processing unit to set the processing speed as fast as possible
How to implement AES encryption sharing a pipeline.
The method of claim 1,
Setting the number of round processing unit,
If the hardware requirement is the processing speed and the size of the hardware, the number of the round processing unit is set to have the lowest driving frequency while satisfying the processing speed and the size of the hardware.
How to implement AES encryption sharing a pipeline.
The method of claim 1,
Setting the number of round processing unit,
If the hardware requirement is a hardware size and a driving frequency, the number of the round processing unit is set to satisfy the hardware size and the driving frequency and to maximize the processing speed.
How to implement AES encryption sharing a pipeline.
The method of claim 1,
Setting the number of round processing unit,
When the hardware requirement is the driving frequency and the processing speed, the number of the round processing unit is set to satisfy the driving frequency and the processing speed so that the hardware is as small as possible.
How to implement AES encryption sharing a pipeline.
The method of claim 1,
Setting the number of rounds to be processed by each of the round processing units,
To set the minimum number of rounds to be processed by each of the round processing units
How to implement AES encryption sharing a pipeline.
The method of claim 1,
Setting the number of rounds to be processed by each of the round processing units,
To set the round processing unit to process only the initial round alone
How to implement AES encryption sharing a pipeline.
A requirements checking unit for checking hardware requirements;
A scale setting unit for setting the number of round processing units that satisfy the hardware requirements;
A round checking unit for checking the number of rounds required for AES encryption; And
If the required number of rounds is larger than the number of round processing unit, comprising a sharing setting unit for setting the number of rounds to be processed in each of the round processing units
AES encryption implementation that shares the pipeline.
The method of claim 12,
A design unit for designing an encryption device comprising a key deployment unit for connecting the round processing units sharing a number of rounds set by the sharing setting unit in a pipeline, and providing an encryption key corresponding to the round to each of the round processing units Containing
AES encryption implementation that shares the pipeline.
The method of claim 12,
The hardware requirements are:
At least one of a processing speed, a driving frequency, or a hardware size
AES encryption implementation that shares the pipeline.
Round processing units sharing a predetermined number of round processings; And
A key development unit for receiving an encryption key, generating an encryption key corresponding to each round, and providing the generated encryption key to a round processing unit for processing the corresponding round;
The round processing unit,
Characterized in that connected to the pipeline structure according to the processing order of the rounds to each processing
AES encryption device that shares the pipeline.
16. The method of claim 15,
Among the round processing units, the first round processing unit of the pipeline structure,
To handle only the initial round
AES encryption device that shares the pipeline.
17. The method of claim 16,
The initial round,
And an addition function added to the plaintext block that receives the generated encryption key provided from the key deployment unit.
AES encryption device that shares the pipeline.
16. The method of claim 15,
The round,
A substitution function for replacing data received from the previous round with a value of a predetermined table;
A shift function for shifting data substituted by the substitution unit by a row;
A blending function for mixing the shifted data by the shift unit in column units through a matrix operation; And
And an addition function for adding the generated encryption key provided from the key development unit to the data mixed by the mixing unit.
AES encryption device that shares the pipeline.
16. The method of claim 15,
The last round processed by the last round processing unit of the pipeline structure,
A substitution function for replacing data received from the previous round with a value of a predetermined table;
A shift function for shifting data substituted by the substitution unit by row; and
And an addition function for adding the generated encryption key provided from the key development unit to the data shifted by the shift unit.
AES encryption device that shares the pipeline.
16. The method of claim 15,
The number of round processing units sharing the predetermined number of round processing is
Designed to meet hardware requirements including at least one of processing speed, drive frequency or hardware size
AES encryption device that shares the pipeline.

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