CN105007154A - Encryption and decryption device based on AES (Advanced Encryption Standard) algorithm - Google Patents

Abstract

The invention discloses an encryption and decryption device based on an AES algorithm, relates to the technical field of information security, and solves the problem of a single AES encryption and decryption mode in the prior art. The encryption and decryption device of the present invention includes a cryptographic processing module for processing data. The cryptographic processing module includes an input logic path, a first multiplexing unit, a cryptographic function operation unit, a first demultiplexing unit, an output logic path and a second multiplexing unit. The AES mode control signal controls the selection of the input logic path to input the packet data, and selects the cryptographic function operation unit to perform forward or reverse processing on the packet data, and then controls the selection of the output logic path to output the packet data. The present invention is mainly used for encrypting and decrypting data through the AES algorithm.

Description

An encryption and decryption device based on AES algorithm

technical field

The invention relates to the technical field of information security, in particular to an encryption and decryption device based on an AES algorithm.

Background technique

AES (Advanced Encryption Standard, Advanced Encryption Standard) is a new information encryption algorithm established and used by the US NIST (National Institute of Standards and Technology, National Institute of Standards and Technology) in 2002. With the continuous improvement of modern cryptanalysis level, chip processing capability and computing technology, AES algorithm has been widely used in various industries and departments, and gradually replaced the encryption function of DES in IPSec, SSL and ATM.

At present, domestic research on algorithm implementation is usually based on software implementation. Compared with the software encryption system, the hardware encryption system has faster processing speed and is more secure and reliable. At present, the number of high-speed hardware implementations of AES is relatively small. Therefore, with the popularization and application of the AES algorithm, the hardware development of the algorithm has gradually become an important topic.

In the process of realizing the present invention, the inventor found that there are at least the following technical problems in the prior art:

The AES algorithm includes five encryption and decryption modes: ECB, CTR, OFB, CFB and CBC. However, in the current prior art, there are very few AES encryption devices that support full modes, usually only two or three types are supported. The encryption mode is relatively single, and the security and confidentiality are poor.

Contents of the invention

The invention provides an encryption and decryption device based on the AES algorithm, capable of supporting all modes of the AES encryption and decryption algorithm, and improving the security and reliability of the encryption and decryption.

The present invention provides an encryption and decryption device based on the AES algorithm, including a cryptographic processing module for processing data; the cryptographic processing module includes:

at least one input logic path for performing logic operations on input packet data;

The first multiplex selection unit is used to select one input logic path according to the AES mode control signal to output the grouped data after logic operation;

A cryptographic function operation unit, configured to select a forward or reverse cryptographic function to encrypt and decrypt the packet data according to the AES mode control signal;

The second demultiplexing unit is used to decompose the encrypted and decrypted packet data into at least one path of packet data;

At least one output logic path, used to perform logical operations on each path of decomposed grouped data;

The second multiplexing unit is configured to select one output logic path according to the AES mode control signal to output the grouped data after logic operation.

The core algorithm part of the encryption and decryption device based on the AES algorithm provided by the present invention is implemented by full hardware, supports all 5 kinds of AES encryption and decryption modes, and 3 kinds of key bit widths, can meet all the requirements for encryption and decryption of the AES algorithm, and improves data security. The security and confidentiality of encryption and decryption make the present invention have a stronger ability to resist external attacks.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings that need to be used in the description of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention. For those skilled in the art, other drawings can also be obtained based on these drawings without creative effort.

FIG. 1 is a schematic structural diagram of a cryptographic processing module in an embodiment of the present invention;

Fig. 2 is a schematic structural diagram of a forward cipher processing module in an embodiment of the present invention;

3 is a schematic structural diagram of a reverse cipher processing module in an embodiment of the present invention;

4 is a schematic structural diagram of a forward cryptographic operation unit in an embodiment of the present invention;

Fig. 5 is a schematic structural diagram of a reverse cryptographic operation unit in an embodiment of the present invention;

Fig. 6 is the processing flowchart of the forward cryptographic operation unit in Fig. 4;

Fig. 7 is the processing flowchart of the reverse cryptographic operation unit in Fig. 5;

FIG. 8 is a schematic structural diagram of an encryption and decryption device based on the AES algorithm provided by the present invention.

Detailed ways

The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

The encryption and decryption device provided by the present invention implements multiplexing of logical resources according to the characteristics of the encryption and decryption mode of the AES algorithm. From the data processing flow of AES algorithm encryption and decryption, we can see that the difference between several encryption modes lies in two points: one is the composition of the input packet data before the encryption function processing and the output packet data after processing; the other is the selected encryption function. According to the above two features, in the present invention, the pre-processed and processed data are processed by multiple logical channels. For data with the same structure before and after processing, merge and multiplex through logical channels. In this way, when encrypting and decrypting, you only need to select the relevant logical channel, and then call the forward/reverse encryption function to realize multiple AES encryption and decryption modes. The following will be described in detail in conjunction with the embodiments.

In an embodiment provided by the present invention, the encryption and decryption device based on the AES algorithm mainly improves the encryption processing module. Specifically, as shown in Figure 1, the password processing module includes:

at least one input logic path for performing logic operations on input packet data;

The first multiplex selection unit is used to select one input logic path according to the AES mode control signal to output the grouped data after logic operation;

A cryptographic function operation unit, configured to select a forward or reverse cryptographic function to encrypt and decrypt the packet data according to the AES mode control signal;

The first demultiplexing unit is used to decompose the encrypted and decrypted packet data into at least one path of packet data;

At least one output logic path, used to perform logical operations on each path of decomposed grouped data;

The second multiplexing unit is configured to select one output logic path according to the AES mode control signal to output the grouped data after logic operation.

Specifically, the cryptographic processing module further includes a second demultiplexing unit connected to the input logical path, for decomposing the input packet data into multiple paths. When the input packet data processed by the input logic paths are the same, the input packet data needs to be decomposed by the second path decomposition unit and sent to each input logic path. When the input packet data processed by the input logic paths are different, the input packet data can be directly handed over to the input logic path for processing.

Specifically, the output logical path is any one of the following output logical paths: the first input logical path is used to directly input the packet data; the second input logical path is used to perform XOR between the input packet data and the password initialization vector The data after logic operation; the third input logic path is used to input the grouped data and the output 128-bit data group of the previous stage to carry out the data after XOR logic operation; the fourth input logic path is used to directly input the key initial vector ; The fifth input logic path is used to input the data after the splicing operation of the low b-s bits of the previous stage input packet and the s bits of the previous stage ciphertext; the sixth input logic path is used to input the output 128 of the previous stage A bit data packet; a seventh input logic channel for inputting a value of the counter.

Specifically, the output logic path is any one of the following output logic paths: the first output logic path is used to directly output the packet data; the second output logic path is used to output the high s bit of the packet data and the current level plaintext The data after the XOR operation of the s bits of the s bits; the third output logic path is used to output the data after the XOR operation between the packet data and the current level plaintext; the fourth output logic path is used to output the high s bits of the packet data and the current level The data after the XOR operation of the s bits of the ciphertext; the fifth output logic path is used to output the data after the XOR operation between the packet data and the current level ciphertext; the sixth output logic path is used to output the packet data and the key The data after the XOR operation of the initial vector; the seventh output logic path, used to output the data after the XOR operation of the packet data and the input ciphertext of the previous stage.

Compared with the prior art, the present invention multiplexes the input logic channel and output logic channel of forward encryption and reverse decryption, effectively saving the hardware implementation area of the device. By configuring the input logic channel and the output logic channel, various modes of the AES algorithm can be realized. The specific implementation of various modes of the AES algorithm is described in detail in the following embodiments.

In an embodiment provided by the present invention, the cryptographic processing module is divided into forward cryptographic function processing and reverse cryptographic function processing into two independent modules. Specifically, the two modules respectively include an input logic path, a demultiplexing unit, a demultiplexing unit, and an output logic path. The specific implementation process of the two modules will be introduced in detail below.

Referring to FIG. 2 , the forward cryptographic function processing module includes seven input logic paths, two demultiplexers, two multiplexers, a forward cryptographic function computing unit, and five output logic paths. Wherein, the plaintext packet data is output as three input logical paths through the demultiplexer. The other four input logic paths have different input packet data, so there is no need to set up a demultiplexer. The outputs of the seven input logic paths are connected to the input terminals of the first multiplexer. The output end of the first multiplexer is connected to the forward encryption function operation unit; the output end of the forward encryption function operation unit is connected to the second multiplexer. The second demultiplexer breaks down into five output logic paths. Five output logic lanes are selected for output by a second multiplexer.

Among them, the seven input logic paths include: path (1), used to directly input plaintext packet data; path (2), used to input plaintext packet data and the initial vector of the password after XOR logic operation; path (3), It is used for the data after XOR logical operation of the input plaintext packet data and the output 128-bit data packet of the previous stage. Passage (4), is used for directly inputting the key initial vector IV; Passage (5), is used for inputting the data after the low b-s bit of the plaintext packet data of the previous level and the s bit of the ciphertext of the previous level are spliced; (6) is used to input the 128-bit data packet output by the previous stage; the path (7) is used to input the value of the counter. Among them, the five output logic paths include: path (8), used to directly output ciphertext packet data; path (9), used to output the data after the XOR operation of the high s bit of the ciphertext packet data and the s bit of the current level plaintext ; Passage (10), for outputting ciphertext packet data and the data after XOR operation of current level plaintext; Pathway (11), for outputting ciphertext packet data high s bit and s bit of current level ciphertext to carry out XOR operation or the data after the operation; the path (12) is used to output the data after the XOR operation between the ciphertext block data and the current level ciphertext.

Referring to FIG. 3 , the reverse cryptographic function processing module includes an input logic path, a reverse cryptographic function computing unit, a demultiplexer, three output logic paths and a multiplexer. Since the reverse processing involves only one input logic channel, the demultiplexer and multiplexer at the input can be omitted. The input logic channel is connected to the reverse encryption function operation unit; the reverse encryption function operation unit is divided into three output logic paths through the demultiplexer; the output logic path is selected for output through the multiplexer.

Wherein, the input logic path includes path (0), which is used to directly output the ciphertext packet data. Three output logic paths include: path (1), for directly outputting ciphertext block data; path (2), for outputting the data after XOR operation between plaintext block data and key initial vector IV; path (3), using The output plaintext block data and the data after the XOR operation is performed on the input ciphertext of the previous stage.

Based on the above, it can be seen that the present invention adopts the logical resource multiplexing technology to combine the same logical channels of the five modes, and at the same time separately design the involved forward cryptographic function CIPHk and reverse cryptographic function CIPH _-1 K. The input logic path and the output logic path are selected through the AES mode control signal, and the cryptographic function is called as a public module to realize 5 encryption and decryption modes of the AES algorithm. The following describes the specific ways to implement the five modes.

ECB encryption: use the path (1)(8) in Figure 2; ECB decryption: use the path (0)(1) in Figure 3.

CBC encryption: the first input 128-bit data packet adopts the path (2) (8) of Fig. 2, and the other input 128-bit data packets adopt the path (3) (8) of Fig. 2 . CBC decryption: the first output 128-bit data packet adopts the path (0)(2) of FIG. 3, and the other output 128-bit data packets adopt the path (0)(3) of FIG. 3.

CFB encryption: the first input 128-bit data packet adopts the pathway (4)(9) in Figure 2, and the other input 128-bit data packets adopt the pathway (5)(10) in Figure 2. CFB decryption: the first input 128-bit data packet adopts the path (4) (11) in Figure 2, and the other input 128-bit data packets adopt the path (5) (11) in Figure 2 .

OFB encryption: the first input 128-bit data packet adopts the path (4) (10) of Fig. 2, and other input 128-bit data packets adopt the path (6) (10) of Fig. 2 . OFB decryption: the first input 128-bit data packet adopts the path (4) (12) of Fig. 2, and other input 128-bit data packets adopt the path (6) (12) of Fig. 2 .

CTR encryption: adopt the path (7) (10) of Fig. 2. CTR decryption: adopt the path (7) (12) of Fig. 2.

It should be noted that the present invention is not limited to the above-mentioned embodiments. Any one or more encryption and decryption modes of ECB, CTR, OFB, CFB, and CBC implemented by selecting any combination of input logic channels and output logic channels are within the protection scope of the present invention. Compared with the prior art, the encryption and decryption device provided by the present invention can realize multiple encryption and decryption modes, effectively improve data security and confidentiality, and at the same time, effectively save the hardware implementation area of the device by multiplexing logic resources.

In an embodiment provided by the present invention, improvements are made to the forward cryptographic function computing unit and the reverse cryptographic function computing unit. Since the three bit-width AES algorithms correspond to the key K of 128/192/256bit, but the minimum unit of data processing is 128bit, it is only because the number of encryption and decryption data processing rounds corresponding to the different key bit width is different, respectively. 10/12/14 rounds. However, each round of processing is the same, so the present invention designs each round of processing separately and calls it as a public resource, so as to save resources and reduce the area. For different numbers of rounds, register configuration is used to control the number of public module calls processed in a single round.

Specifically, referring to FIG. 4, the forward cryptographic function operation unit includes two modules: the first operation performs S-box transformation, row transformation, column transformation, and XOR processing on the data in sequence, and is used to realize the data except the last one. Round operations for rounds other than rounds. The second operation module sequentially performs three steps of S-box transformation, row transformation, and XOR with the extended key to realize the last round of round operation.

Referring to Figure 5, the reverse cipher function operation unit includes two modules: the third operation module sequentially performs inverse row transformation, inverse S-box transformation, XOR with the extended key, and inverse column transformation processing on the data to realize the process of removing the last round The round operation of other rounds; the fourth operation module sequentially performs inverse row transformation, inverse S-box transformation, and XOR processing with the extended key to realize the last round operation.

In the prior art, the round operation process in the forward function operation unit and the reverse function operation unit is reversed. It can be seen from the above that the round operation process of the reverse function operation unit and the forward function operation unit of the present invention are not completely reversed. Therefore, compared with the prior art, the present invention has higher security.

Referring to Fig. 6 and Fig. 7, the present invention preferably adopts multi-stage pipeline design for processing round operations. As shown in Table 1, in the present invention, the round operation is preferably divided into Nr1, Nr2, Nr3, and Nr4, and the final round is 5 rounds, and the sum of the 5 rounds is Nr. Of course, it can also be divided into more stages or the number of round operations of each stage can be adjusted appropriately.

Table 1

Wherein, the number in the table indicates the number of round operations to be performed, and if it is 0, it means that the round operation of this level is not performed. The number of calculations Nr1 in the first round is uniformly allocated to 3, and the number of calculations in the fourth round Nr4 + the distribution of the final round will vary depending on the total number of rounds. The number of operations Nr2 in the second stage and the number Nr3 in the third stage are allocated as 4 if this stage of operation is required, and as 0 if this stage of operation is not performed. Each round of operation requires 1 clock cycle, and Nr1 is allocated as 3. It takes 1 clock cycle to XOR with the extended key before the execution of the Nr1 round, and it takes 4 clock cycles together with Nr1, so that when the input 128-bit data packet fills the 4-stage pipeline, it can be output every 4 clock cycles. 128-bit data grouping greatly shortens the time required for the original forward and reverse cipher functions to generate and output 128-bit grouped data in 10/12/14 clock cycles.

In an embodiment provided by the present invention, the cryptographic processing module further includes a bit width converting unit, configured to perform bit width conversion on the input block data and the output block data. Specifically, as shown in FIG. 2 , the bit width conversion unit is connected to the input end of the demultiplexer and the output end of the multiplexer. The bit width conversion unit in FIG. 3 is connected to the input end of the path (0) and the output end of the multiplexer.

In an embodiment provided by the present invention, referring to FIG. 8 , the AES encryption and decryption device further includes an interactive register module connected to the cryptographic processing module for generating the AES mode control signal C required by the cryptographic processing module according to the register configuration information. The configuration information of the register in the present invention can be obtained from the input data stream, and corresponding configuration information can also be obtained from the processor. The interactive registration module generates an AES mode control signal C according to the register configuration information, and controls the cryptographic processing module to encrypt and decrypt the block data D0 to be encrypted and decrypted and the key initialization vector IV. It should be noted that the AES mode control signal C is not only used to control the encryption and decryption mode, but also used to control the working bit width and the like.

In an embodiment provided by the present invention, the encryption and decryption device further includes a processor module connected to the interactive registration module and used for setting register configuration information. As mentioned above, the register configuration information loaded by the input data stream is actually a hardware configuration method, which has the advantage of fast operation speed, but the configuration method is relatively single and fixed. The processor module is configured by software, that is, the user can complete the register configuration by loading the corresponding configuration program in the processor module. Therefore, the configuration mode of the processor has higher flexibility than the configuration mode of the input data stream. However, the present invention adopts the combination of the two, and various working modes can be configured, which improves the operating speed of the device and also enhances the flexibility of configuration.

In an embodiment provided by the present invention, the encryption and decryption device further includes an input data selection module. The input data selection module is used to select input data streams D in different formats to enter the interactive registration module. The input data stream D contains register configuration information and data D0 to be encrypted and decrypted.

In an embodiment provided by the present invention, the encryption and decryption device further includes an interface module, configured to perform format conversion on input data streams of different formats, and the converted data streams are selected and output by the input data selection module. Wherein, the interface module includes a serial port conversion unit, a parallel port conversion unit, an SPI conversion unit and a JTAG conversion unit. Among them, the serial port conversion unit is used to convert the serial data stream into a parallel data stream, for example, convert a 1-bit data stream into a 32-bit data stream, and the parallel conversion unit is used to convert a parallel data stream into another parallel data stream , such as converting an 8-bit or 16-bit or 32-bit data stream into a 32-bit data stream. The SPI conversion unit is used to convert the data stream satisfying the SPI protocol into a parallel data stream, for example, convert a 1-bit or 2-bit or 4-bit data stream into a 32-bit data stream. The JTAG conversion unit converts the data stream satisfying the JTAG protocol into a parallel data stream, for example, converts a 1-bit data stream into a 32-bit data stream. Wherein, the JTAG conversion unit can also be used to configure the key K. The interface module in the present invention adopts data stream transmission rate matching technology to unify multiple interfaces with different rates into an interface with a fixed rate to facilitate subsequent data processing.

In an embodiment provided by the present invention, the encryption and decryption device further includes an output data selection module, which is used to control the encryption processing module to select and output forward processing data D1 or reverse processing data according to the AES mode control signal C D2. The output data selection module selects and outputs the forward/reverse processed data according to the AES mode control signal C of the interactive register, and stores them to complete the loading process of the entire data stream.

In an embodiment provided by the present invention, the encryption and decryption device further includes a storage module connected to the output data selection module for storing forward/reverse processed data.

In summary, the encryption and decryption device provided by the present invention implements the core part of the AES algorithm by using full hardware, supports all five encryption and decryption modes at the same time, can meet all the requirements for encryption and decryption, and improves data security and confidentiality . Therefore, compared with the prior art, the present invention has a stronger ability to resist external attacks. In addition, the device has multiple configuration modes, which effectively improves the flexibility of device configuration, and supports multiple data interfaces at the same time to meet the requirements of multiple data stream applications.

Those of ordinary skill in the art can understand that the implementation of all or part of the processes in the above embodiments can be completed by instructing related hardware through a computer program, and the program can be stored in a computer-readable storage medium. During execution, it may include the processes of the embodiments of the above-mentioned methods. Wherein, the storage medium may be a magnetic disk, an optical disk, a read-only memory (Read-Only Memory, ROM) or a random access memory (Random Access Memory, RAM), etc.

The above is only a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Anyone skilled in the art can easily think of changes or substitutions within the technical scope disclosed in the present invention. All should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be determined by the protection scope of the claims.

Claims (12)

1. An encryption and decryption device based on an AES algorithm is characterized by comprising a cryptographic processing module for processing data; the cryptographic processing module includes:

at least one input logic path for performing logic operation on input packet data;

the first multi-path selection unit is used for selecting one path of input logic path to output the grouped data after the logic operation according to the AES mode control signal;

the cipher function operation unit is used for selecting a forward or reverse cipher function to encrypt and decrypt the grouped data according to the AES mode control signal;

the first demultiplexing unit is used for decomposing the encrypted and decrypted grouped data into at least one path of grouped data;

at least one output logic path for performing logic operation on each decomposed packet data;

and the second multi-path selection unit is used for selecting one path of output logic path to output the grouped data after the logic operation according to the AES mode control signal.

2. The encryption and decryption apparatus according to claim 1, wherein the cryptographic processing module further comprises a second demultiplexing unit configured to demultiplex incoming packet data into multiple paths and send the multiple paths to the incoming logical path.

3. The encryption and decryption apparatus according to claim 1, wherein the input logic path is any one of the following input logic paths:

a first input logic path for directly inputting packet data;

the second input logic path is used for inputting data obtained after the XOR logic operation is carried out on the grouped data and the password initial vector;

a third input logic path for inputting data obtained by performing exclusive-or logic operation on the packet data and the output 128-bit data packet of the previous stage;

the fourth input logic path is used for directly inputting the key initial vector;

the fifth input logic path is used for inputting data obtained after splicing operation is carried out on the low b-s bit of the previous-stage input grouping and the s bit of the previous-stage ciphertext;

a sixth input logic path for inputting the output 128-bit data packet of the previous stage;

a seventh input logic path for inputting the value of the counter.

4. The encryption and decryption apparatus according to claim 1, wherein the output logic path is any one of the following output logic paths:

a first output logic path for directly outputting the packet data;

the second output logic path is used for outputting data after the XOR operation of the high s bits of the grouped data and the s bits of the current-level plaintext;

the third output logic path is used for outputting data obtained after the XOR operation of the grouped data and the current-level plaintext;

the fourth output logic path is used for outputting data obtained after XOR operation is carried out on the high s bits of the grouped data and the s bits of the current-stage ciphertext;

the fifth output logic path is used for outputting the data after the XOR operation of the grouped data and the current-stage ciphertext;

a sixth output logic path, configured to output data obtained by performing xor operation on the packet data and the key initial vector;

and the seventh output logic path is used for outputting data obtained by performing exclusive-or operation on the grouped data and the input ciphertext of the previous stage.

5. The encryption/decryption apparatus according to claim 1, wherein the cryptographic function operation unit includes a forward cryptographic function operation unit and a reverse cryptographic function operation unit; wherein,

the forward cryptographic function operation unit comprises two modules: the first operation module performs S-box transformation, row transformation, column transformation and expanded key XOR processing on the data in sequence, and is used for realizing round operations of other rounds except the last round of round operations; the second operation module performs S-box transformation, row transformation and expanded key XOR processing on the data in sequence and is used for realizing the last round of operation;

the reverse cryptographic function operation unit comprises two modules: the third operation module sequentially performs inverse row transformation, inverse S box transformation, XOR with the expanded key and inverse column transformation on the data, and is used for realizing round operation of other rounds except the last round; and the fourth operation module sequentially performs inverse row transformation, inverse S box transformation and expanded key XOR processing on the data and is used for realizing the last round of operation.

6. The encryption and decryption apparatus according to claim 1, wherein the cryptographic processing module further includes a bit width conversion unit configured to perform bit width conversion on the input packet data and the output packet data.

7. The encryption and decryption apparatus according to claim 1, further comprising an interaction register module for generating the AES mode control signal according to register configuration information.

8. The encryption and decryption apparatus according to claim 7, further comprising a processor module for configuring register configuration information required by the register interaction module.

9. The encryption and decryption apparatus according to claim 7, further comprising an input data selection module for selecting input data streams of different formats into the interactive registration module.

10. The encryption and decryption apparatus according to claim 9, further comprising an interface module, configured to format-convert input data streams with different formats and send the format-converted input data streams to the input data selection module.

11. The encryption and decryption apparatus according to claim 1, further comprising an output data selection module for controlling the cryptographic processing module to select and output the forward/backward processed data according to the AES mode control signal.

12. The encryption and decryption apparatus according to claim 11, further comprising a storage module for storing the data outputted by the output data selection module.