KR20090000444A - Manufacturing method of nonvolatile memory device - Google Patents

Abstract

The present invention relates to a method of manufacturing a nonvolatile memory device, comprising: providing a semiconductor substrate having a tunnel insulating film and a first conductive layer formed on an active region, and a dielectric film formed on the semiconductor substrate including the first conductive layer. Forming a contact hole by forming a capping layer, removing a portion of the capping layer and the dielectric layer included in a region where a select line is to be formed, and a region between the select line and an adjacent word line; Forming a second conductive layer and a gate electrode layer on the capping layer including a contact hole, the gate electrode layer, the second conductive layer, the capping layer, the dielectric layer, the first conductive layer, the tunnel insulating layer; Etching the semiconductor substrate to form a trench in a portion of the semiconductor substrate, so that a word line adjacent to the selection line is desired. It can be prevented from being subjected to the program operation.

Description

Method of fabricating non-volatile memory device

1A to 1F are cross-sectional views of devices sequentially illustrated to explain a method of manufacturing a nonvolatile memory device according to the present invention.

<Description of the symbols for the main parts of the drawings>

102 semiconductor substrate 104 tunnel insulating film

106: first conductive layer 108: dielectric film

110: capping layer 112: mask pattern

114: second conductive layer 116: gate electrode layer

The present invention relates to a method of manufacturing a nonvolatile memory device, and more particularly, to a method of manufacturing a flash memory device.

Flash memory is one of non-volatile memories that can store data when power is cut off. Flash memory can be electrically programmed and erased, and does not require a refresh function to rewrite data at regular intervals. Such flash memory devices are classified into NOR flash memory and NAND flash memory according to the cell structure and operating conditions. NOR flash memory is mainly used in applications that require high-speed operation because a plurality of word lines are connected in parallel and can be programmed and erased at an arbitrary address. On the other hand, NAND flash memory is a structure in which a word line formed by connecting a plurality of memory cells between a pair of select lines forms a string and is connected to a source and a drain. Mainly used in

To program this NAND flash memory, the F-N tunneling effect is used. To this end, a high voltage is applied to the memory cell to be programmed and the semiconductor substrate is grounded to make a bias difference. As a result, electrons in a channel region of the semiconductor substrate are tunneled to the floating gate of the memory cell, and electrons are trapped and programmed in the floating gate of the memory cell. However, since a high voltage is equally applied to other memory cells sharing the word line with the memory cell being programmed, the other memory cells sharing the word line may be programmed undesirably.

To prevent this problem, the channel region of another memory cell sharing the word line is boosted to maintain a constant voltage, for example, 8V or more. As a result, a voltage difference between the channel region and another memory cell sharing the word line may be reduced to prevent program operation. However, when boosting the channel region of the word line adjacent to the select line, when 0 V is applied to the select line, a gate induced drain leakage (GIDL) current is generated in a section where the select line and the junction overlap. At this time, the generated electrons move quickly to the channel region and then act as a hot carrier by the program voltage applied to the word line adjacent to the selection line to move to the floating gate. Because of this, the threshold voltage may increase in the word line adjacent to the select line and may still cause unwanted programming.

The present invention prevents unwanted program operation from occurring by forming trenches in the semiconductor substrate between the select line and the select line and the adjacent word lines to increase the electron transfer path between the select line and the select line and the adjacent word lines. An ONO contact formed in the line may be formed between the select line and the word line adjacent to the select line to form a trench in the semiconductor substrate more easily.

A method of manufacturing a nonvolatile memory device according to the present invention includes providing a semiconductor substrate having a tunnel insulating film and a first conductive layer formed on an active region, a dielectric film formed on the semiconductor substrate including the first conductive layer; Forming a contact hole by forming a capping layer, removing a portion of the capping layer and the dielectric layer included in a region where a select line is to be formed, and a region between the select line and an adjacent word line; Forming a second conductive layer and a gate electrode layer on the capping layer including a hole; and the gate electrode layer, the second conductive layer, the capping layer, the dielectric layer, the first conductive layer, the tunnel insulating layer, and the Etching the semiconductor substrate to form a trench in a portion of the semiconductor substrate corresponding to one side of the contact hole.

After forming the trench, the method may further include forming a junction region on the semiconductor substrate including the trench. The etching process of forming the trench may include performing a first etching process of etching the gate electrode layer, the second conductive layer, the capping layer, and the first conductive layer until the tunnel insulating layer and the dielectric layer are exposed. And performing a second etching process of etching the exposed first conductive layer and the semiconductor substrate after removing the tunnel insulating layer and the dielectric layer, and removing the exposed tunnel insulating layer after removing the first conductive layer. It may include the step of performing a third etching process. The selection line may include a source selection line and a drain selection line. The first conductive layer may be formed of polysilicon. The capping layer may be formed of polysilicon. The second conductive layer may be formed of polysilicon or tungsten silicide.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention.

However, the present invention is not limited to the embodiments described below, but may be implemented in various forms, and the scope of the present invention is not limited to the embodiments described below. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention. Only this embodiment is provided to complete the disclosure of the present invention and to fully inform those skilled in the art, the scope of the present invention should be understood by the claims of the present application.

1A to 1F are cross-sectional views of devices sequentially illustrated to explain a method of manufacturing a nonvolatile memory device according to the present invention.

Referring to FIG. 1A, a semiconductor substrate 102 having an isolation layer (not shown) is provided. The semiconductor substrate 102 is defined by an active region (not shown) through an isolation layer (not shown). The semiconductor substrate 102 may be formed of silicon. Subsequently, a tunnel insulating film 104 is formed on the semiconductor substrate 102. The tunnel insulating film 104 is preferably formed of an oxide film. The first conductive layer 106 is formed on the tunnel insulating film 104. The first conductive layer 106 may be used as a floating gate in which electrons moved from the channel region formed under the tunnel insulating layer 104 may be stored in the flash memory device to perform a program operation or the like. The first conductive layer 106 may be formed of polysilicon. An insulating film, for example, a dielectric film 108, is formed on the first conductive layer 106. The dielectric film 108 is preferably formed of a laminated film of ONO (Oxide / Nitride / Oxide) structure. Thereafter, a capping layer 110 is formed on the dielectric film 108. The capping layer 110 may prevent the dielectric film 108 from being damaged in a subsequent contact hole forming process and may serve as a part of a control gate layer formed in a subsequent process. The capping layer 110 is preferably formed of a conductive film, for example, polysilicon.

Referring to FIG. 1B, after the mask pattern 112 is formed on the capping layer 110, the capping layer 110 and the dielectric layer 108 are patterned by an etching process using the mask pattern 112 to form a contact hole ( Form A). At this time, part of the first conductive layer 106 may be removed together. The contact hole A is formed to connect the control gate of the selection line formed in the subsequent process to the first conductive layer 106. In this case, the position of the contact hole A formed is included in the position where the selection line is formed in the subsequent process, and at the same time, the position corresponding to the space between the selection line and the word line formed adjacent thereto is also included. It is preferable.

Referring to FIG. 1C, after removing the mask pattern 112 (see FIG. 1B), a second conductive layer 114 is formed on the capping layer 110 including the contact hole A (see FIG. 1B). At this time, the second conductive layer 114 and the first conductive layer 106 are in electrical contact through the contact hole A. The second conductive layer 114 may serve as a control gate in the flash memory device. The second conductive layer 114 may be formed of a single layer or a laminated structure using polysilicon or tungsten silicide. Thereafter, the gate electrode layer 116 is formed on the second conductive layer 114.

Referring to FIG. 1D, a mask pattern 118 is formed on the gate electrode layer 116. Subsequently, a gate etching process of etching the stacked layers formed by the above-described process is performed to form a gate. To this end, first, the gate electrode layer 116 is etched by performing an etching process using the mask pattern 118, and the lower portion of the gate electrode layer 116 is further etched under the condition that the polysilicon is etched more than the oxide film. Therefore, in the above-described process, the contact hole A (see FIG. 1B) is formed so that the portion where the dielectric film 108 does not remain is etched until the tunnel insulation film 104 is exposed, and the dielectric film 108 The remaining portion of) is etched until the dielectric film 108 is exposed.

As a result, the second conductive layer 114 and the capping layer 110 are removed between the word lines formed in a subsequent process to expose the dielectric film 108. In addition, a portion of the dielectric film 108 remains between the select line formed in the subsequent process and the word line adjacent thereto, so that the portion of the dielectric film 108 remains in the second conductive layer 114 and the capping layer. 110 is removed to expose dielectric film 108. However, in the portion where the dielectric film 108 does not remain, the second conductive layer 114, the capping layer 110, and the first conductive layer 106 are removed to expose the tunnel insulating layer 104.

Referring to FIG. 1E, an etching process is performed to remove the exposed dielectric film 108 and the tunnel insulating film 104, and then to remove the exposed semiconductor substrate 102 and the first conductive layer 106. At this time, a trench 102a is formed in the semiconductor substrate 102 corresponding to one side of the contact hole A (see FIG. 1B) formed in the above-described process in the semiconductor substrate 102 between the selection line and the adjacent word line. As such, the trench 102a may be formed in the semiconductor substrate 102 without any additional process by remaining a portion of the dielectric film 108 between the selection line and the adjacent word line and performing an etching process using the same. Meanwhile, the size of the trench 102a formed in the semiconductor substrate 102 may be adjusted by adjusting the size of the dielectric film 108 remaining between the selection line and the word line adjacent thereto. Although the present invention has been described as leaving a portion of the dielectric film 108 between the select line and the word line adjacent thereto, the present invention is not limited thereto, and the dielectric film 108 may be removed between the select line and the word line adjacent thereto. It may be.

Thereafter, the tunnel insulating film 104 between the word lines is removed and the mask pattern 118 (see FIG. 1D) is removed. As a result, a selection line including a source select line (SSL) and a drain select line (DSL) and a plurality of word lines WL0, WL1,..., WL30, and WL31 positioned therebetween are formed. Is complete.

Referring to FIG. 1F, a plurality of junction regions 120 are formed in the semiconductor substrate 102 including the trench 102a by performing an ion implantation process. Subsequently, although not shown in the drawings, gate spacers may be formed on sidewalls of the selection line and the word line, and a manufacturing process of a conventional nonvolatile memory device may be performed.

According to the present invention, a trench is formed in a semiconductor substrate between a select line and an adjacent word line, thereby increasing the distance that electrons generated by the gate induced drain leakage (GIDL) travels to an adjacent word line and by the channel boosting voltage. The electric field can be relaxed. As a result, the probability that the electrons generated by the GIDL act as a hot carrier on the adjacent word line is greatly reduced, and the program disturbance phenomenon can be prevented.

On the other hand, in order to reduce the program disturbance phenomenon, the space between the select line and the adjacent word line is physically increased or the space between the select line and the adjacent word line is not used as a memory cell, Instead, a dummy word line may be formed. However, this method may increase the size of the string, the size of the memory device may be unnecessarily large.

In addition, the dielectric film may be removed only on the select line by changing the position or size of the contact hole formed to remove the ONO film, and the dielectric film may be left between the select line and the adjacent word line. In this case, after the gate is formed through the gate etching process, an ion implantation process for forming a junction region is performed and a first gate spacer formation process is performed. Thereafter, an etching process of opening only a space between the selection line and the word line adjacent thereto is performed, and the trench is formed by etching the semiconductor substrate using the etching process. In this case, in the process of opening only the space between the selection line and the adjacent word line, the overlap margin is very important, and the difficulty of the process increases, and an additional compensation ion implantation process must be performed to compensate for the junction damaged by etching. Thereafter, the second gate spacer forming process is further performed in consideration of the spacer deposition thickness. As such, if the dielectric film remains between the select line and the adjacent word line, the process step is increased and the process difficulty is increased as compared with the present invention.

According to the method for manufacturing a nonvolatile memory device of the present invention, an ONO contact formed on a selection line is also formed between the selection line and the word line adjacent to the selection line, and then subjected to an etching process, thereby eliminating the need for a separate process. Trench may be formed in the substrate. Therefore, the process can be simplified and the process time can be shortened, such as the number of masks used during the process is reduced. In addition, trenches are formed in the semiconductor substrate between the select line and the select line and the adjacent word line to increase the electron movement path between the select line and the select line and the adjacent word line, thereby causing unwanted program operation of the select line and the adjacent word line. Can be prevented.

Claims (4)

Providing a semiconductor substrate having a tunnel insulating film and a first conductive layer formed over the active region; Forming a dielectric film and a capping layer on the semiconductor substrate including the first conductive layer; Forming a contact hole by removing a portion of the capping layer and the dielectric layer included in a region where a select line is to be formed and a region between the select line and an adjacent word line; Forming a second conductive layer and a gate electrode layer on the capping layer including the contact hole; The gate electrode layer, the second conductive layer, the capping layer, the dielectric layer, the first conductive layer, the tunnel insulating layer, and the semiconductor substrate are etched to form a trench in a portion of the semiconductor substrate corresponding to one side of the contact hole. A method of manufacturing a nonvolatile memory device comprising the step of forming. The method of claim 1, And forming a junction region in the semiconductor substrate including the trench after forming the trench. The method of claim 1, wherein the etching process for forming the trench, Performing a first etching process of etching the gate electrode layer, the second conductive layer, the capping layer and the first conductive layer until the tunnel insulating layer and the dielectric layer are exposed; Performing a second etching process of etching the exposed first conductive layer and the semiconductor substrate after removing the tunnel insulating layer and the dielectric layer; And And removing the exposed first tunnel insulating layer after removing the first conductive layer, and performing a third etching process. The method of claim 1, And the select line comprises a source select line and a drain select line.

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