JP2012094790A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

The performance of a semiconductor device having a nonvolatile memory is improved.
A split gate type nonvolatile memory is formed via a control gate electrode CG formed on a semiconductor substrate 1 via an insulating film 3 and an insulating film 5 having a charge storage portion on the semiconductor substrate 1. The memory gate electrode MG is formed in a sidewall spacer shape on the side surface 22 of the control gate electrode CG via the insulating film 5. The control gate electrode CG protrudes from the lower portion 21a of the side surface 21 opposite to the side adjacent to the memory gate electrode MG via the insulating film 5, and on the side adjacent to the memory gate electrode MG via the insulating film 5. The lower part 22a of the side surface 22 is retracted. In the memory gate electrode MG, a lower portion 23a of the side surface 23 on the side adjacent to the control gate electrode CG via the insulating film 5 protrudes.
[Selection] Figure 2

Description

  The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a technology effective when applied to a semiconductor device having a nonvolatile memory and a method for manufacturing the same.

  EEPROM (Electrically Erasable and Programmable Read Only Memory) is widely used as a nonvolatile semiconductor memory device that can be electrically written and erased. These storage devices (memory) typified by currently used flash memory have a conductive floating gate electrode and a trapping insulating film surrounded by an oxide film under the gate electrode of the MISFET. The charge accumulation state in the floating gate and the trapping insulating film is stored information and is read as the threshold value of the transistor. This trapping insulating film refers to an insulating film capable of accumulating charges, and examples thereof include a silicon nitride film. The threshold value of the MISFET is shifted by such charge injection / release to / from the charge storage region to operate as a memory element. As this flash memory, there is a split gate type cell using a MONOS (Metal-Oxide-Nitride-Oxide-Semiconductor) film. In such a memory, by using a silicon nitride film as a charge storage region, it is superior in data retention reliability because it accumulates charges discretely compared to a conductive floating gate film, and also in data retention reliability. Therefore, the oxide films above and below the silicon nitride film can be made thinner, and the voltage of the write / erase operation can be lowered.

  Japanese Patent Application Laid-Open No. 2004-186252 (Patent Document 1), Japanese Patent Application Laid-Open No. 2004-343014 (Patent Document 2) and Japanese Patent Application Laid-Open No. 2004-1111749 (Patent Document 3) describe a technique related to a MONOS type nonvolatile memory. Has been.

JP 2004-186252 A JP 2004-343014 A JP 2004-1111749 A

  According to the study of the present inventor, the following has been found.

  In a split gate type nonvolatile memory, for example, an ONO (Oxide-Nitride-Oxide) film having a laminated structure including a silicon oxide film, a silicon nitride film, and a silicon oxide film is formed as a laminated gate insulating film. The control gate electrode and the memory gate electrode are adjacent to each other through the ONO film. In recent years, it has been desired to improve the electrical performance or ensure the reliability of the nonvolatile memory.

  An object of the present invention is to provide a technique capable of improving the electrical performance of a semiconductor device. Another object of the present invention is to provide a technique capable of improving the reliability of a semiconductor device. Another object of the present invention is to provide a technique capable of improving the electrical performance of a semiconductor device and to provide a technique capable of improving the reliability of the semiconductor device.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  A semiconductor device according to a typical embodiment is a semiconductor device including a split gate nonvolatile memory cell, and includes a first gate electrode formed on a semiconductor substrate via a gate insulating film, and the semiconductor substrate. And a second gate electrode formed through an insulating film having a charge storage portion, and the second gate electrode is adjacent to the second side surface of the first gate electrode through the insulating film. is doing. The lower portion of the first side surface of the first gate electrode is opposite to the side adjacent to the second gate electrode through the insulating film, and is adjacent to the second gate electrode through the insulating film. The lower part of the first side surface on the side to be retracted. The lower part of the third side surface of the second gate electrode protrudes adjacent to the first gate electrode through the insulating film.

  In addition, a method for manufacturing a semiconductor device according to a representative embodiment is a method for manufacturing a semiconductor device including a memory cell of a nonvolatile memory, wherein (a) a step of preparing a semiconductor substrate, (b) a step of preparing the semiconductor substrate Forming a first insulating film for a gate insulating film on a main surface; (c) forming a first silicon film for a first gate electrode constituting the memory cell on the first insulating film; have. Further, (d) after the step (c), the step of etching the first silicon film to form a first silicon film pattern, (e) after the step (d), the main surface of the semiconductor substrate and the first step (1) forming a second insulating film having a charge storage portion inside on the upper surface and side surfaces of the silicon film pattern; (f) forming the memory cell on the second insulating film after the step (e); Forming a second silicon film for the second gate electrode. Further, (g) after the step (f), the second silicon film is etched, and the second gate constituting the memory cell is adjacent to the first silicon film pattern via the second insulating film. Forming an electrode; (h) removing an exposed portion of the second insulating film; (i) after the step (h), etching the first silicon film pattern to form the second gate electrode and the Forming the first gate electrode adjacent to each other through the second insulating film. The first gate electrode has a second side surface adjacent to the second gate electrode through the second insulating film, and a first side surface opposite to the second side surface. The first silicon film pattern formed in the step (d) has a fourth side surface that later becomes the second side surface of the first gate electrode. In the step (d), the first silicon film pattern is formed so that a lower portion of the fourth side surface of the first silicon film pattern is retracted. In the step (i), the first gate electrode is formed. The first silicon film pattern is processed so that the lower portion of the first side surface protrudes.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  According to the representative embodiment, the electrical performance of the semiconductor device can be improved. In addition, the reliability of the semiconductor device can be improved. In addition, electrical performance can be improved and the reliability of the semiconductor device can be improved.

It is principal part sectional drawing of the semiconductor device which is one embodiment of this invention. It is the elements on larger scale which expanded a part of FIG. It is an equivalent circuit diagram of a memory cell. 6 is a table showing an example of voltage application conditions to each part of a selected memory cell during “write”, “erase”, and “read”. It is a process flow figure showing a part of manufacturing process of a semiconductor device which is one embodiment of the present invention. It is principal part sectional drawing in the manufacturing process of the semiconductor device of one embodiment of this invention. FIG. 7 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 6; FIG. 8 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 7; FIG. 9 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 8; FIG. 10 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 9; FIG. 11 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 10; It is a partial expanded sectional view of FIG. It is a partial expanded sectional view of FIG. FIG. 12 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 11; FIG. 15 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 14; FIG. 16 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 15; FIG. 17 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 16; FIG. 18 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 17; FIG. 19 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 18; FIG. 20 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 19; FIG. 21 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 20; FIG. 22 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 21; FIG. 23 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 22; FIG. 24 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 23; FIG. 25 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 24; FIG. 26 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 25; FIG. 27 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 26; FIG. 28 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 27; FIG. 29 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 28; It is explanatory drawing of the process of patterning a silicon film by an etching. It is explanatory drawing of the process of patterning a silicon film by an etching. It is explanatory drawing of the process of patterning a silicon film by an etching. It is explanatory drawing of the process of patterning a silicon film by an etching. It is explanatory drawing of the process of patterning a silicon film by an etching. It is explanatory drawing of the process of patterning a silicon film by an etching. It is explanatory drawing of the process of patterning a silicon film by an etching. It is explanatory drawing of the process of patterning a silicon film by an etching. It is principal part sectional drawing of the semiconductor device which is one embodiment of this invention. It is explanatory drawing of the semiconductor device which is one embodiment of this invention. It is principal part sectional drawing in the manufacturing process of the semiconductor device of other embodiment of this invention. FIG. 41 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 40; It is principal part sectional drawing of the semiconductor device which is other embodiment of this invention. It is principal part sectional drawing in the manufacturing process of the semiconductor device of other embodiment of this invention. FIG. 44 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 43; FIG. 45 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 44;

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. There are some or all of the modifications, details, supplementary explanations, and the like. Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number. Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted. In the following embodiments, the description of the same or similar parts will not be repeated in principle unless particularly necessary.

  In the drawings used in the embodiments, hatching may be omitted even in a cross-sectional view so as to make the drawings easy to see. Further, even a plan view may be hatched to make the drawing easy to see.

(Embodiment 1)
The present invention is a semiconductor device including a non-volatile memory (non-volatile memory element, flash memory, non-volatile semiconductor memory device), and the non-volatile memory mainly has a trapping insulating film (charge can be accumulated in a charge accumulation portion). Insulating film) is used. In the following embodiments, the nonvolatile memory will be described based on a memory cell using an n-channel MISFET (MISFET: Metal Insulator Semiconductor Field Effect Transistor) as a basis and using a trapping insulating film. The polarities (polarity of applied voltage and carrier polarity at the time of writing / erasing / reading) in the following embodiments are for explaining the operation in the case of a memory cell based on an n-channel MISFET. In the case of using a p-channel type MISFET as a basis, the same operation can be obtained in principle by inverting all the polarities such as applied potential and carrier conductivity type.

  A semiconductor device and a manufacturing method thereof according to the present embodiment will be described with reference to the drawings.

  FIG. 1 is a cross-sectional view of a main part of the semiconductor device of the present embodiment. The semiconductor device of the present embodiment is a semiconductor device including a nonvolatile memory, and FIG. 1 shows a cross-sectional view of a main part of a memory cell region of the nonvolatile memory. FIG. 2 is a partial enlarged cross-sectional view (main cross-sectional view) of the memory cell MC in the semiconductor device of the present embodiment, and a part of FIG. 1 is enlarged. 2 does not show the insulating film 13 in the structure of FIG. 1 for easy understanding.

  As shown in FIG. 1, a semiconductor substrate (semiconductor wafer) 1 made of p-type single crystal silicon having a specific resistance of about 1 to 10 Ωcm, for example, has an element isolation region (elements described later) for isolating elements. The p-type well PW1 is formed in the active region isolated (defined) corresponding to the isolation region 2 (not shown here). In the p-type well PW1 in the memory cell region, a memory cell MC of a nonvolatile memory including a memory transistor and a control transistor (selection transistor) as shown in FIG. 1 is formed. In each memory cell region, a plurality of memory cells MC are formed in an array, and each memory cell region is electrically isolated from other regions by an element isolation region.

  As shown in FIG. 1 and FIG. 2, the memory cell MC of the nonvolatile memory in the semiconductor device of the present embodiment is a split gate type memory cell, and has a control gate electrode (selection gate electrode) CG. Two MISFETs of a (selection transistor) and a memory transistor having a memory gate electrode (memory gate electrode) MG are connected.

  Here, a MISFET (Metal Insulator Semiconductor Field Effect Transistor) including a gate insulating film including a charge storage portion (charge storage layer) and a memory gate electrode MG is referred to as a memory transistor (memory transistor). The MISFET including the gate electrode CG is referred to as a control transistor (selection transistor, memory cell selection transistor). Therefore, the memory gate electrode MG is a gate electrode of the memory transistor, the control gate electrode CG is a gate electrode of the control transistor, and the control gate electrode CG and the memory gate electrode MG are nonvolatile memories (memory cells thereof). It is the gate electrode which comprises.

  Hereinafter, the configuration of the memory cell MC will be specifically described.

  As shown in FIGS. 1 and 2, the memory cell MC of the nonvolatile memory includes n-type semiconductor regions MS and MD for source and drain formed in the p-type well PW1 of the semiconductor substrate 1, and the semiconductor substrate. A control gate electrode CG formed on the top of 1 (p-type well PW1), and a memory gate electrode MG formed on the top of the semiconductor substrate 1 (p-type well PW1) and adjacent to the control gate electrode CG. Yes. The memory cell MC of the nonvolatile memory further includes an insulating film (gate insulating film) 3 formed between the control gate electrode CG and the semiconductor substrate 1 (p-type well PW1), the memory gate electrode MG, and the semiconductor substrate 1 The insulating film 5 is formed between the (p-type well PW1) and between the memory gate electrode MG and the control gate electrode CG.

  The control gate electrode CG and the memory gate electrode MG extend along the main surface of the semiconductor substrate 1 and are arranged side by side with the insulating film 5 interposed between the opposing side surfaces (side walls). The extending direction of the control gate electrode CG and the memory gate electrode MG is a direction perpendicular to the paper surface of FIG. The control gate electrode CG and the memory gate electrode MG are disposed above the semiconductor substrate 1 (p-type well PW1) between the semiconductor region MD and the semiconductor region MS via insulating films 3 and 5 (however, the control gate electrode CG is an insulating film). 3, the memory gate electrode MG is formed via the insulating film 5), the memory gate electrode MG is located on the semiconductor region MS side, and the control gate electrode CG is located on the semiconductor region MD side.

  The control gate electrode CG and the memory gate electrode MG are adjacent to each other with the insulating film 5 interposed therebetween, and the memory gate electrode MG is disposed on the side surface (side wall) 22 of the control gate electrode CG via the insulating film 5. It is formed in a sidewall spacer shape. The insulating film 5 extends over both the region between the memory gate electrode MG and the semiconductor substrate 1 (p-type well PW1) and the region between the memory gate electrode MG and the control gate electrode CG. .

  An insulating film 3 (that is, an insulating film 3 under the control gate electrode CG) formed between the control gate electrode CG and the semiconductor substrate 1 (p-type well PW1) functions as a gate insulating film of the control transistor, and is a memory gate. The insulating film 5 between the electrode MG and the semiconductor substrate 1 (p-type well PW1) (that is, the insulating film 5 under the memory gate electrode MG) is a gate insulating film of the memory transistor (a gate insulating film having a charge storage portion inside). ).

  The insulating film 3 can be formed of, for example, a silicon oxide film or a silicon oxynitride film. The insulating film 3 is a metal oxide having a dielectric constant higher than that of the silicon nitride film, such as a hafnium oxide film, an aluminum oxide film (alumina), or a tantalum oxide film, in addition to the above-described silicon oxide film or silicon oxynitride film. A membrane may be used.

  The insulating film 5 includes a silicon oxide film (oxide film) 6a, a silicon nitride film (nitride film, charge storage layer) 6b on the silicon oxide film 6a, and a silicon oxide film (oxide film) 6c on the silicon nitride film 6b. It consists of a laminated film having

  Since the insulating film 5 has a laminated structure of the silicon oxide film 6a, the silicon nitride film 6b, and the silicon oxide film 6c, the region between the memory gate electrode MG and the semiconductor substrate 1 (p-type well PW) and the memory gate The insulating film 5 extending to the region between the electrode MG and the control gate electrode CG can also be regarded as a laminated gate insulating film (a gate insulating film having a laminated structure). However, the insulating film 5 between the memory gate electrode MG and the semiconductor substrate 1 (p-type well PW) functions as a gate insulating film of the memory transistor, but the insulation between the memory gate electrode MG and the control gate electrode CG. The film 5 functions as an insulating film for insulating (electrically separating) the memory gate electrode MG and the control gate electrode CG.

  Of the insulating film 5, the silicon nitride film 6b is an insulating film for accumulating charges and functions as a charge accumulating layer (charge accumulating portion). That is, the silicon nitride film 6 b is a trapping insulating film formed in the insulating film 5. For this reason, the insulating film 5 can be regarded as an insulating film having a charge storage portion (charge storage layer, here, the silicon nitride film 6b) inside.

  The silicon oxide film 6c and the silicon oxide film 6a located above and below the silicon nitride film 6b can function as a charge block layer (charge block film, charge confinement layer). With the structure in which the silicon nitride film 6b is sandwiched between the silicon oxide film 6c and the silicon oxide film 6a, charges can be accumulated in the silicon nitride film 6b. The silicon oxide film 6a, the silicon nitride film 6b, and the silicon oxide film 6c can also be regarded as ONO (oxide-nitride-oxide) films.

The semiconductor region MS and the semiconductor region MD are semiconductor regions for source or drain. That is, the semiconductor region MS is a semiconductor region that functions as one of a source region or a drain region, and the semiconductor region MD is a semiconductor region that functions as the other of the source region or the drain region. Here, the semiconductor region MS is a semiconductor region functioning as a source region, and the semiconductor region MD is a semiconductor region functioning as a drain region. The semiconductor regions MS and MD are each composed of a semiconductor region (n-type impurity diffusion layer) into which n-type impurities are introduced, and each has an LDD (lightly doped drain) structure. That is, the source semiconductor region MS includes an n ⁻ type semiconductor region (extension region) EX1 and an n ⁺ type semiconductor region (source region) 10a having a higher impurity concentration than the n ⁻ type semiconductor region EX1. The drain semiconductor region MD includes an n ⁻ type semiconductor region (extension region) EX2 and an n ⁺ type semiconductor region (drain region) 10b having an impurity concentration higher than that of the n ⁻ type semiconductor region EX2. The n ⁺ type semiconductor region 10a has a deeper junction depth and a higher impurity concentration than the n ⁻ type semiconductor region EX1, and the n ⁺ type semiconductor region 10b has a deeper junction depth than the n ⁻ type semiconductor region EX2. And the impurity concentration is high.

  On side surfaces (side surfaces not adjacent to each other) of the memory gate electrode MG and the control gate electrode CG, side wall spacers (side walls, side wall spacers, side wall insulating films) made of an insulator (insulating film) such as silicon oxide. ) SW is formed. That is, the side on the side (side wall) 24 of the memory gate electrode MG opposite to the side adjacent to the control gate electrode CG via the insulating film 5 and the side adjacent to the memory gate electrode MG via the insulating film 5 Sidewall spacers SW are formed on the side surfaces (sidewalls) 21 of the opposite control gate electrode CG.

  Here, among the side surfaces (side walls) of the control gate electrode CG, the side surface (side wall) adjacent to the memory gate electrode MG via the insulating film 5 is referred to as a side surface (side wall) 22 with reference numeral 22. Of the side surfaces (side walls) of the control gate electrode CG, the side surface (side wall) opposite to the side surface (side wall) 22, that is, the side surface (side wall) on the semiconductor region MD side is denoted by reference numeral 21. It will be referred to as (side wall) 21. In addition, among the side surfaces (side walls) of the memory gate electrode MG, the side surface (side wall) adjacent to the control gate electrode CG via the insulating film 5 is referred to as a side surface (side wall) 23 with reference numeral 23. Of the side surfaces (sidewalls) of the gate electrode MG, the side surface (sidewall) opposite to the side surface (sidewall) 23, that is, the side surface (sidewall) on the semiconductor region MS side is denoted by reference numeral 24 and is referred to as the side surface (sidewall). (Side wall) 24.

The n ⁻ type semiconductor region EX1 of the source part is formed in a self-aligned manner with respect to the memory gate electrode MG, and the n ⁺ type semiconductor region 10a is formed with respect to the side wall spacer SW on the side surface (side wall) 24 of the memory gate electrode MG. It is formed in a self-aligning manner. For this reason, the low concentration n ⁻ type semiconductor region EX1 is formed below (below) the sidewall spacer SW on the side surface 24 of the memory gate electrode MG, and the high concentration n ⁺ type semiconductor region 10a has a low concentration. It is formed outside the n ⁻ type semiconductor region EX1. Accordingly, the low concentration n ⁻ type semiconductor region EX1 is formed adjacent to the channel region of the memory transistor, and the high concentration n ⁺ type semiconductor region 10a is in contact with (adjacent to the low concentration n ⁻ type semiconductor region EX1). However, it is formed so as to be separated from the channel region of the memory transistor by the n ⁻ type semiconductor region EX1.

The n ⁻ type semiconductor region EX2 in the drain portion is formed in a self-aligned manner with respect to the control gate electrode CG, and the n ⁺ type semiconductor region 10b is formed with respect to the sidewall spacer SW on the side surface (side wall) 21 of the control gate electrode CG. It is formed in a self-aligning manner. For this reason, the low concentration n ⁻ type semiconductor region EX2 is formed below (below) the sidewall spacer SW on the side surface 21 of the control gate electrode CG, and the high concentration n ⁺ type semiconductor region 10b has a low concentration. It is formed outside the n ⁻ type semiconductor region EX2. Therefore, the low concentration n ⁻ type semiconductor region EX2 is formed adjacent to the channel region of the control transistor, and the high concentration n ⁺ type semiconductor region 10b is in contact with (adjacent to the low concentration n ⁻ type semiconductor region EX2). However, it is formed so as to be separated from the channel region of the control transistor by the n ⁻ type semiconductor region EX2.

  A channel region of the memory transistor is formed under the insulating film 5 under the memory gate electrode MG, and a channel region of the control transistor is formed under the insulating film 3 under the control gate electrode CG. In the channel formation region of the control transistor under the insulating film 3 under the control gate electrode CG, a semiconductor region (p-type semiconductor region or n-type semiconductor region) for adjusting the threshold value of the control transistor is formed as necessary. In the channel formation region of the memory transistor under the insulating film 5 under the memory gate electrode MG, a semiconductor region for adjusting the threshold value of the memory transistor (p-type semiconductor region or n-type semiconductor region) is formed as necessary. Has been.

A halo region HA for suppressing short channel characteristics (punch through) is formed for the n ⁻ type semiconductor region EX2 in the drain portion. That is, in the p-type well PW1, the halo region HA is formed so as to wrap (cover) the n ⁻ -type semiconductor region EX2. The halo region HA has a conductivity type opposite to that of the n ⁻ type semiconductor region EX2 and the same conductivity type as the p-type well PW1, and has a higher impurity concentration (p-type impurity concentration) than the p-type well PW1. Then, it is p-type (p-type semiconductor region).

The halo region HA is formed with respect to the n ⁻ type semiconductor region EX2 for drain (is formed so as to wrap around the n ⁻ type semiconductor region EX2 in the p type well PW1), but is short of the control transistor. It is formed to suppress channel characteristics. For the source n ⁻ type semiconductor region EX1, the halo region HA does not have to be formed, but can be formed to suppress the short channel characteristic of the memory transistor.

  The control gate electrode CG is made of a conductor (conductor film), but is preferably made of a silicon film 4 such as an n-type polysilicon film (polycrystalline silicon film doped with n-type impurities, doped polysilicon film). The silicon film 4 constituting the control gate electrode CG is preferably an n-type silicon film, and has a low resistivity by introducing an n-type impurity. Specifically, the control gate electrode CG is made of a patterned silicon film 4.

  The memory gate electrode MG is made of a conductor (conductor film), but is preferably made of a silicon film 7. The silicon film 7 constituting the memory gate electrode MG is preferably an n-type silicon film, and has a low resistivity by introducing an n-type impurity. The silicon film 7 is more preferably an n-type polysilicon film (polycrystalline silicon film doped with n-type impurities, doped polysilicon film). As will be described later, for the memory gate electrode MG, the silicon film 7 formed on the semiconductor substrate 1 so as to cover the control gate electrode CG is anisotropically etched, and the insulating film 5 is formed on the side surface (side wall) of the control gate electrode CG. The silicon film 7 is formed by leaving the film through. Therefore, the memory gate electrode MG is formed in a side wall spacer shape on the side surface (side wall) 21 of the control gate electrode CG via the insulating film 5.

  In the present embodiment, in the control gate electrode CG, the lower portion 21a of the side surface (first side surface, side wall) 21 on the semiconductor region MD side protrudes toward the semiconductor region MD side, and is adjacent to the memory gate electrode MG via the insulating film 5. The lower portion 22a of the side surface (second side surface, side wall) 22 on the side to be retracted toward the semiconductor region MD side. Further, in the memory gate electrode MG, a lower portion 23a of a side surface (third side surface, side wall) 23 adjacent to the control gate electrode CG via the insulating film 5 protrudes toward the control gate electrode CG side. This will be described in more detail later.

The upper part (upper surface) of the memory gate electrode MG (the silicon film 7 constituting), the upper part (upper surface) of the control gate electrode CG (the upper part), and the upper parts (upper surface, surface) of the n ⁺ type semiconductor regions 10a and 10b. ), A metal silicide layer (metal silicide film) 12 is formed by a salicide (Salicide: Self Aligned Silicide) technique or the like. The metal silicide layer 12 is made of, for example, a cobalt silicide layer or a nickel silicide layer. The metal silicide layer 12 can reduce the diffusion resistance and the contact resistance. A combination of the silicon film 4 constituting the control gate electrode CG and the metal silicide layer 12 on the upper part thereof can be regarded as the control gate electrode CG, and the silicon film 7 constituting the memory gate electrode MG; A combination of the upper metal silicide layer 12 and the metal silicide layer 12 can be regarded as the memory gate electrode MG. In addition, from the viewpoint of preventing a short circuit between the memory gate electrode MG and the control gate electrode CG as much as possible, the metal silicide layer 12 may not be formed on one or both of the memory gate electrode MG and the control gate electrode CG. obtain.

  On the semiconductor substrate 1, an insulating film 13 is formed as an interlayer insulating film so as to cover the control gate electrode CG, the memory gate electrode MG, and the sidewall spacer SW. The insulating film 13 is formed of a single film of a silicon oxide film or a laminated film of a silicon nitride film and a silicon oxide film formed thicker than the silicon nitride film on the silicon nitride film. The upper surface of the insulating film 13 is flattened.

  A contact hole (opening, through-hole) CNT is formed in the insulating film 13, and a conductive plug PG is embedded in the contact hole CNT as a conductor portion (connecting conductor portion).

  Plug PG is formed of a thin barrier conductor film formed on the bottom and side walls (side surfaces) of contact hole CNT, and a main conductor film formed so as to bury contact hole CNT on the barrier conductor film. However, in order to simplify the drawing, in FIG. 1, the barrier conductor film and the main conductor film (tungsten film) constituting the plug PG are shown in an integrated manner. The barrier conductor film constituting the plug PG can be, for example, a titanium film, a titanium nitride film, or a laminated film thereof, and the main conductor film constituting the plug PG can be a tungsten film.

The contact hole CNT and the plug PG embedded in the contact hole CNT are formed over the n ⁺ type semiconductor regions 10a and 10b, the control gate electrode CG, the memory gate electrode MG, and the like. At the bottom of the contact hole CNT, a part of the main surface of the semiconductor substrate 1, for example, a part of the n ⁺ type semiconductor regions 10a and 10b (the metal silicide layer 12 on the surface thereof), a metal on the surface of the control gate electrode CG (the surface on the surface). A part of the silicide layer 12), a part of the memory gate electrode MG (the metal silicide layer 12 on the surface thereof), and the like are exposed. The plug PG is connected to the exposed portion (exposed portion at the bottom of the contact hole CNT). In FIG. 1, a part of the n ⁺ -type semiconductor region 10b (the metal silicide layer 12 on the surface thereof) is exposed at the bottom of the contact hole CNT and electrically connected to the plug PG filling the contact hole CNT. Connected cross sections are shown.

  A wiring (wiring layer) M1 is formed on the insulating film 13 in which the plug PG is embedded. The wiring M1 is, for example, a damascene wiring (buried wiring), and is a wiring provided on an insulating film (not shown in FIG. 1 but corresponding to an insulating film 14 described later) formed on the insulating film 13. Embedded in the groove. The wiring M1 is electrically connected to the source region (semiconductor region MS) of the memory transistor, the drain region (semiconductor region MD) of the control transistor, the control gate electrode CG, the memory gate electrode MG, and the like through the plug PG. In FIG. 1, as an example of the wiring M1, a wiring M1 electrically connected to the drain region (semiconductor region MD) of the control transistor via the plug PG is shown. Further, upper wirings and insulating films are also formed, but their illustration and description are omitted here. Further, the wiring M1 and the wiring above it are not limited to damascene wiring (embedded wiring), and can be formed by patterning a conductor film for wiring, for example, tungsten wiring or aluminum wiring. You can also.

  FIG. 4 is a table showing an example of voltage application conditions to each part of the selected memory cell during “write”, “erase”, and “read” in the present embodiment. The table of FIG. 4 shows the voltage applied to the memory gate electrode MG of the memory cell (selected memory cell) as shown in FIGS. 1 to 3 at the time of “write”, “erase”, and “read”. Vmg, voltage Vs applied to the source region (semiconductor region MS), voltage Vcg applied to the control gate electrode CG, voltage Vd applied to the drain region (semiconductor region MD), and base voltage Vb applied to the p-type well PW1 Is described. Note that what is shown in the table of FIG. 4 is a preferred example of the voltage application conditions, and is not limited to this, and can be variously changed as necessary. In the present embodiment, the electron injection into the silicon nitride film 6b which is the charge storage layer (charge storage portion) in the insulating film 5 of the memory transistor is “writing”, and the hole is injected. Is defined as “erase”.

  In the table of FIG. 4, the column A corresponds to the case where the writing method is the SSI method and the erasing method is the BTBT method, and the column B is the writing method is the SSI method and the erasing method is the FN method. The column C corresponds to the case where the writing method is the FN method and the erasing method is the BTBT method, and the column D is the case where the writing method is the FN method and the erasing method is the FN method. It corresponds to.

  The SSI method can be regarded as an operation method in which a memory cell is written by injecting hot electrons into the silicon nitride film 6b. The BTBT method is an erasure of the memory cell by injecting hot holes into the silicon nitride film 6b. The FN method can be regarded as an operation method in which writing or erasing is performed by electron or hole tunneling. In other words, the FN method writing can be regarded as an operation method in which memory cells are written by injecting electrons into the silicon nitride film 6b by the FN tunnel effect. Can be regarded as an operation method in which memory cells are erased by injecting holes into the silicon nitride film 6b by the FN tunnel effect. This will be specifically described below.

  There are two writing methods: a so-called SSI (Source Side Injection) method that writes by hot electron injection by source side injection (hot electron injection writing method) and a so-called FN method called FN (Fowler Nordheim). There is a writing method (tunneling writing method) in which writing is performed by tunneling.

  In the SSI writing, for example, voltages (Vmg = 10V, Vs = 5V, Vcg = 1V, Vd = 0.5V) as shown in the “write operation voltage” in the column A or B in the table of FIG. , Vb = 0 V) is applied to each part of the selected memory cell to be written, and writing is performed by injecting electrons into the silicon nitride film 6b in the insulating film 5 of the selected memory cell. At this time, hot electrons are generated in a channel region (between the source and drain) between the two gate electrodes (memory gate electrode MG and control gate electrode CG), and in the insulating film 5 below the memory gate electrode MG. Hot electrons are injected into the silicon nitride film 6b which is a charge storage portion. The injected hot electrons (electrons) are trapped in the trap level in the silicon nitride film 6b in the insulating film 5, and as a result, the threshold voltage of the memory transistor rises (becomes a write state).

  In the FN system writing, for example, voltages (Vmg = −12V, Vs = 0V, Vcg = 0V, Vd = 0V, as shown in “writing operation voltage” in the column C or D in the table of FIG. Vb = 0V) is applied to each part of the selected memory cell to be written, and electrons are tunneled from the memory gate electrode MG and injected into the silicon nitride film 6b in the insulating film 5 in the selected memory cell. Do. At this time, electrons are injected from the memory gate MG through the silicon oxide film 6 c by FN tunneling (FN tunneling effect) and injected into the insulating film 5, and are trapped by trap levels in the silicon nitride film 6 b in the insulating film 5. As a result, the threshold voltage of the memory transistor increases (becomes a write state).

  In the FN mode writing, writing can also be performed by tunneling electrons from the semiconductor substrate 1 and injecting the electrons into the silicon nitride film 6b in the insulating film 5. In this case, the writing operation voltage is, for example, FIG. The “write operation voltage” in the column C or D in the table of FIG.

  The erasing method includes an erasing method (hot hole injection erasing method) in which erasing is performed by hot hole injection by BTBT (Band-To-Band Tunneling) called a BTBT method, and an FN (Fowler) called a FN method. There is an erasing method (tunneling erasing method) that performs erasing by tunneling.

  In the BTBT erasure, erasure is performed by injecting holes generated by BTBT (Band-To-Band Tunneling) into the charge storage portion (the silicon nitride film 6b in the insulating film 5). For example, the voltage (Vmg = −6V, Vs = 6V, Vcg = 0V, Vd = open, Vb = 0V) as shown in the “erase operation voltage” in the column A or C in the table of FIG. Is applied to each part of the selected memory cell. As a result, holes are generated by the BTBT (Band-To-Band Tunneling) phenomenon and the electric field is accelerated to inject holes into the silicon nitride film 6b in the insulating film 5 of the selected memory cell. The threshold voltage of the transistor is lowered (becomes an erased state).

  In the FN type erasure, for example, voltages (Vmg = 12 V, Vs = 0 V, Vcg = 0 V, Vd = 0 V, Vb = 0V) is applied to each part of the selected memory cell to be erased, and in the selected memory cell, holes (holes) are tunneled from the memory gate electrode MG and injected into the silicon nitride film 6b in the insulating film 5. Erase. At this time, holes are injected into the insulating film 5 by tunneling the silicon oxide film 6 c from the memory gate MG by FN tunneling (FN tunneling effect), and trapped in trap levels in the silicon nitride film 6 b in the insulating film 5. As a result, the threshold voltage of the memory transistor decreases (becomes an erased state).

  In FN erasing, erasing can also be performed by tunneling holes from the semiconductor substrate 1 and injecting them into the silicon nitride film 6b in the insulating film 5. In this case, the erasing operation voltage is, for example, as shown in FIG. The sign of “erase operation voltage” in the column B or D in the table can be reversed.

  When writing or erasing is performed by the FN method (that is, in the case of the operation methods B, C, and D), when charges are tunneled from the memory gate electrode MG and injected into the silicon nitride film 6b, the silicon oxide film 6c It is preferable to make the film thickness thinner than the film thickness of the silicon oxide film 6a. On the other hand, when writing or erasing is performed by the FN method (that is, in the case of the operation methods B, C, and D), when charges are tunneled from the semiconductor substrate 1 and injected into the silicon nitride film 6b, the film of the silicon oxide film 6a It is preferable to make the thickness smaller than the thickness of the silicon oxide film 6c. In addition, when the writing is the SSI method and the erasing is the BTBT method (that is, the operation method A), the thickness of the silicon oxide film 6c is preferably set to be equal to or larger than the thickness of the silicon oxide film 6a.

  At the time of reading, for example, a voltage as shown in “reading operation voltage” in the columns A, B, C, or D in the table of FIG. 4 is applied to each part of the selected memory cell to be read. . The voltage Vmg applied to the memory gate electrode MG at the time of reading is set to a value between the threshold voltage of the memory transistor in the writing state and the threshold voltage in the erasing state, thereby discriminating between the writing state and the erasing state. can do.

  Next, a method for manufacturing the semiconductor device of the present embodiment will be described.

  FIG. 5 is a process flow diagram showing a part of the manufacturing process of the semiconductor device of the present embodiment. 6 to 29 are main-portion cross-sectional views during the manufacturing process of the semiconductor device of the present embodiment. Among these, the sectional views of FIGS. 6 to 11 and FIGS. 14 to 29 show the memory cell region (region where the memory cell MC of the nonvolatile memory is formed) 1A and the peripheral circuit region (circuits other than the nonvolatile memory). A cross-sectional view of a main part of the region 1B to be formed is shown, in which a memory cell MC is formed in the memory cell region 1A and a MISFET is formed in the peripheral circuit region 1B. 12 corresponds to the partially enlarged sectional view of FIG. 10, and FIG. 13 corresponds to the partially enlarged sectional view of FIG. The memory cell region 1A and the peripheral circuit region 1B are formed on the same semiconductor substrate 1. The memory cell region 1A and the peripheral circuit region 1B may not be adjacent to each other. However, in order to facilitate understanding, in the cross-sectional views of FIGS. 6 to 11 and FIGS. 14 to 29, the memory cell region 1A is adjacent to the memory cell region 1A. The peripheral circuit region 1B is illustrated. Here, the peripheral circuit is a circuit other than the nonvolatile memory, such as a processor such as a CPU, a control circuit, a sense amplifier, a column decoder, a row decoder, and an input / output circuit.

  In the present embodiment, the case where an n-channel MISFET (control transistor and memory transistor) is formed in the memory cell region 1A will be described. However, the p-channel MISFET (control transistor and Memory transistor) can also be formed in the memory cell region 1A. Similarly, in this embodiment, the case where an n-channel type MISFET is formed in the peripheral circuit region 1B will be described, but a p-channel type MISFET may be formed in the peripheral circuit region 1B with the conductivity type reversed. In addition, a CMISFET (Complementary MISFET) or the like can be formed in the peripheral circuit region 1B.

  As shown in FIG. 6, first, a semiconductor substrate (semiconductor wafer) 1 made of, for example, p-type single crystal silicon having a specific resistance of about 1 to 10 Ωcm is prepared (prepared) (step S1 in FIG. 5). Then, an element isolation region (inter-element isolation insulating region) 2 that defines (defines) an active region is formed on the main surface of the semiconductor substrate 1 (step S2 in FIG. 5). The element isolation region 2 is made of an insulator such as silicon oxide, and can be formed by, for example, an STI (Shallow Trench Isolation) method or a LOCOS (Local Oxidization of Silicon) method. For example, the element isolation region 2 can be formed by forming an element isolation groove in the main surface of the semiconductor substrate 1 and then embedding an insulating film made of, for example, silicon oxide in the element isolation groove. .

  Next, as shown in FIG. 7, a p-type well PW1 is formed in the memory cell region 1A of the semiconductor substrate 1 and a p-type well PW2 is formed in the peripheral circuit region 1B (step S3 in FIG. 5). The p-type wells PW1 and PW2 can be formed by ion-implanting a p-type impurity such as boron (B) into the semiconductor substrate 1, for example. The p-type wells PW1 and PW2 are formed from the main surface of the semiconductor substrate 1 to a predetermined depth.

  Next, in order to adjust the threshold voltage of a control transistor formed later in the memory cell region 1A, a channel is formed with respect to the surface portion (surface layer portion) of the p-type well PW1 in the memory cell region 1A as necessary. Dope ion implantation is performed. Further, in order to adjust the threshold voltage of the MISFET formed later in the peripheral circuit region 1B, channel dope ions are applied to the surface portion (surface layer portion) of the p-type well PW2 in the peripheral circuit region 1B as necessary. Make an injection.

  Next, after cleaning the surface of the semiconductor substrate 1 (p-type wells PW1, PW2) by dilute hydrofluoric acid cleaning or the like, the main surface of the semiconductor substrate 1 (surfaces of the p-type wells PW1, PW2) is used for the gate insulating film. The insulating film 3 is formed (step S4 in FIG. 5). The insulating film 3 can be formed of, for example, a thin silicon oxide film or a silicon oxynitride film. The film thickness (formed film thickness) of the insulating film 3 can be set to, for example, about 2 to 3 nm.

  Next, as shown in FIG. 8, a silicon film 4 is formed on the main surface (entire main surface) of the semiconductor substrate 1, that is, on the insulating film 3, as a conductor film (conductor film) for a gate electrode ( (Deposition) (step S5 in FIG. 5). The silicon film 4 is made of a polycrystalline silicon film and can be formed using a CVD (Chemical Vapor Deposition) method or the like. The film thickness (deposition film thickness) of the silicon film 4 can be set to, for example, about 50 to 250 nm. At the time of film formation, the silicon film 4 can be formed as an amorphous silicon film, and the amorphous silicon film can be converted into a polycrystalline silicon film by subsequent heat treatment.

  After the silicon film 4 is formed, a photoresist pattern (not shown here, but this photoresist pattern is formed over the entire peripheral circuit region 1B) is formed on the silicon film 4 by photolithography. Using the resist pattern as a mask (ion implantation blocking mask), an n-type impurity is introduced into the silicon film 4 in the memory cell region 1A by an ion implantation method or the like. As a result, the silicon film 4 in the memory cell region 1A becomes an n-type silicon film 4 (doped polysilicon film) by introducing n-type impurities.

  Next, a silicon film pattern (first silicon film pattern) SP1 is formed in the memory cell region 1A by patterning the silicon film 4 in the memory cell region 1A using photolithography technology and etching technology (step of FIG. 5). S6). The patterning step in step S6 can be performed as follows (see FIGS. 9 and 10).

  That is, first, as shown in FIG. 9, a photoresist pattern PR1 is formed on the silicon film 4 by using a photolithography method. The photoresist pattern PR1 is formed in the entire peripheral circuit region 1B and the region where the silicon film pattern SP1 is to be formed in the memory cell region 1A. Then, by using the photoresist pattern PR1 as an etching mask, the silicon film 4 is etched and patterned to form a silicon film pattern made of the patterned silicon film 4 in the memory cell region 1A as shown in FIG. SP1 is formed. At this time, since the photoresist pattern PR1 is formed in the peripheral circuit region 1B, the silicon film 4 is not patterned. The silicon film 4 remaining in the peripheral circuit region 1B can be regarded as a silicon film pattern (second silicon film pattern) SP2. The insulating film 3 remains under the silicon film pattern SP1. Accordingly, the silicon film pattern SP1 is formed on the semiconductor substrate 1 (p-type well PW1) via the insulating film 3. Thereafter, the photoresist pattern PR1 is removed. FIG. 10 shows a stage where the photoresist pattern PR1 is removed.

  Part of the silicon film pattern SP1 later becomes the control gate electrode CG, and the silicon film pattern SP1 has a side surface (fourth side surface, side wall) SP1a that becomes the side surface (side wall) 22 of the control gate electrode CG. .

  Specifically, the silicon film pattern SP1 has a pattern in which the control gate electrodes CG of the memory cells sharing the drain region are connected. For this reason, of the side surfaces (sidewalls) SP1a located on the opposite sides of the silicon film pattern SP1, one side surface (sidewall) SP1a later becomes the above-described one of the control gate electrodes CG of the memory cells sharing the drain region. The side surface 22 becomes the side surface 22 and the other side surface (side wall) SP1a later becomes the side surface 22 of the other control gate electrode CG of the memory cell sharing the drain region.

  In the memory cell region 1A, the insulating film 3 other than the portion covered with the silicon film pattern SP1 can be removed by dry etching performed in the patterning process of step S6 or wet etching after the dry etching.

  In the present embodiment, in step S6 (silicon film pattern SP1 formation process), as shown in FIG. 10, the silicon film pattern SP1 is moved so that the lower SP1b of the side surface SP1a of the silicon film pattern SP1 is retracted. Form. This can be realized by adjusting the etching conditions in step S6, and an example of the method will be described later.

  Next, in order to adjust the threshold voltage of a memory transistor formed later in the memory cell region 1A, the surface portion (surface layer portion) of the p-type well PW1 in the memory cell region 1A is adjusted as necessary. Channel doped ion implantation is performed.

  Next, after performing a cleaning process to clean the main surface of the semiconductor substrate 1, as shown in FIG. 11, the main surface (front surface) of the semiconductor substrate 1 and the surface (upper surface and side surfaces) of the silicon film pattern SP1. The insulating film 5 for the gate insulating film of the memory transistor is formed thereon (step S7 in FIG. 5). FIG. 12 is a partially enlarged cross-sectional view in which a part of the memory cell region 1A before the formation of the insulating film 5 is enlarged. FIG. 13 shows the memory cell region 1A at the stage where the insulating film 5 is formed. It is the partial expanded sectional view which expanded a part. For this reason, FIG. 12 corresponds to a partially enlarged sectional view in which a part of FIG. 10 is enlarged, and FIG. 13 corresponds to a partially enlarged sectional view in which a part of FIG. 11 is enlarged.

  As described above, the insulating film 5 is an insulating film having a charge storage portion (charge storage layer) inside, and as the insulating film, the silicon oxide film 6a, the silicon nitride film 6b, and the silicon oxide film formed in this order from the bottom. In order to make the drawing easier to see, FIG. 11 shows the stacked film of the silicon oxide film 6a, the silicon nitride film 6b and the silicon oxide film 6c as the insulating film 5 simply. Therefore, actually, as shown in FIG. 13, the insulating film 5 is formed on the silicon oxide film (oxide film) 6a, the silicon nitride film (nitride film) 6b on the silicon oxide film 6a, and the silicon nitride film 6b. And a silicon oxide film (oxide film) 6c. In step S7, as shown in FIGS. 11 and 13, the insulating film 5 includes the main surface (surface) of the semiconductor substrate 1 (including the p-type well PW1 and the element isolation region 2) and the surface of the silicon film pattern SP1 (see FIG. 11). (Side surface and upper surface) and the surface (side surface and upper surface) of the silicon film 4 (however, the insulating film 5 is not formed below the silicon film pattern SP1 and below the silicon film 4). In general, the insulating film 5 is also formed on the element isolation region 2 in the film forming process, but the insulating film 5 may not be formed on the element isolation region 2.

  Of the insulating film 5, the silicon oxide films 6a and 6c can be formed by, for example, an oxidation process (thermal oxidation process), a CVD method, or a combination thereof. It is possible to use ISSG (In Situ Steam Generation) oxidation for the oxidation treatment (thermal oxidation treatment) at this time. Of the insulating film 5, the silicon nitride film 6b can be formed by, for example, a CVD method.

  In this embodiment, the silicon nitride film 6b is formed as the insulating film (charge storage layer) having a trap level. However, a silicon nitride film is preferable in terms of reliability, but nitriding The charge storage layer (charge storage portion) is not limited to a silicon film, and a high dielectric constant film having a dielectric constant higher than that of a silicon nitride film, such as an aluminum oxide film (alumina), a hafnium oxide film, or a tantalum oxide film, is used. It can also be used. In addition, a charge storage layer (charge storage portion) can be formed using silicon nanodots.

  In order to form the insulating film 5, for example, on the surface of the semiconductor substrate 1 (p-type well PW1), on the surface (side surface and upper surface) of the silicon film pattern SP1, and on the surface (side surface and upper surface) of the silicon film 4 After the silicon oxide film 6a is formed by a thermal oxidation method (preferably ISSG oxidation), a silicon nitride film 6b is deposited on the silicon oxide film 6a by a CVD method, and a silicon oxide film 6c is further formed on the silicon nitride film 6b by CVD. Formed by process and / or thermal oxidation. Thereby, the insulating film 5 composed of a laminated film of the silicon oxide film 6a, the silicon nitride film 6b, and the silicon oxide film 6c can be formed.

  The thickness of the silicon oxide film 6a can be, for example, about 2 to 10 nm, the thickness of the silicon nitride film 6b can be, for example, about 5 to 15 nm, and the thickness of the silicon oxide film 6c can be, for example, 2 to 10 nm. Can be about. The last oxide film (the uppermost silicon oxide film 6c of the insulating film 6) is formed by, for example, oxidizing the upper layer portion of the nitride film (intermediate silicon nitride film 6b of the insulating film 5). A high breakdown voltage film can also be formed.

  The insulating film 5 functions as a gate insulating film of a memory gate electrode MG to be formed later, and has a charge holding (charge accumulation) function. Therefore, the insulating film 5 has a laminated structure of at least three layers so that it can function as a gate insulating film having a charge holding (charge accumulation) function of the memory transistor, and the outer layers (silicon oxide films 6a and 6c). The potential barrier height of the inner layer (silicon nitride film 6b) is lower than the potential barrier height. This is because, as in the present embodiment, the insulating film 5 includes a silicon oxide film 6a, a stacked film including a silicon nitride film 6b on the silicon oxide film 6a, and a silicon oxide film 6c on the silicon nitride film 6b. This can be achieved.

  Next, as shown in FIG. 14, the peripheral circuit region is formed on the main surface (entire main surface) of the semiconductor substrate 1, that is, on the insulating film 5 so as to cover the silicon film pattern SP1 in the memory cell region 1A. In 1B, a silicon film 7 is formed (deposited) as a conductor film for forming the memory gate electrode MG so as to cover the silicon film 4 (step S8 in FIG. 5). 14 and the subsequent FIGS. 15 to 29, similarly to FIG. 11, the laminated film of the silicon oxide film 6a, the silicon nitride film 6b, and the silicon oxide film 6c is simply an insulating film in order to make the drawing easy to see. This is illustrated as 5.

  The silicon film 7 is made of a polycrystalline silicon film and can be formed using a CVD method or the like. The film thickness (deposition film thickness) of the silicon film 7 can be, for example, about 30 to 150 nm. At the time of film formation, the silicon film 7 can be formed as an amorphous silicon film, and the amorphous silicon film can be converted into a polycrystalline silicon film by subsequent heat treatment.

  The silicon film 7 has a low resistance by introducing n-type impurities. Although n-type impurities can be introduced into the silicon film 7 by ion implantation after the formation of the silicon film 7, n-type impurities can also be introduced into the silicon film 7 when the silicon film 7 is formed. In the case where n-type impurities are introduced when the silicon film 7 is formed, the n-type impurities are introduced by including a doping gas (gas for adding n-type impurities) in the gas for forming the silicon film 7. The silicon film 7 can be formed. In any case, a silicon film 7 into which an n-type impurity is introduced is formed in the memory cell region 1A and the peripheral circuit region 1B.

  Next, the silicon film 7 is etched back (etching, dry etching, anisotropic etching) by an anisotropic etching technique to form the memory gate electrode MG (step S9 in FIG. 5).

  In the etch back process of step S9, the silicon film 7 is anisotropically etched (etched back) by an amount corresponding to the deposited film thickness of the silicon film 7, so that (insulating) is formed on both side surfaces (side walls) SP1a of the silicon film pattern SP1. The silicon film 7 is left in the form of sidewall spacers (via the film 5), and the silicon film 7 in other regions is removed. Thereby, as shown in FIG. 15, in the memory cell region 1A, the silicon film 7 remaining in the shape of the sidewall spacer via the insulating film 5 on both side surfaces (side walls) SP1a of the silicon film pattern SP1. A memory gate electrode MG is formed. The memory gate electrode MG is formed on the insulating film 5 so as to be adjacent to the silicon film pattern SP1 with the insulating film 5 interposed therebetween. Also, the silicon film 7 remains in the shape of a sidewall spacer on the side surface (side wall) of the silicon film 4 remaining in the peripheral circuit region 1B through the insulating film 5, and this is referred to as a silicon spacer 8. And

  In the stage where the etch back process of step S9 is performed, the insulating film 5 in the region not covered with the memory gate electrode MG and the silicon spacer 8 is exposed. The insulating film 5 under the memory gate electrode MG in the memory cell region 1A becomes a gate insulating film of the memory transistor. The memory gate length can be adjusted by adjusting the deposited film thickness of the silicon film 7 deposited in step S8.

  Further, in the above step S6 (silicon film pattern SP1 formation step), the silicon film pattern SP1 is formed in a structure in which the lower portion 31a of the side surface SP1a of the silicon film pattern SP1 is recessed, so that the memory formed in step S9. The gate electrode MG has a structure in which the lower part of the side surface (the side surface 23) adjacent to the control gate electrode CG via the insulating film 5 protrudes toward the control gate electrode CG.

  Next, as shown in FIG. 16, a portion of the insulating film 5 that is exposed without being covered with the memory gate electrode MG and the silicon spacer 8 is removed by etching (for example, wet etching) (step S10 in FIG. 5). . At this time, in the memory cell region 1A, the insulating film 5 located under the memory gate electrode MG and between the memory gate electrode MG and the silicon film pattern SP1 remains without being removed, and the insulating film 5 in other regions remains. Removed. As can be seen from FIG. 16, in the memory cell region 1A, both the region between the memory gate electrode MG and the semiconductor substrate 1 (p-type well PW1) and the region between the memory gate electrode MG and the silicon film pattern SP1. The insulating film 5 extends continuously over the region.

  Next, the control gate electrode CG is formed in the memory cell region 1A by patterning the silicon film pattern SP1 in the memory cell region 1A using a photolithography technique and an etching technique (step S11 in FIG. 5). The patterning process in step S11 can be performed as follows (see FIGS. 17 and 18).

  That is, first, as shown in FIG. 17, a photoresist pattern PR2 is formed on the main surface of the semiconductor substrate 1 by using a photolithography method. In the memory cell region 1A, the photoresist pattern PR2 covers the memory gate electrode MG and the silicon film pattern SP1 that is to be the control gate electrode CG adjacent thereto (adjacent via the insulating film 5). A portion of the silicon film pattern SP1 that does not become the control gate electrode CG is formed so as to be exposed. That is, in the memory cell region 1A, the photoresist pattern PR2 covers the memory gate electrode MG and the control gate electrode CG formation scheduled adjacent to the memory gate electrode MG, and exposes a portion of the silicon film pattern SP1 that does not become the control gate electrode CG. To be formed. On the other hand, in the peripheral circuit region 1B, a photoresist pattern PR2 is formed entirely, and the silicon film 4 in the peripheral circuit region 1B is covered with the photoresist pattern PR2. Then, using the photoresist pattern PR2 as an etching mask, the silicon film pattern SP1 is etched and patterned, thereby forming a control gate electrode CG in the memory cell region 1A as shown in FIG. Thereafter, the photoresist pattern PR2 is removed. FIG. 18 shows a stage where the photoresist pattern PR2 is removed.

  The control gate electrode CG is composed of a patterned silicon film pattern SP1. As described above, since the silicon film pattern SP1 is made of the patterned silicon film 4, the control gate electrode CG is formed by the silicon film 4. In the memory cell region 1A, the insulating film 3 remaining under the control gate electrode CG becomes the gate insulating film of the control transistor. Therefore, the control gate electrode CG is formed on the semiconductor substrate 1 (p-type well PW) via the insulating film 3 as a gate insulating film, and the control gate electrode CG is connected to the memory gate electrode MG via the insulating film 5. Next to each other.

  Further, when the silicon film pattern SP1 is etched in step 11, the memory gate electrode MG remains covered without being etched because it is covered with the photoresist pattern PR2. The insulating film 5 continuously extends over both the region between the memory gate electrode MG and the semiconductor substrate 1 (p-type well PW1) and the region between the memory gate electrode MG and the control gate electrode CG. Yes. Further, when the silicon film pattern SP1 is etched in step 11, the photoresist pattern PR2 is formed in the peripheral circuit region 1B, so that the patterning of the silicon film 4 in the peripheral circuit region 1B is not performed.

  In the present embodiment, in step S11 (control gate electrode CG formation step), as shown in FIG. 18, the silicon film pattern SP1 is formed so that the lower portion 21a of the side surface 21 of the control gate electrode CG protrudes. The control gate electrode CG is formed by processing. This can be realized by adjusting the etching conditions in step S11, and an example of the method will be described later.

  Next, a photoresist pattern is formed on the main surface of the semiconductor substrate 1 using a photolithography method (this photoresist pattern is formed in the p-channel type MISFET formation scheduled region in the entire memory cell region 1A and the peripheral circuit region 1B, though not shown here). Using this photoresist pattern as a mask, an n-type impurity is introduced into the silicon film 4 in the n-channel MISFET formation planned region of the peripheral circuit region 1B by an ion implantation method or the like. As a result, in the peripheral circuit region 1B, the silicon film 4 in the n-channel MISFET formation planned region becomes the n-type silicon film 4 by introducing the n-type impurity.

  Next, the gate electrode GE is formed in the peripheral circuit region 1B by patterning the silicon film 4 (that is, the silicon film pattern SP2) in the peripheral circuit region 1B by using the photolithography technique and the etching technique (step S12 in FIG. 5). ). The patterning step in step S12 can be performed as follows (see FIGS. 19 and 20).

  That is, first, as shown in FIG. 19, a photoresist pattern PR3 is formed on the main surface of the semiconductor substrate 1 by using a photolithography method. The photoresist pattern PR3 is formed in the entire memory cell region 1A and the gate electrode GE formation region in the peripheral circuit region 1B. Then, using this photoresist pattern PR3 as an etching mask, the silicon film 4 (that is, the silicon film pattern SP2) in the peripheral circuit region 1B is patterned by etching to form the gate electrode GE as shown in FIG. . At this time, the silicon spacer 8 can also be removed by etching. On the other hand, since the memory cell region 1A is covered with the photoresist pattern, the memory gate electrode MG and the control gate electrode CG are not etched. Thereafter, the photoresist pattern PR3 is removed. FIG. 20 shows a stage where the photoresist pattern PR3 is removed.

  In this way, as shown in FIG. 20, the gate electrode GE made of the patterned n-type silicon film 4 is formed. The gate electrode GE is a gate electrode of a MISFET that constitutes a circuit other than the nonvolatile memory.

Next, using an ion implantation method or the like, an n-type impurity such as arsenic (As) or phosphorus (P) is used as a mask (ion implantation blocking mask) using the control gate electrode CG, the memory gate electrode MG, and the gate electrode GE. By using (doping) into the semiconductor substrate 1 (p-type wells PW1, PW2), n ⁻ -type semiconductor regions (impurity diffusion layers) EX1, EX2, EX3 are formed as shown in FIG. 5 step S13).

At this time, the n ⁻ -type semiconductor region EX1 is self-aligned with the side surface 24 of the memory gate electrode MG (the side surface 24 opposite to the side adjacent to the control gate electrode CG via the insulating film 5) in the memory cell region 1A. Formed. The n ⁻ type semiconductor region EX2 is self-aligned with the side surface 21 of the control gate electrode CG (the side surface 21 opposite to the side adjacent to the memory gate electrode MG via the insulating film 5) in the memory cell region 1A. Formed. Further, the n ⁻ type semiconductor region EX3 is formed in self-alignment with both side walls of the gate electrode GE in the peripheral circuit region 1B. The n ⁻ type semiconductor region EX1 and the n ⁻ type semiconductor region EX2 function as a part of the source / drain region (source or drain region) of the memory cell formed in the memory cell region 1A, and the n ⁻ type semiconductor region EX3 It can function as a part of the source / drain region (source or drain region) of the MISFET formed in the peripheral circuit region 1B. The n ⁻ type semiconductor region EX1, the n ⁻ type semiconductor region EX2, and the n ⁻ type semiconductor region EX3 can be formed by the same ion implantation process, but can also be formed by different ion implantation processes. Further, the ion implantation for forming the n ⁻ type semiconductor regions EX1, EX2, and EX3 is preferably performed not in the oblique ion implantation but in a direction perpendicular to the main surface of the semiconductor substrate 1.

Next, ion implantation (halo ion implantation) of a p-type impurity is performed on the semiconductor substrate 1 (p-type well PW1) in the memory cell region 1A to form a halo region (p-type semiconductor region) HA (step of FIG. 5). S14). The halo region HA is formed so as to enclose (cover) the n ⁻ type semiconductor region EX2, and has an impurity concentration (p type impurity concentration) higher than that of the p type well PW1.

Halo region HA is, n ^- a halo region formed against type semiconductor region EX2, the p-type well PW1 n ^- -type wrap around the semiconductor region EX2 (cover) as are formed, n ^- -type semiconductor region The conductivity type is opposite to that of EX2, and the same conductivity type as that of the p-type well PW1 is p-type (p-type semiconductor region) here. The halo region HA is formed to suppress short channel characteristics (punch through).

At the time of ion implantation for forming the halo region HA, the control gate electrode CG can function as a mask (ion implantation blocking mask). However, ion implantation for forming the halo region HA is performed by oblique ion implantation ( (Inclined ion implantation) is more preferable, whereby the halo region HA can be accurately formed so as to wrap (cover) the n ⁻ type semiconductor region EX2. In general ion implantation, impurity ions are accelerated and implanted in a direction perpendicular to the main surface of the semiconductor substrate 1. In oblique ion implantation, a predetermined direction from a direction perpendicular to the main surface of the semiconductor substrate 1 is used. Impurity ions are accelerated and implanted in an inclined direction.

Further, the n ⁻ type semiconductor region EX2 and the halo region HA do not necessarily have to be formed in this order, but the ion implantation for forming the n ⁻ type semiconductor region EX2 and the ion implantation for forming the halo region HA are at least It is necessary to carry out after forming the control gate electrode CG and before forming a side wall spacer SW described later.

Further, since the halo region HA is formed to suppress the short channel characteristic, it is formed with respect to the n ⁻ type semiconductor region EX2 for drain (it is formed so as to wrap around the n ⁻ type semiconductor region EX2). It is not necessary to form the halo region HA for the n ⁻ type semiconductor region EX1. Therefore, at the time of ion implantation for forming the halo region HA, the n ⁻ type semiconductor region EX1 for the source is covered with a photoresist pattern, and the p ⁻ type is applied to the n ⁻ type semiconductor region EX1. The halo region may be prevented from being formed. In the case of FIG. 21, ion implantation for forming the halo region HA is performed with the entire peripheral circuit region 1B and the n ⁻ type semiconductor region EX1 of the memory cell region 1A covered with a photoresist pattern (not shown). In this case, the halo region HA is formed for the n ⁻ type semiconductor region EX2, but the halo region is not formed for the n ⁻ type semiconductor region EX1 and the n ⁻ type semiconductor region EX3. As another form, a halo region can be formed for the n ⁻ type semiconductor region EX1 and the n ⁻ type semiconductor region EX3 in order to suppress short channel characteristics.

  Next, an insulator (insulating film) such as silicon oxide is formed on the side surfaces of the control gate electrode CG and the memory gate electrode MG (side surfaces 21 and 24 opposite to the side adjacent to each other via the insulating film 5). A sidewall spacer SW is formed (step S15 in FIG. 5). The sidewall spacer SW forming step in step S15 can be performed as follows (see FIGS. 22 and 23).

  That is, first, as shown in FIG. 22, an insulating film 9 such as a silicon oxide film is formed (deposited) on the entire main surface of the semiconductor substrate 1. Then, the insulating film 9 is selectively etched on the side surfaces 21 and 24 of the control gate electrode CG and the memory gate electrode MG as shown in FIG. 23 by anisotropic etching (etchback). And sidewall spacers SW are formed. The sidewall spacer SW is formed on the side surfaces of the control gate electrode CG and the memory gate electrode MG (side surfaces 21 and 24 opposite to the side adjacent to each other via the insulating film 5) and on both side surfaces (side walls) of the gate electrode GE. Formed on top.

Next, as shown in FIG. 24, n ⁺ -type semiconductor regions (impurity diffusion layers) 10a, 10b, and 10c are formed using an ion implantation method or the like (step S16 in FIG. 5).

For example, an n-type impurity such as arsenic (As) or phosphorus (P) is masked (ion-implanted) with the control gate electrode CG, the memory gate electrode MG, the gate electrode GE, and the side wall spacers SW on the side surfaces (side walls). By introducing it into the semiconductor substrate 1 (p-type wells PW1, PW2) as a blocking mask, the n ⁺ -type semiconductor regions 10a, 10b, 10c can be formed. At this time, the n ⁺ type semiconductor region 10a is formed in self alignment with the sidewall spacer SW on the side surface 24 of the memory gate electrode MG in the memory cell region 1A, and the n ⁺ type semiconductor region 10b is formed in the memory cell region 1A. In FIG. 6, the gate electrode is formed in self-alignment with the sidewall spacer SW on the side surface 21 of the control gate electrode CG. The n ⁺ type semiconductor region 10c is formed in self-alignment with the sidewall spacer SW on both side surfaces of the gate electrode GE in the peripheral circuit region 1B. Thereby, an LDD (lightly doped drain) structure is formed.

In this manner, n ^- -type semiconductor region EX1 and than by the n ⁺ -type semiconductor region 10a of high impurity concentration, n-type semiconductor region MS functioning as a source region of the memory transistor is formed, n ^- -type semiconductor The region EX2 and the n ⁺ type semiconductor region 10b having a higher impurity concentration than the region EX2 form an n type semiconductor region MD that functions as a drain region of the control transistor. The n ⁻ type semiconductor region EX3 and the n ⁺ type semiconductor region 10c having a higher impurity concentration than the n ⁻ type semiconductor region EX3 form an n type semiconductor region SD that functions as a source / drain region of the MISFET in the peripheral circuit region 1B.

Next, the impurities introduced into the n-type semiconductor regions MS, MD, SD (n ⁻ type semiconductor regions EX1, EX2, EX3 and n ⁺ type semiconductor regions 10a, 10b, 10c) for the source and drain are activated. Activation annealing, which is a heat treatment for the purpose, is performed.

  In this manner, the memory cell MC of the nonvolatile memory is formed in the memory cell region 1A, and the MISFET is formed in the peripheral circuit region 1B.

Next, a silicon oxide film is formed on the entire main surface of the semiconductor substrate 1 by a CVD method or the like. Then, the upper surfaces (surfaces) of the n ⁺ type semiconductor regions 10a, 10b, and 10c, the upper surfaces of the control gate electrodes CG, the upper surfaces of the memory gate electrodes MG, and the upper surfaces of the gate electrodes GE are formed by photolithography and etching. (Silicon region, silicon film) is exposed. Then, as shown in FIG. 25, on the upper surfaces (surfaces) of the n ⁺ type semiconductor regions 10a, 10b, and 10c, on the upper surfaces (portions not covered with the sidewall spacers SW) of the memory gate electrode MG, and the control gate electrodes. The metal film 11 covers the control gate electrode CG, the memory gate electrode MG, the gate electrode GE, and the sidewall spacer SW over the entire main surface of the semiconductor substrate 1 including the upper surface of the CG and the upper surface of the gate electrode GE. Is formed (deposited). The metal film 11 is made of, for example, a cobalt (Co) film or a nickel (Ni) film, and can be formed using a sputtering method or the like.

Next, by subjecting the semiconductor substrate 1 to heat treatment, the upper layer portion (surface layer portion) of the n ⁺ type semiconductor regions 10a, 10b, and 10c, the control gate electrode CG, the memory gate electrode MG, and the gate electrode GE is changed to the metal film 11. React with. As a result, as shown in FIG. 26, metal silicide is formed on the n ⁺ type semiconductor regions 10a, 10b, 10c, the control gate electrode CG, the memory gate electrode MG, and the gate electrode GE, respectively (upper surface, surface, upper layer portion). Layer 12 is formed. The metal silicide layer 12 can be, for example, a cobalt silicide layer (when the metal film 11 is a cobalt film) or a nickel silicide layer (when the metal film 11 is a nickel film). Thereafter, the unreacted metal film 11 is removed. FIG. 26 shows a cross-sectional view at this stage. Thus, by performing a so-called salicide process, the metal silicide layer 12 is formed on the n ⁺ type semiconductor regions 10a, 10b, and 10c, the control gate electrode CG, the memory gate electrode MG, and the gate electrode GE. The resistance of the source, drain and each gate electrode (CG, MG, GE) can be reduced.

  Next, as shown in FIG. 27, an insulating film as an interlayer insulating film is formed on the entire main surface of the semiconductor substrate 1 so as to cover the control gate electrode CG, the memory gate electrode MG, the gate electrode GE, and the sidewall spacer SW. (Interlayer insulating film) 13 is formed (deposited). The insulating film 13 is composed of a single film of a silicon oxide film or a laminated film of a silicon nitride film and a silicon oxide film formed thicker than the silicon nitride film on the silicon nitride film. Can be formed. After the formation of the insulating film 13, the upper surface of the insulating film 13 is planarized using a CMP (Chemical Mechanical Polishing) method or the like as necessary.

  Next, the insulating film 12 is dry-etched using a photoresist pattern (not shown) formed on the insulating film 13 by photolithography as an etching mask, as shown in FIG. Contact holes (openings, through-holes) CNT are formed in the substrate.

  Next, a conductive plug PG made of tungsten (W) or the like is formed in the contact hole CNT as a conductor portion (connection conductor portion).

  In order to form the plug PG, for example, a barrier conductor film (for example, a titanium film, a titanium nitride film, or a laminated film thereof) is formed on the insulating film 13 including the inside (on the bottom and side walls) of the contact hole CNT. . Then, a main conductor film made of a tungsten film or the like is formed on the barrier conductor film so as to fill the contact holes CNT, and unnecessary main conductor films and barrier conductor films on the insulating film 13 are formed by a CMP method or an etch back method. By removing, the plug PG can be formed. For simplification of the drawing, FIG. 28 shows the barrier conductor film and the main conductor film (tungsten film) constituting the plug PG in an integrated manner.

The contact hole CNT and the plug PG embedded in the contact hole CNT are formed on the n ⁺ type semiconductor regions 10a, 10b, and 10c, the control gate electrode CG, the memory gate electrode MG, the upper portion of the gate electrode GE, and the like. At the bottom of the contact hole CNT, a part of the main surface of the semiconductor substrate 1, for example, a part of the n ⁺ type semiconductor regions 10a, 10b, 10c (the metal silicide layer 12 on the surface thereof), the control gate electrode CG (on the surface) Part of the metal silicide layer 12), part of the memory gate electrode MG (metal silicide layer 12 on the surface thereof), part of the gate electrode GE (metal silicide layer 12 on the surface thereof), etc. are exposed. . In the cross-sectional view of FIG. 28, a part of the n ⁺ -type semiconductor regions 10b and 10c (the metal silicide layer 12 on the surface thereof) is exposed at the bottom of the contact hole CNT, and is a plug PG that fills the contact hole CNT. And a cross section electrically connected to each other.

  Next, as shown in FIG. 29, the insulating film 14 is formed on the insulating film 13 in which the plug PG is embedded. The insulating film 14 can also be formed of a stacked film of a plurality of insulating films.

  Next, the wiring M1 which is the first layer wiring is formed by a single damascene method. Specifically, the wiring M1 can be formed as follows. First, after a wiring groove is formed in a predetermined region of the insulating film 14 by dry etching using a photoresist pattern (not shown) as a mask, a barrier conductor film (on the insulating film 14 including the bottom and side walls of the wiring groove is formed. For example, a titanium nitride film, a tantalum film, a tantalum nitride film, or the like is formed. Subsequently, a copper seed layer is formed on the barrier conductor film by a CVD method or a sputtering method, and a copper plating film is further formed on the seed layer by using an electrolytic plating method. Embed the inside. Then, the main conductor film (copper plating film and seed layer) and the barrier conductor film in the region other than the wiring trench are removed by the CMP method, and the first layer wiring using the copper buried in the wiring trench as the main conductive material M1 is formed. For simplification of the drawing, the wiring M1 is shown by integrating a barrier conductor film, a seed layer, and a copper plating film.

  The wiring M1 is connected via a plug PG to the source region (semiconductor region MS) of the memory transistor, the drain region (semiconductor region MD) of the control transistor, the source / drain region (semiconductor region SD) of the MISFET in the peripheral circuit region 1B, and the control gate. It is electrically connected to the electrode CG, the memory gate electrode MG, the gate electrode GE, or the like. Thereafter, the second and subsequent wirings are formed by a dual damascene method or the like, but illustration and description thereof are omitted here. Further, the wiring M1 and the wiring higher than that are not limited to damascene wiring, and can be formed by patterning a conductor film for wiring, for example, tungsten wiring or aluminum wiring.

  As described above, the semiconductor device of the present embodiment is manufactured.

  Next, the configuration and effects of the present embodiment will be described in more detail.

  One of the main features of the semiconductor device of the present embodiment is that the lower portion 21a of the side surface 21 of the control gate electrode CG is on the semiconductor region MD side (the side closer to the semiconductor region MD, that is, the side away from the memory gate electrode MG). It is protruding (protruding, protruding, overhanging). That is, when viewed in a cross section parallel to the gate length direction of the control gate electrode CG (FIGS. 1 and 2 correspond to this cross section), as can be seen from FIGS. 1 and 2, the side surface of the control gate electrode CG 21 has a lower portion 21a protruding toward the semiconductor region MD. That is, the side surface 21 of the control gate electrode CG is a substantially flat surface (a surface substantially perpendicular to the main surface of the semiconductor substrate 1) except for the lower portion 21a, whereas the lower portion 21a protrudes toward the semiconductor region MD. ing. Further, the fact that the lower portion 21a of the side surface 21 of the control gate electrode CG protrudes toward the semiconductor region MD means that the lower end portion of the control gate electrode CG on the semiconductor region MD side protrudes toward the semiconductor region MD. Yes. In addition, the lower portion 21a of the side surface 21 of the control gate electrode CG protrudes toward the semiconductor region MD so that the lower surface 25 of the control gate electrode CG extends in the gate length direction (the gate length direction of the control gate electrode CG). This means that the lower portion 21a of the side surface 21 of the control gate electrode CG protrudes (that is, the lower end portion of the control gate electrode CG on the semiconductor region MD side protrudes).

  Here, the control gate electrode CG has side surfaces 21 and 22 located on opposite sides, but the side surface 22 of the control gate electrode CG is adjacent (opposed) to the memory gate electrode MG through the insulating film 5. The side surface 21 of the control gate electrode CG is the side surface opposite to the side surface 22. The side surface 21 of the control gate electrode CG can be regarded as a side surface on the semiconductor region MD side, and the side surface 22 of the control gate electrode CG can be regarded as a side surface on the control gate electrode CG side. Although the sidewall spacer SW is formed on the side surface 21 of the control gate electrode CG, the memory gate electrode MG is formed on the side surface 22 of the control gate electrode CG with the insulating film 5 interposed therebetween. The side wall spacer SW is not formed on the side surface 22 of the electrode CG. The lower surface 25 of the control gate electrode CG is a surface facing the semiconductor substrate 1 (p-type well PW1) with the insulating film 3 interposed therebetween. The lower end portion of the control gate electrode CG on the semiconductor region MD side corresponds to the lower end portion (corner portion) sandwiched between the lower portion 21a of the side surface 21 of the control gate electrode CG and the lower surface 25 of the control gate electrode CG. .

  In the present embodiment, since the lower portion 21a of the side surface 21 of the control gate electrode CG protrudes toward the semiconductor region MD, the distance (interval) L1 between the control gate electrode CG and the plug PG is not reduced. The gate length (effective gate length) of the control gate electrode CG can be increased. That is, when the distance L1 between the control gate electrode CG and the plug PG is constant, the lower portion 21a of the side surface 21 of the control gate electrode CG protrudes toward the semiconductor region MD and does not protrude (that is, this embodiment). Compared with the case where the entire side surface 21 is a flat surface, the gate length of the control gate electrode CG is larger in the former (when the lower portion 21a of the side surface 21 protrudes) in the semiconductor region MD side. The distance is increased by the distance L2 projecting into the position.

  Here, the distance L1 between the control gate electrode CG and the plug PG is the distance between the upper portion of the side surface 21 of the control gate electrode CG and the plug PG (however, in the direction parallel to the gate length of the control gate electrode CG). Distance) and is shown in FIG. The distance L2 at which the lower portion 21a of the side surface 21 of the control gate electrode CG protrudes toward the semiconductor region MD is the side surface 21 on the basis of the substantially flat surface other than the lower portion 21a among the side surfaces 21 of the control gate electrode CG. 2 corresponds to the distance at which the lower portion 21a (the lower end portion of the control gate electrode CG on the semiconductor region MD side) protrudes toward the semiconductor region MD side, and is shown in FIG.

  If the distance L1 between the control gate electrode CG and the plug PG is reduced, the control gate electrode CG and the plug PG are likely to be close to each other or short-circuited, so that the manufacturing yield and reliability of the semiconductor device may be reduced. There is sex. For this reason, in order to surely prevent a short circuit between the control gate electrode CG and the plug PG and to reliably prevent a decrease in reliability due to the proximity of the control gate electrode CG and the plug PG, the control gate electrode It is desirable that the distance L1 between the CG and the plug PG should have a value (distance) of a certain level or more. On the other hand, unlike the present embodiment, when the entire side surface 21 of the control CG is a flat surface, the gate length of the control gate electrode CG should be increased while increasing the distance L1 between the control gate electrode CG and the plug PG. As a result, the size of the memory cell (the size in the direction parallel to the gate length of the control gate electrode CG) increases, which leads to downsizing (smaller area) and higher performance (increasing memory capacity) of the semiconductor device. It is disadvantageous in terms.

  On the other hand, in the present embodiment, the lower portion 21a of the side surface 21 of the control gate electrode CG protrudes toward the semiconductor region MD, so that the distance L1 between the control gate electrode CG and the plug PG is not reduced. The gate length of the control gate electrode CG can be increased. That is, when the distance L1 between the control gate electrode CG and the plug PG is constant, the lower portion 21a of the side surface 21 of the control gate electrode CG protrudes toward the semiconductor region MD, thereby causing the distance protruding toward the semiconductor region MD. The gate length of the control gate electrode CG can be increased by the amount L2. Therefore, the manufacturing yield and reliability of the semiconductor device can be improved, and the semiconductor device can be reduced in size (smaller area) and higher in performance (increase in memory capacity).

  In addition, when the lower portion 21a of the side surface 21 of the control gate electrode CG is protruded toward the semiconductor region MD, compared to the case where the lower portion 21a is not protruded (that is, the entire side surface 21 is a flat surface unlike the present embodiment). The distance between the lower portion 21a of the side surface 21 of the control gate electrode CG and the plug PG becomes small. However, the contact hole CNT and the plug PG filling it are tapered. That is, the side wall of contact hole CNT (that is, the side surface of plug PG) is inclined from the direction perpendicular to the main surface of semiconductor substrate 1 (contact hole CNT and plug PG that embeds it have a smaller diameter in the lower part than in the upper part). Is inclined to be). When the plug PG has a taper shape, in the control gate electrode CG, the portion close to the plug PG is the upper portion of the side surface 21 of the control gate electrode CG.

  For this reason, even if the lower portion 21a of the side surface 21 of the control gate electrode CG protrudes toward the semiconductor region MD and the lower portion 21a of the side surface 21 of the control gate electrode CG approaches the plug PG, the taper shape of the plug PG The distance between the lower portion 21a of the side surface 21 of the control gate electrode CG and the plug PG can be sufficiently ensured. That is, when the entire side surface 21 of the control gate electrode CG is brought close to the plug PG, there is a concern that the manufacturing yield and the reliability may be lowered. However, as in the present embodiment, the side surface 21 of the control gate electrode CG Even if the parts other than the lower part 21a are separated from the plug PG and only the lower part 21a is protruded so as to approach the plug PG, the lower part 21a of the side surface 21 of the control gate electrode CG and the plug PG are formed due to the tapered shape of the plug PG. The distance between can be secured. For this reason, the proximity or short circuit between the control gate electrode CG and the plug PG can be prevented accurately, and the manufacturing yield and reliability of the semiconductor device can be improved.

  Another main feature of the semiconductor device of the present embodiment is that the lower portion 22a of the side surface 22 of the control gate electrode CG is on the semiconductor region MD side (the side closer to the semiconductor region MD, that is, the side away from the memory gate electrode MG). Is retracted (recessed, recessed). That is, when viewed in a cross section parallel to the gate length direction of the control gate electrode CG (FIGS. 1 and 2 correspond to this cross section), as can be seen from FIGS. 1 and 2, the side surface of the control gate electrode CG 22, the lower part 22 a recedes to the semiconductor region MD side (side approaching the semiconductor region MD, that is, side away from the memory gate electrode MG). That is, the side surface 22 of the memory gate electrode MG is a substantially flat surface (a surface substantially perpendicular to the main surface of the semiconductor substrate 1) except for the lower portion 22a, whereas the lower portion 22a recedes toward the semiconductor region MD. is doing. Further, the lower part 22a of the side surface 22 of the control gate electrode CG is retracted to the semiconductor region MD side. This means that the lower end portion of the control gate electrode CG on the memory gate electrode MG side is retracted to the semiconductor region MD side. I mean. Further, the lower part 22a of the side surface 22 of the control gate electrode CG recedes to the semiconductor region MD side so that the lower surface 25 of the control gate electrode CG shrinks in the gate length direction (gate length direction of the control gate electrode CG). This means that the lower portion 22a of the side surface 22 of the control gate electrode CG is retracted (that is, the lower end portion of the control gate electrode CG on the memory gate electrode MG side is retracted).

  Still another major feature of the semiconductor device of the present embodiment is that the lower portion 23a of the side surface 23 of the memory gate electrode MG is away from the control gate electrode CG side (the side closer to the control gate electrode CG, that is, the semiconductor region MS). (Protruding, protruding, overhanging). That is, when viewed in a cross section parallel to the gate length direction of the control gate electrode CG (FIGS. 1 and 2 correspond to this cross section), as can be seen from FIGS. 1 and 2, the side surface of the memory gate electrode MG 23, the lower part 23a protrudes to the control gate electrode CG side. That is, the side surface 23 of the memory gate electrode MG is a substantially flat surface (a surface substantially perpendicular to the main surface of the semiconductor substrate 1) except for the lower portion 23a, whereas the lower portion 23a faces the control gate electrode CG side. It protrudes. Further, the lower portion 23a of the side surface 23 of the memory gate electrode MG protrudes toward the control gate electrode CG. This means that the lower end portion of the memory gate electrode MG on the control gate electrode CG side protrudes toward the control gate electrode CG. I mean. Further, the fact that the lower portion 23a of the side surface 23 of the memory gate electrode MG protrudes toward the control gate electrode CG indicates that the lower surface 26 of the memory gate electrode MG extends in the gate length direction (the gate length direction of the memory gate electrode MG). This means that the lower portion 23a of the side surface 23 of the memory gate electrode MG protrudes (that is, the lower end portion of the memory gate electrode MG on the control gate electrode CG side protrudes).

  Here, the side surface 23 of the memory gate electrode MG is a side surface adjacent to (opposed to) the control gate electrode CG through the insulating film 5. That is, the side surface 22 of the control gate electrode CG and the side surface 23 of the memory gate electrode MG are adjacent (opposed) via the insulating film 5. In the memory gate electrode MG, the sidewall spacer SW is formed on the side surface 24 opposite to the side surface 23, but the control gate electrode CG is formed on the side surface 23 of the memory gate electrode MG via the insulating film 5. Therefore, the sidewall spacer SW is not formed on the side surface 23 of the memory gate electrode MG. The side surface 23 of the memory gate electrode MG can be regarded as a side surface on the control gate electrode CG side, and the side surface 24 of the memory gate electrode MG can be regarded as a side surface on the semiconductor region MS side. The lower surface 26 of the memory gate electrode MG is a surface facing the semiconductor substrate 1 (p-type well PW1) with the insulating film 5 interposed therebetween. The lower end portion of the control gate electrode CG on the memory gate electrode MG side corresponds to the lower end portion (corner portion) sandwiched between the lower portion 22a of the side surface 22 of the control gate electrode CG and the lower surface 25 of the control gate electrode CG. Yes. The lower end portion of the memory gate electrode MG on the control gate electrode CG side corresponds to the lower end portion (corner portion) sandwiched between the lower portion 23a of the side surface 23 of the memory gate electrode MG and the lower surface 26 of the memory gate electrode MG. Yes.

  It is related that the lower part 22a of the side surface 22 of the control gate electrode CG recedes to the semiconductor region MD side and the lower part 23a of the side surface 23 of the memory gate electrode MG protrudes to the control gate electrode CG side. . That is, since the lower part 22a of the side surface 22 of the control gate electrode CG has retreated to the semiconductor region MD side, the lower part 23a of the side surface 23 of the memory gate electrode MG can be protruded to the control gate electrode CG side.

  Unlike the present embodiment, when the lower portion 23a of the side surface 23 of the memory gate electrode MG protrudes to the control gate electrode CG side without causing the lower portion 22a of the side surface 22 of the control gate electrode CG to recede to the semiconductor region MD side. Since the lower portion 23a of the side surface 23 of the memory gate electrode MG is close to the control gate electrode CG, the withstand voltage between the memory gate electrode MG and the control gate electrode CG is lowered.

  On the other hand, unlike the present embodiment, the lower portion 22a of the side surface 22 of the control gate electrode CG is retracted to the semiconductor region MD side, but the lower portion 23a of the side surface 23 of the memory gate electrode MG protrudes to the control gate electrode CG side. There is a case where it is not allowed. However, in this case, in the p-type well PW1, an electric field is generated by the memory gate electrode MG and the control gate electrode CG below the insulating film 5 interposed between the memory gate electrode MG and the control gate electrode CG. A region that is difficult to be applied and that is difficult to form a channel region is likely to be generated. This causes a decrease in read current (current value flowing between the source and drain during read operation) of the memory cell of the nonvolatile memory, or a decrease in write speed.

  On the other hand, in the present embodiment, the lower portion 22a of the side surface 22 of the control gate electrode CG is retreated to the semiconductor region MD side, and the lower portion 23a of the side surface 23 of the memory gate electrode MG is protruded to the control gate electrode CG side. Therefore, a breakdown voltage between the memory gate electrode MG and the control gate electrode CG can be secured, and a decrease in read current and a decrease in write speed of the memory cell of the nonvolatile memory can be prevented.

  In this embodiment, the gate length of the control gate electrode CG is reduced by retracting the lower portion 22a of the side surface 22 of the control gate electrode CG to the semiconductor region MD side. However, the side surface of the memory gate electrode MG is correspondingly reduced. By projecting the lower portion 23a of the memory 23 toward the control gate electrode CG, the gate length (effective gate length) of the memory gate electrode MG can be increased.

  Therefore, for the memory gate electrode MG, the gate length of the memory gate electrode MG can be increased as much as the lower portion 23a of the side surface 23 of the memory gate electrode MG protrudes toward the control gate electrode CG. On the other hand, the gate length (effective gate length) of the control gate electrode CG can be increased by protruding the lower portion 21a of the side surface 21 of the control gate electrode CG toward the semiconductor region MD as described above. It is. Therefore, as for the control gate electrode CG, even if the gate length of the control gate electrode CG is reduced by the amount that the lower part 22a of the side surface 22 of the control gate electrode CG is retracted to the semiconductor region MD side, the side surface of the control gate electrode CG The gate length (effective gate length) of the control gate electrode CG can be increased by the amount that the lower portion 21a of the protrusion 21 protrudes toward the semiconductor region MD.

  Therefore, in the present embodiment, the lower portion 21a of the side surface 21 of the control gate electrode CG is protruded, the lower portion 22a of the side surface 22 of the control gate electrode CG is retracted, and the lower portion 23a of the side surface 23 of the memory gate electrode MG is protruded. Thus, the total value of the gate length of the control gate electrode CG and the gate length of the memory gate electrode MG can be obtained without increasing the dimension of the memory cell (the dimension in the direction parallel to the gate length of the control gate electrode CG). Can be bigger. Therefore, the total value of the gate length of the control gate electrode CG and the gate length of the memory gate electrode MG is increased while downsizing (smaller area) and higher performance (increasing memory capacity) of the semiconductor device. be able to. In the present embodiment, the lower portion 21a of the side surface 21 of the control gate electrode CG is protruded, the lower portion 22a of the side surface 22 of the control gate electrode CG is retracted, and the lower portion 23a of the side surface 23 of the memory gate electrode MG is protruded. Thus, the total value of the gate length of the control gate electrode CG and the gate length of the memory gate electrode MG can be increased without reducing the distance L1 between the control gate electrode CG and the plug PG. Therefore, the total value of the gate length of the control gate electrode CG and the gate length of the memory gate electrode MG can be increased while improving the manufacturing yield and reliability of the semiconductor device.

  If the gate length of the control gate electrode CG is small, the short channel effect is likely to occur. However, the short channel effect can be suppressed or prevented by increasing the gate length of the control gate electrode CG. For this reason, by increasing the gate length of the control gate electrode CG, the performance (electrical performance) of the semiconductor device having a nonvolatile memory can be improved.

  Further, by increasing the gate length of the memory gate electrode MG, the gate length direction (the gate of the memory gate electrode MG) of the charge storage portion (here, the silicon nitride film 6b of the insulating film 5) located under the memory gate electrode MG. Since the dimension in the long direction is also increased, the amount of holes that can be stored in the charge storage portion (here, the silicon nitride film 6b of the insulating film 5) can be increased. If the amount of holes stored in the charge storage portion (here, the silicon nitride film 6b of the insulating film 5) is large at the time of erasing, even if the holes disappear after the erasing, the erased state (the state where holes are accumulated) is maintained ( Maintenance). Therefore, by increasing the gate length of the memory gate electrode MG, it is possible to improve the retention characteristic of the stored information (particularly the retention characteristic in the erased state), and the performance (electrical performance) of the semiconductor device having a nonvolatile memory. Can be improved.

  In the present embodiment, as described above, the lower portion 21a of the side surface 21 of the control gate electrode CG protrudes, the lower portion 22a of the side surface 22 of the control gate electrode CG retracts, and the lower portion 23a of the side surface 23 of the memory gate electrode MG extends. By projecting, the total value of the gate length of the control gate electrode CG and the gate length of the memory gate electrode MG can be increased. Then, the protrusion amount of the lower portion 21a of the side surface 21 of the control gate electrode CG, the retraction amount of the lower portion 22a of the side surface 22 of the control gate electrode CG, and the protrusion amount of the lower portion 23a of the side surface 23 of the memory gate electrode MG are controlled. The amount of increase in the total value of the gate length of the control gate electrode CG and the gate length of the memory gate electrode MG is adjusted to which of the gate length of the control gate electrode CG and the gate length of the memory gate electrode MG. can do. That is, the protrusion amount of the lower portion 21a of the side surface 21 of the control gate electrode CG is increased, and the retreat amount of the lower portion 22a of the side surface 22 of the control gate electrode CG is decreased (accordingly, the protrusion of the lower portion 23a of the side surface 23 of the memory gate electrode MG). When the amount is also reduced), the increase amount of the total value of the gate length of the control gate electrode CG and the gate length of the memory gate electrode MG is mainly distributed to the increase of the gate length of the control gate electrode CG. . On the other hand, when the protrusion amount of the lower portion 23a of the side surface 23 of the memory gate electrode MG is increased (with this increase, the retraction amount of the lower portion 22a of the side surface 22 of the control gate electrode CG also increases), the gate length of the control gate electrode CG and the memory The increase amount of the total gate length of the gate electrode MG is distributed mainly to the increase of the gate length of the memory gate electrode MG. Of course, the increase amount of the total value of the gate length of the control gate electrode CG and the gate length of the memory gate electrode MG is distributed to both the increase of the gate length of the control gate electrode CG and the increase of the gate length of the memory gate electrode MG. As described above, the protrusion amount of the lower portion 21a of the side surface 21 of the control gate electrode CG, the retraction amount of the lower portion 22a of the side surface 22 of the control gate electrode CG, and the protrusion amount of the lower portion 23a of the side surface 23 of the memory gate electrode MG are controlled. You can also. The protruding amount of the lower portion 21a of the side surface 21 of the control gate electrode CG corresponds to the distance L2, and the protruding amount of the lower portion 23a of the side surface 23 of the memory gate electrode MG corresponds to a distance L3 described later. .

  As described above, in the present embodiment, the total value of the gate length of the control gate electrode CG and the gate length of the memory gate electrode MG is increased, and the amount of increase is increased by the gate length of the control gate electrode CG and the memory gate electrode. It can be distributed to one or both of the MG gate lengths. For this reason, since one or both of the gate length of the control gate electrode CG and the gate length of the memory gate electrode MG can be increased, the performance of the semiconductor device can be improved.

  In the present embodiment, the lower portion 23a of the side surface 23 of the memory gate electrode MG protrudes toward the control gate electrode CG, so that the gate length of the memory gate electrode can be increased. The distance L3 at which the lower portion 23a of the side surface 23 protrudes toward the control gate electrode CG is more than half of the thickness T1 of the insulating film 5 interposed between the control gate electrode CG and the memory gate electrode MG (that is, L3 ≧ T1 × 0). .5) is preferred. Here, the distance L3 at which the lower portion 23a of the side surface 23 of the memory gate electrode MG protrudes toward the control gate electrode CG is a side surface of the side surface 23 of the memory gate electrode MG with reference to a substantially flat surface other than the lower portion 23a. This corresponds to the distance at which the lower portion 23a of 23 (the lower end portion of the control gate electrode CG on the memory gate electrode MG side) protrudes toward the control gate electrode CG, and is shown in FIG. The thickness T1 of the insulating film 5 is also shown in FIG. The distance L3 at which the lower portion 23a of the side surface 23 of the memory gate electrode MG protrudes toward the control gate electrode CG is set to be more than half of the thickness T1 of the insulating film 5 (that is, L3 ≧ T1 × 0.5). The gate length of the electrode MG can be accurately increased, and the effects (such as improvement in retention characteristics of stored information) obtained by increasing the gate length of the memory gate electrode MG can be accurately obtained.

  In the present embodiment, the lower portion 21a of the side surface 21 of the control gate electrode CG is projected, the lower portion 22a of the side surface 22 of the control gate electrode CG is retracted, and the lower portion 23a of the side surface 23 of the memory gate electrode MG is projected. An example of a method for forming the control gate electrode CG and the memory gate electrode MG will be described in more detail.

  30 to 37 are explanatory views of a process of patterning the silicon film 4 by etching. The process of patterning the silicon film 4 described here by etching corresponds to the step S6 (silicon film pattern SP1 formation process) and the step S11 (control gate electrode CG formation process).

  FIG. 30 corresponds to a state before patterning (etching) of the silicon film 4 is started. A photoresist pattern corresponding to the photoresist pattern PR1 or the photoresist pattern PR2 is formed on the silicon film 4, but the illustration of the photoresist pattern is omitted here. When anisotropic dry etching of the silicon film 4 is started, as shown in FIG. 31, the silicon film 4 is formed on the side surface (side wall of the etching region) 31 of the silicon film 4 formed by anisotropic dry etching. Etching of the silicon film 4 proceeds while deposits (deposit layers) 32 resulting from this etching are deposited. In the stage of FIG. 31, the bottom surface 33 of the etching region is still in the middle of the thickness direction of the silicon film 4 and has not reached the insulating film 3. Since the lower part 31a of the side surface 31 is not covered with the deposit 32, it has a tapered shape.

  When anisotropic dry etching of the silicon film 4 further proceeds, as shown in FIG. 32, the bottom surface 33 of the etching region reaches the insulating film 3 and the insulating film 3 is exposed. FIG. 32 shows a stage where the bottom surface 33 of the etching region has just reached the insulating film 3. 32, the lower portion 31a of the side surface 31 is not covered with the deposit 32, and thus has a tapered shape.

  When the state shown in FIG. 32 is obtained and further overetching by anisotropic dry etching is performed, the tapered shape of the lower portion of the side surface 31 of the silicon film 4 is eliminated, and as shown in FIG. 33, the silicon film 4 The side surface 31 of this is a substantially flat surface including the lower part. Thereafter, the structure shown in FIG. 34 is obtained through the removal of the deposit 32 and the removal process of the insulating film 3 in a portion not covered with the silicon film 4, and the side surface 31 of the silicon film 4 is substantially flat including the lower part. (Therefore, the lower portion 31a of the side surface 31 is not tapered).

  However, in this embodiment, it is necessary to project the lower portion 21a of the side surface 21 of the control gate electrode CG. Therefore, in step S11 (control gate electrode CG formation step), the silicon film 4 is patterned (etched) as follows. In step S11 (control gate electrode CG formation step), the silicon film pattern SP1 corresponds to the silicon film 4 described here.

  That is, after the structure shown in FIG. 32 is obtained by anisotropic dry etching as described above, the dry etching is finished with almost no over-etching. Thereafter, the structure shown in FIG. 35 is obtained through the removal process of the deposit 32 and the removal process of the insulating film 3 in a portion not covered with the silicon film 4. The dry etching is finished when the bottom surface 33 of the etching region reaches the insulating film 3 (the insulating film 3 is exposed) and the lower portion 31a of the side surface 31 of the silicon film 4 is tapered (over-etching). 35), as shown in FIG. 35, the side surface 31 of the silicon film 4 is in a state where the lower portion 31a is tapered (projected state). The side surface 31 (side surface 31 from which the lower portion 31a protrudes) of the silicon film 4 becomes the side surface 21 of the control gate electrode CG, and the lower portion 31a of the side surface 31 of the silicon film 4 becomes the lower portion 21a of the side surface 21 of the control gate electrode CG. . In this manner, a structure in which the lower portion 21a of the side surface 21 of the control gate electrode CG protrudes toward the semiconductor region MD can be obtained. The distance L2 at which the lower portion 21a of the side surface 21 of the control gate electrode CG protrudes toward the semiconductor region MD can be controlled by adjusting the etching conditions in step S11 (control gate electrode CG forming step).

  In the present embodiment, it is necessary to recede the lower part 22a of the side surface 22 of the control gate electrode CG. Therefore, in step S6 (silicon film pattern SP1 formation step), the silicon film 4 is patterned (etched) as follows.

  That is, after the structure shown in FIG. 32 is obtained by anisotropic dry etching as described above, isotropic dry etching is performed without performing overetching by anisotropic dry etching (that is, When the structure of FIG. 32 is obtained, the anisotropic dry etching is switched to isotropic dry etching). Thereby, in the side surface 31 of the silicon film 4, the region where the deposit 32 is deposited (that is, the region other than the lower portion 31 a) is covered with the deposit 32, so that isotropic etching does not proceed. Among the side surfaces 31 of 4, the region where the deposit 32 is not deposited (that is, the lower portion 31a) undergoes isotropic etching (that is, side etching proceeds). Therefore, as shown in FIG. 36, the lower portion 31a of the side surface 31 of the silicon film 4 is in a state of retreating with respect to the region other than the lower portion 31a. Thereafter, the structure shown in FIG. 37 is obtained through the removal process of the deposit 32 and the removal process of the insulating film 3 which is not covered with the silicon film 4. As a result, as shown in FIG. 37, the side surface 31 of the silicon film 4 is in a state in which the lower portion 31a is retracted. The side surface 31 of the silicon film 4 (the side surface 31 with the lower portion 31a receding) becomes the side surface SP1a of the silicon film pattern SP1, that is, the side surface 22 of the control gate electrode CG, and the lower portion 31a of the side surface 31 of the silicon film 4 is the control gate electrode. It becomes the lower part 22a of the side surface 22 of CG. In this way, it is possible to obtain a structure in which the lower portion 22a of the side surface 22 of the control gate electrode CG is retreated to the semiconductor region MD side. The distance L4 that the lower part 22a of the side surface 22 of the control gate electrode CG recedes to the semiconductor region MD side can be controlled by adjusting the etching conditions in the above step S6 (silicon film pattern SP1 formation step).

  In step S7 (insulating film 5 forming step), the insulating film 5 is formed conformally to the shape of the side surface SP1a of the silicon film SP1, and in step S8 (silicon film 7 forming step). The silicon film 7 can be formed conformally with respect to the surface of the insulating film 5. Therefore, in step S6 (silicon film pattern SP1 formation step), a structure in which the lower portion 31a of the side surface 31 of the silicon film 4 (corresponding to the side surface SP1a of the silicon film pattern SP1 here) is retreated as described above can be obtained. For example, by performing the above steps S7, S8, and S9, it is possible to obtain a structure in which the lower portion 23a of the side surface 23 of the memory gate electrode MG protrudes toward the control gate electrode CG.

  Further, in the present embodiment, as described above, the lower portion 23a of the side surface 23 of the memory gate electrode MG protrudes toward the control gate electrode CG, so that the gate of the memory gate electrode MG is compared with the case where it does not protrude. The length can be increased. For this reason, when the memory gate length of the memory gate electrode MG is the same, the lower portion 23a of the side surface 23 of the memory gate electrode MG protrudes to the control gate electrode CG side (corresponding to the present embodiment). Compared with the case where there is not, the thickness of the silicon film 7 for forming the memory gate electrode MG can be reduced in the case where it protrudes (corresponding to the present embodiment). In the present embodiment, since the thickness of the silicon film 7 for forming the memory gate electrode MG can be reduced, an advantage described below with reference to FIG. 38 can be obtained.

  FIG. 38 is a main-portion cross-sectional view of the semiconductor device of the present embodiment, and shows a state where the plug PG is connected to the contact portion MGa of the memory gate electrode MG.

  The control gate electrode CG in the region (memory cell region) shown in FIG. 1 functions as a gate electrode of a control transistor (selection transistor) constituting the memory cell MC. On the other hand, the control gate electrode CG in the region (word shunt region) shown in FIG. 38 is located on the element isolation region 2 and does not function as the gate electrode of the control transistor of the memory cell MC. It functions as a control gate line (selection gate line) that electrically connects control gate electrodes of a plurality of memory cells MC arranged in a direction perpendicular to the paper surface. The control gate electrode CG in the region (memory cell region) shown in FIG. 1 and the control gate electrode CG in the region (word shunt region) shown in FIG. 38 extend in a direction perpendicular to the plane of FIG. 1 and FIG. Existing and connected (ie, formed integrally).

  Further, as shown in FIG. 1, the memory gate electrode MG is formed on one side surface (side wall) of the control gate electrode CG via the insulating film 5 and extends on the semiconductor substrate 1 together with the control gate electrode CG. (The extending direction is a direction perpendicular to the paper surface of FIG. 1), but in the region (word shunt region) shown in FIG. 38, the contact hole MG and the contact portion MGa for connecting the plug PG filling it are provided. Have. A portion of the memory gate electrode MG other than the contact portion MGa is formed in a side wall spacer shape via an insulating film 5 on one side surface (side wall) of the control gate electrode CG as shown in FIG. The portion formed in a sidewall shape and the contact portion MGa are integrally formed. Therefore, the contact portion MGa can be regarded as a part of the memory gate electrode MG, but is a portion that does not function as the gate electrode of the memory transistor of the memory cell MC of the nonvolatile memory. Therefore, the contact portion MGa of the memory gate electrode MG is preferably provided in a region (here, a word shunt region) other than the memory cell region in which a plurality of memory cells MC are arranged in an array, and is disposed on the element isolation region 2. It is preferable to do.

  As shown in FIG. 38, the contact portion MGa extends from the control gate electrode CG to the element isolation region 2, and between the contact portion MGa and the control gate electrode CG and between the contact portion MGa and the element isolation region. Insulating film 5 is interposed between the two. A contact hole CNT and a plug PG that embeds the contact hole CNT are formed on a part of the contact portion MG located on the element isolation region 2, and the plug PG is connected to the contact portion MG, and is formed above the plug PG. Is connected to the wiring M1. Therefore, the contact portion MGa is electrically connected to the wiring M1 on the plug PG via the plug PG on the contact portion MGa. A metal silicide layer 12 is formed on the surface layer portion (but not covered with the sidewall spacer SW) of the contact portion MGa, and the bottom surface of the plug PG is the metal formed on the surface layer portion of the contact portion MGa. It is in contact with the silicide layer 12.

  When a part of the contact portion MGa of the memory gate electrode MG rides on the control gate electrode CG as shown in FIG. 38, the contact portion MGa running on the control gate electrode CG is also sufficiently covered by the insulating film 13. In order to be covered, it is necessary to increase the thickness of the insulating film 13 (the distance from the main surface of the semiconductor substrate 1 to the upper surface of the insulating film 13).

  However, the contact hole CNT formed in the insulating film 13 needs to be formed so as to surely penetrate the insulating film 13. For this reason, when the insulating film 13 is thick, the amount of dry etching when forming the contact hole CNT in the insulating film 13 increases accordingly, and a photoresist pattern (not shown) for forming the contact hole CNT increases. There is a possibility that the amount of shaving increases and the shape of the contact hole CNT is abnormal, resulting in a decrease in yield. In addition, it is necessary to set a large amount of over-etching when forming the contact hole CNT, which may cause damage due to over-etching on a portion exposed at the bottom of the contact hole CNT.

  Further, when the insulating film 13 is thick, the depth of the contact hole CNT formed in the insulating film 13 becomes deep. However, contact holes are difficult to form if the aspect ratio (aspect ratio) is too large. For this reason, when the thickness of the insulating film 13 is increased, it is necessary to increase the planar dimension (opening area) of the contact hole CNT in order to suppress an increase in the aspect ratio of the contact hole CNT. This is disadvantageous for downsizing.

  In contrast, in the present embodiment, as described above, when the memory gate length of the memory gate electrode MG is the same, the lower portion 23a of the side surface 23 of the memory gate electrode MG protrudes toward the control gate electrode CG. When the case (corresponding to this embodiment) is compared with the case where it does not protrude, the thickness of the silicon film 7 for forming the memory gate electrode MG is larger in the case of protrusion (corresponding to this embodiment). Can be thinned. Since the thickness of the silicon film 7 for forming the memory gate electrode MG can be reduced, the height of the contact portion MGa on the control gate electrode CG can be reduced. The thickness (distance from the main surface of the semiconductor substrate 1 to the upper surface of the insulating film 13) can be reduced.

  For this reason, in this embodiment, since the insulating film 13 can be made thin, it is possible to set the etching amount and the over-etching amount of dry etching when forming the contact hole CNT small, and the etching amount is large. It is possible to suppress or prevent the occurrence of contact hole CNT shape abnormality and the occurrence of damage due to overetching. Therefore, the reliability of the semiconductor device can be improved and the performance of the semiconductor device can be improved.

  In the present embodiment, since the insulating film 13 can be made thin, the aspect ratio (aspect ratio) of the contact hole CNT can be reduced if the planar dimension (opening area) of the contact hole CNT is the same. If the aspect ratio of the contact hole CNT is the same, the planar dimension (opening area) of the contact hole CNT can be reduced. For this reason, the contact hole CNT can be easily formed, and the planar dimension (opening area) of the contact hole can be reduced. Therefore, the manufacturing yield of the semiconductor device can be improved, and the semiconductor device can be reduced in size (reduced area). In addition, the miniaturization (small area) of the semiconductor device can be promoted.

  Further, in the present embodiment, since the lower portion 21a of the side surface 21 of the control gate electrode CG protrudes toward the semiconductor region SD as described above, the following advantages related to the halo region HA can also be obtained. .

In step S13, ion implantation for forming the n ⁻ -type semiconductor region EX2 is performed, and in step S14, ion implantation for forming the halo region HA is performed. During these ion implantations, the control gate electrode CG is formed on the semiconductor substrate 1. It can function as an ion implantation blocking mask. However, the implantation energy (ion acceleration energy) of the ion implantation for forming the halo region HA is larger than the implantation energy (ion acceleration energy) of the ion implantation for forming the n ⁻ type semiconductor region EX2. Therefore, at the time of ion implantation for forming the halo region HA, the impurity ions can penetrate the portion where the lower portion 23a of the side surface 23 of the memory gate electrode MG protrudes, while the n ⁻ type semiconductor region EX2 is formed. At the time of ion implantation, impurity ions hardly penetrate through the portion where the lower portion 23a of the side surface 23 of the memory gate electrode MG protrudes. For this reason, during ion implantation for forming the halo region HA, even if the lower portion 23a of the side surface 23 of the memory gate electrode MG protrudes, it is not affected by this and is sufficiently deep (when viewed in the gate length direction). Impurity ions can be implanted up to the back side. On the other hand, when ion implantation for forming the n ⁻ type semiconductor region EX2 is performed, the lower side 23a of the side surface 23 of the memory gate electrode MG is projected, and the front side (front side when viewed in the gate length direction). Impurity ions are implanted only up to. Therefore, comparing the case where the lower portion 21a of the side surface 21 of the control gate electrode CG protrudes toward the semiconductor region SD (corresponding to the present embodiment) and the case where it does not protrude (corresponding to the present embodiment). (Corresponding) can increase the distance L5 from the end of the n ⁻ type semiconductor region EX2 to the end of the halo region HA.

Here, n ^- -type distance L5 from end to end of the halo region HA semiconductor region EX2 is when viewed in the gate length direction of the control gate electrode, n ^- end type semiconductor region EX2 (i.e. n ^- 2 corresponds to the distance from the boundary of the type semiconductor region EX2 and the halo region HA) to the end of the halo region HA, and is schematically shown in FIG.

The halo region HA is formed to suppress short channel characteristics (punch through). However, if the distance L5 from the end of the n ⁻ type semiconductor region EX2 to the end of the halo region HA is increased, the depletion layer expands. Therefore, the short channel characteristic (punch through) suppression effect can be enhanced. Therefore, in the present embodiment, the lower portion 21a of the side surface 21 of the control gate electrode CG protrudes toward the semiconductor region SD, so that the distance from the end portion of the n ⁻ type semiconductor region EX2 to the end portion of the halo region HA. L5 can be increased, and the short channel characteristic (punch through) suppression effect by the halo region HA can be enhanced.

  FIG. 39 is an explanatory diagram of the semiconductor device of the present embodiment. The memory cell MC (lower side of FIG. 39) of the semiconductor device of the present embodiment and the memory cell MC101 of the comparative example (upper side of FIG. 39) are shown. These are shown side by side in FIG. The control gate electrode CG101 and the memory gate electrode MG101 constituting the memory cell MC101 of the comparative example correspond to the control gate electrode CG and the memory gate electrode MG of the present embodiment, respectively, but are different from the present embodiment. The entire side surfaces (side surfaces corresponding to the side surfaces 21, 22, and 23) of the control gate electrode CG101 and the memory gate electrode MG101, including the lower portions thereof, are perpendicular to the main surface of the semiconductor substrate. In the memory cell MC101 of the comparative example, the insulating film 103 is a gate insulating film (corresponding to the insulating film 3 in this embodiment) of the control transistor, and the silicon oxide film 106a, the silicon nitride film 106b, and the silicon oxide film 106c. Is a gate insulating film of the memory transistor (corresponding to the insulating film 5 in this embodiment). Further, the sidewall spacer SW101 corresponds to the sidewall spacer SW of the present embodiment.

  As can be seen by comparing the memory cell MC of the present embodiment of FIG. 39 (lower side of FIG. 39) with the memory cell MC101 of the comparative example (upper side of FIG. 39), the effective memory gate length L8 is the memory cell MC. And the memory cell MC101, the thickness L7 of the silicon film constituting the memory gate electrode MG can be made smaller (thinner) than the thickness L6 of the silicon film constituting the memory gate electrode MG101. For this reason, the dimension of the memory cell MC (dimension in the gate length direction) can be made smaller than the dimension of the memory cell MC101 (dimension in the gate length direction) by the distance L9 (shown in FIG. 39). it can. Therefore, in the present embodiment, the effective memory gate length (effective gate length of the memory gate electrode) L8 can be secured while reducing the cell size (dimension in the gate length direction) of the memory cell MC. . In other words, in the present embodiment, the cell size (dimension in the gate length direction) of the memory cell MC can be reduced while ensuring the effective memory gate length L8.

(Embodiment 2)
40 and 41 are fragmentary cross-sectional views of the semiconductor device of the present embodiment during the manufacturing process.

  In the said Embodiment 1, step S11 (control gate electrode CG formation process) and step S12 (gate electrode GE formation process) were performed by the separate process (separate etching process). In contrast, in the present embodiment, step S11 (control gate electrode CG forming step) and step S12 (gate electrode GE forming step) are performed in the same step (same etching step).

  That is, after carrying out the steps up to step S10 to obtain the structure of FIG. 16, in this embodiment, as shown in FIG. 40, a photolithographic method is used on the main surface of the semiconductor substrate 1 to perform photolithography. A resist pattern PR2a is formed. The pattern shape of the photoresist pattern PR2a in the memory cell region 1A is the same as the pattern shape of the photoresist pattern PR2 in the memory cell region 1A. The pattern shape of the photoresist pattern PR2a in the peripheral circuit region 1B is the same as that of the photoresist pattern. This is the same as the pattern shape in the peripheral circuit region 1B of the pattern PR3.

  That is, in the memory cell region 1A, the photoresist pattern PR2a covers the memory gate electrode MG and the silicon film pattern SP1 that is to be the control gate electrode CG adjacent thereto (adjacent via the insulating film 5). The portion of the silicon film pattern SP1 that does not become the control gate electrode CG is exposed. That is, in the memory cell region 1A, the photoresist pattern PR2a covers the memory gate electrode MG and the region where the control gate electrode CG is to be formed adjacent thereto, and exposes the silicon film pattern SP1 that does not become the control gate electrode CG. To be formed. On the other hand, in the peripheral circuit region 1B, the photoresist pattern PR2a is formed in the region where the gate electrode GE is to be formed (the portion of the silicon film 4 that does not become the control gate electrode CG is exposed).

  Then, by using the photoresist pattern PR2a as an etching mask, the silicon film pattern SP1 in the memory cell region 1A and the silicon film 4 (that is, the silicon film pattern SP2) in the peripheral circuit region 1B are etched and patterned, so that FIG. As shown, the control gate electrode CG is formed in the memory cell region 1A, and the gate electrode GE is formed in the peripheral circuit region 1B. Thereafter, the photoresist pattern PR2a is removed. FIG. 41 shows a stage where the photoresist pattern PR2a is removed.

  Since the control gate electrode CG formed in the present embodiment is the same as that in the first embodiment, the description thereof is omitted here. On the other hand, the gate electrode GE formed in the present embodiment is that the lower portion 41a of the side surface 41 of the gate electrode GE protrudes to the outside (on the side of the semiconductor region SD to be formed later). It is different from the gate electrode GE.

  The subsequent steps are the same as those in the first embodiment, and the steps S13, S14, S15, S16 and the subsequent steps are performed.

  In the present embodiment, by performing step S11 (control gate electrode CG forming step) and step S12 (gate electrode GE forming step) in the same step, the number of manufacturing steps of the semiconductor device can be reduced. On the other hand, in the first embodiment, in the first embodiment, the step S11 (control gate electrode CG forming step) and the step S12 (gate electrode GE forming step) are performed in separate steps. The shape of the side surface 21 of the CG and the shape of the side surface 41 of the gate electrode GE can be controlled independently. For this reason, the freedom degree of design of a semiconductor device can be raised.

(Embodiment 3)
This embodiment corresponds to a modification of the first embodiment.

  In the present embodiment, a case will be described in which the control gate electrode CG of the nonvolatile memory of the first embodiment is formed of a laminated film of a silicon film 4 and an insulating film.

  42 is a main-portion cross-sectional view of the semiconductor device of the present embodiment, and corresponds to FIG. 1 of the first embodiment.

  As shown in FIG. 42, in the memory cell of the nonvolatile memory according to the present embodiment, the control gate electrode CG is constituted by a laminated film (laminated pattern, laminated structure) of the silicon film 4 and the insulating film 51. More specifically, the control gate electrode CG is composed of a laminated film (laminated film pattern) of the silicon film 4, the insulating film 51a on the silicon film 4, and the insulating film 51b on the insulating film 51a. The insulating film 51 includes an insulating film 51a on the silicon film 4 and an insulating film 51b on the insulating film 51a. The insulating film 51a is formed thinner than the insulating film 51b. The insulating film 51a is preferably made of a silicon oxide film, and the insulating film 51b is preferably made of a silicon nitride film.

  In the present embodiment, since the insulating film 51 (in this case, the insulating films 51a and 51b) is formed on the control gate electrode CG of the memory cell, the metal silicide layer is formed on the control gate electrode CG of the memory cell. No 12 is formed. That is, the control gate electrode CG formed by the silicon film 4 and the metal silicide layer 12 thereabove in the first embodiment is changed to the control gate electrode CG formed by the laminated film of the silicon film 4 and the insulating film 51. The replaced one corresponds to the semiconductor device of this embodiment.

  Since the other configuration of the memory cell of this embodiment is the same as that of Embodiment 1, the description thereof is omitted here.

  Next, the manufacturing process of the semiconductor device of this embodiment will be described. 43 to 45 are principal part cross-sectional views during the manufacturing process of the semiconductor device of the present embodiment, showing substantially the same cross-sectional area as in FIGS. 6 to 11 in the first embodiment.

  Since the manufacturing process of the semiconductor device according to the present embodiment is basically the same as the manufacturing process of the semiconductor device according to the first embodiment, differences from the manufacturing process according to the first embodiment will be mainly described below. explain.

  After obtaining the structure shown in FIG. 8 in the same manner as in the first embodiment, in this embodiment, between the step S5 and the step S6, as shown in FIG. A step of forming the insulating film 51 is added. The insulating film 51 forming step includes a step of forming the insulating film 51a on the silicon film 4 and a step of forming the insulating film 51b on the insulating film 51a. In FIG. 43, the drawing is simplified. Therefore, the laminated film of the insulating film 51a and the insulating film 51b is illustrated as the insulating film 51 only.

  In step S6, the silicon film 4 is patterned to form the silicon film pattern SP1 in the first embodiment, but in this embodiment, the stacked film of the silicon film 4 and the insulating film 51 is patterned. Thus, as shown in FIG. 44, a laminated film pattern SP1 composed of a laminated film pattern of the silicon film 4 and the insulating film 51 is formed. Then, between step S6 and step S7, as shown in FIG. 45, in the region where the insulating film 51 is to be removed (for example, the peripheral circuit region 1B), the insulating film 51 is appropriately removed. Subsequent processes (step S7 and subsequent processes) are basically the same as those in the first embodiment, and thus the description thereof is omitted here. In step S11, the control gate electrode CG is formed by patterning the stacked film pattern SP1 including the stacked film pattern of the silicon film 4 and the insulating film 51.

  Also in the present embodiment, the same effect as in the first embodiment can be obtained.

  In addition, in this embodiment, since the control gate electrode CG is formed of a laminated film of the silicon film 4 and the insulating film 51 (more specifically, the insulating films 51a and 51b), the silicon film 4 is formed as described above. Even when the gate electrode is formed thinner than the first embodiment, the height of the memory gate electrode MG formed in a side wall spacer shape on the side surface (side wall) of the control gate electrode CG can be secured.

  In the present embodiment, the manufacturing process of the second embodiment may be applied.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The present invention is effective when applied to a semiconductor device and its manufacturing technology.

1 Semiconductor substrate 1A Memory cell region 1B Peripheral circuit region 2 Element isolation region 3 Insulating film 4 Silicon film 5 Insulating film 6a, 6c Silicon oxide film 6b Silicon nitride film 7 Silicon film 8 Silicon spacer 9 Insulating films 10a, 10b, 10c n ⁺ Type semiconductor region 11 Metal film 12 Metal silicide layers 13, 14, 16 Insulating films 21, 22, 23, 24 Side surfaces 21a, 22a, 23a, 24a Lower portion 31 Side surface 31a Lower portion 32 Deposit 33 Bottom surface 41 Side surface 41a Lower portions 51, 51a 51b Insulating film CG Control gate electrode CNT Contact hole EX1, EX2, EX3 n ⁻ type semiconductor regions L1, L2, L3, L4 Distance M1 Wiring MC Memory cell MD, MS Semiconductor region MG Memory gate electrode PG Plug PW1, PW2 P type well SP1, SP2 Silicon film pattern SD semiconductor Pass SW sidewall spacer

Claims (12)

A semiconductor device including a memory cell of a nonvolatile memory,
A semiconductor substrate;
First and second semiconductor regions of a first conductivity type, which are formed in a semiconductor substrate and constitute the memory cell;
A first gate electrode constituting the memory cell, formed on the semiconductor substrate between the first semiconductor region and the second semiconductor region;
A second gate electrode formed on the semiconductor substrate between the first semiconductor region and the second semiconductor region, adjacent to the first gate electrode and constituting the memory cell;
A first gate insulating film formed between the first gate electrode and the semiconductor substrate;
An insulating film formed between the second gate electrode and the semiconductor substrate and between the first gate electrode and the second gate electrode, the insulating film having a charge storage portion therein;
Have
The first gate electrode is located on the first semiconductor region side;
The second gate electrode is located on the second semiconductor region side;
The first gate electrode has a lower portion of the first side surface on the first semiconductor region side protruding toward the first semiconductor region side, and a lower portion of the second side surface adjacent to the second gate electrode through the insulating film. Has receded to the first semiconductor region side,
2. The semiconductor device according to claim 1, wherein a lower portion of the third side surface of the second gate electrode adjacent to the first gate electrode through the insulating film protrudes toward the first gate electrode. The semiconductor device according to claim 1,
The semiconductor device is characterized in that the insulating film is a laminated film of a first silicon oxide film, a silicon nitride film, and a second silicon oxide film. The semiconductor device according to claim 2,
The semiconductor device according to claim 1, wherein the first and second semiconductor regions are source or drain semiconductor regions. The semiconductor device according to claim 3.
Sidewall spacers made of an insulator are formed on the first side surface of the first gate electrode,
The first semiconductor region includes a third semiconductor region formed below the sidewall spacer, and a fourth semiconductor region adjacent to the third semiconductor region and having a higher impurity concentration than the third semiconductor region. A semiconductor device including the semiconductor device. The semiconductor device according to claim 4.
A semiconductor device having a halo region formed in the semiconductor substrate and having a second conductivity type opposite to the first conductivity type and enclosing the third semiconductor region. The semiconductor device according to claim 5.
The distance by which the lower part of the third side surface of the second gate electrode protrudes toward the first gate electrode is at least half the thickness of the insulating film. A method of manufacturing a semiconductor device including a memory cell of a nonvolatile memory,
(A) preparing a semiconductor substrate;
(B) forming a first insulating film for a gate insulating film on the main surface of the semiconductor substrate;
(C) forming a first silicon film for a first gate electrode constituting the memory cell on the first insulating film;
(D) After the step (c), etching the first silicon film to form a first silicon film pattern;
(E) After the step (d), a step of forming a second insulating film having a charge storage portion therein on the main surface of the semiconductor substrate and the upper surface and side surfaces of the first silicon film pattern;
(F) After the step (e), forming a second silicon film for the second gate electrode constituting the memory cell on the second insulating film;
(G) After the step (f), the second silicon film is etched, and the second gate electrode that is adjacent to the first silicon film pattern via the second insulating film and constitutes the memory cell is formed. Forming step,
(H) removing the exposed portion of the second insulating film;
(I) After the step (h), etching the first silicon film pattern to form the first gate electrode adjacent to the second gate electrode through the second insulating film;
Have
The first gate electrode has a second side surface adjacent to the second gate electrode through the second insulating film, and a first side surface opposite to the second side surface,
The first silicon film pattern formed in the step (d) has a fourth side surface that later becomes the second side surface of the first gate electrode,
In the step (d), the first silicon film pattern is formed so that a lower part of the fourth side surface of the first silicon film pattern is retreated,
In the step (i), the first silicon film pattern is processed so that a lower portion of the first side surface of the first gate electrode protrudes. The method of manufacturing a semiconductor device according to claim 7.
The method of manufacturing a semiconductor device, wherein the second insulating film comprises a laminated film of a first silicon oxide film, a silicon nitride film, and a second silicon oxide film. The method of manufacturing a semiconductor device according to claim 8.
In the step (d), the first silicon film pattern is formed by performing anisotropic dry etching on the first silicon film and then isotropic dry etching on the first silicon film. A method for manufacturing a semiconductor device. In the manufacturing method of the semiconductor device according to claim 9,
(J) After the step (i), ion implantation is performed on the semiconductor substrate using the first gate electrode as a mask to form a semiconductor region functioning as a part of a source or drain region in the semiconductor substrate;
(K) After the step (i), ion implantation is performed on the semiconductor substrate using the first gate electrode as a mask to form a halo region having a conductivity type opposite to that of the semiconductor region and enclosing the semiconductor region. Process,
A method for manufacturing a semiconductor device, further comprising: The method of manufacturing a semiconductor device according to claim 10.
In the step (d), the first silicon film pattern and the second silicon film pattern are formed by etching the first silicon film,
(L) patterning the second silicon film pattern to form a third gate electrode of a MISFET constituting a circuit other than the nonvolatile memory;
A method for manufacturing a semiconductor device, further comprising: The method of manufacturing a semiconductor device according to claim 11.
The method of manufacturing a semiconductor device, wherein the step (i) and the step (l) are performed by the same etching step.

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