KR20080010600A - Nonvolatile Memory Devices - Google Patents

Abstract

The present invention provides a nonvolatile memory device. The device includes an isolation layer defining an active region, a sensing line crossing the upper portion of the active region and including a floating gate and a control gate electrode, and a word line spaced apart from the sensing line and crossing the upper portion of the active region. The active area under the word line includes a wider area than the active area under the sensing line.

Description

Nonvolatile Memory Devices {NON-VOLATILE MEMORY DEVICE}

1 is a plan view of a general ypyrom.

2 is a plan view of a Y pyrom according to an embodiment of the present invention.

3 is a cross-sectional view taken along the line II ′ of FIG. 1.

4 is a cross-sectional view taken along II-II 'of FIG.

5 is a plan view of a Y pyrom according to another embodiment of the present invention.

TECHNICAL FIELD The present invention relates to nonvolatile memory devices, and more particularly, to EPIROM.

The nonvolatile memory device is characterized in that stored data is not destroyed even when power supply is interrupted. The nonvolatile memory device may be classified into a mask ROM, an EPROM, an EEPROM, and the like. In particular, in the EEPROM, a FLOTOX (floating gate tunneling oxide) type memory device includes two transistors, a selection transistor for selecting a cell, and a memory transistor for storing data. Configure.

1 is a plan view of a general ypyrom.

Referring to FIG. 1, device isolation layers 2 defining an active region 3 are disposed on a semiconductor substrate 1 (hereinafter, referred to as a substrate). The active region 3 has a predetermined width and is arranged at a constant pitch. A gate insulating film (not shown) is formed on the active region 3 of the substrate 1. The source region 3s, the floating diffusion region 3f, and the drain region 3d are spaced apart from each other at predetermined intervals in the active region 3.

 A word line WL is disposed between the source region 3s and the floating diffusion region 3f to cross the upper portion of the active region 3 and between the floating diffusion region 3f and the drain region 3d. The sensing line SL is disposed in the upper surface of the active region 3.

The sensing line SL includes a floating gate 4s and a control gate electrode 5s. The floating gate 4s is disposed on the gate insulating film. The control gate electrode 24s is formed on the floating gate 22s to cross the active region 3. An inter-gate dielectric (not shown) is interposed between the floating gate 4s and the control gate electrode 5s.

The word line WL may be composed of a lower gate electrode 4w and an upper gate electrode 5w and may be electrically connected to any part of the substrate 1.

As the capacity of Ipyrom increases, the size of the unit memory cell is reduced. Accordingly, the width of the active area of the unit memory cell is reduced. That is, the width of the channel region of the memory transistor is reduced. As a result, the amount of turn-on current of the ypyrom memory cell may be drastically reduced. As a result, the sensing margin of the EPYROM memory cell may be reduced. In order to secure the sensing margin, the operating voltage of the EPYROM memory cell device may be increased. This increase in operating voltage increases the power consumption of the device, which degrades the performance of Y. pyrom.

An object of the present invention is to provide a nonvolatile memory device capable of increasing the amount of turn-on current.

Provided is a semiconductor device for achieving the above technical problem. The device includes an isolation film defining an active region; A sensing line crossing the top of the active region and including a floating gate and a control gate electrode; And a word line spaced apart from the sensing line and crossing the upper portion of the active region. When the distance between the device isolation layers is defined as the width of an active region, the active region under the word line includes a wider region than the active region under the sensing line.

In an embodiment of the present invention, the width of the active region below the word line may increase or decrease as the distance from the sensing line increases.

In another embodiment of the present invention, the active area below the word line includes a first area and a second area divided in parallel with the word line, and are close to the sensing line among the first area and the second area. The active area width of the area may be wide or the active area width of the area far from the sensing line may be wide.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein but may be embodied in other forms. Rather, the embodiments introduced herein are provided to ensure that the disclosed subject matter is thorough and complete, and that the spirit of the present invention to those skilled in the art will fully convey. In the drawings, the thicknesses of layers (or films) and regions are exaggerated for clarity. In addition, where it is said that a layer (or film) is "on" another layer (or film) or substrate, it may be formed directly on another layer (or film) or substrate or a third layer between them. (Or membrane) may be interposed. Portions denoted by like reference numerals denote like elements throughout the specification.

2 is a plan view of a Y pyrom according to an embodiment of the present invention. 3 is a cross-sectional view taken along the line II ′ of FIG. 2. 4 is a cross-sectional view taken along II-II 'of FIG.

 2 to 4, device isolation layers 12 defining active regions 26 are disposed on a semiconductor substrate 10 (hereinafter, referred to as a substrate). The gate insulating layer 14 is formed on the active region 26 of the substrate 10. The gate insulating layer 14 may be formed of a silicon oxide layer having excellent properties, for example, a thermal oxide layer. Source regions 26s, floating diffusion regions 26f, and drain regions 26d, which are spaced at predetermined intervals, are formed in the active region 26.

 A word line WL is disposed between the source region 26s and the floating diffusion region 26f to cross the upper portion of the active region 26, and the floating diffusion region 26f and the drain region 26d. The sensing line SL is disposed in between to cross the upper portion of the active region 26. The sensing line SL includes a floating gate 22s and a control gate electrode 24s.

 The floating gate 22s is disposed on the gate insulating layer 14. The floating gate 22s may be made of doped polysilicon. The control gate electrode 24s is formed on the floating gate 22s to cross the active region 26. The control gate electrode 24s may be formed of a conductive film. For example, it may be formed of a single film selected from doped polysilicon, metal silicide, conductive metal nitride, metal, or a combination thereof. Preferably, the control gate electrode 24s is a single film selected from doped polysilicon, tungsten silicide, cobalt silicide, nickel silicide, titanium silicide, titanium nitride, tantalum nitride, tungsten, molybdenum, or a combination thereof. It can be formed as.

 An inter-gate dielectric 16 is interposed between the floating gate 22s and the control gate electrode 24s. The inter-gate dielectric layer 16 may be formed of an oxide-nitride-oxide (ONO) layer. In contrast, the inter-gate dielectric layer 16 may include a high dielectric layer having a higher dielectric constant than the ONO layer. For example, a metal oxide film such as an aluminum oxide film or a hafnium oxide film may be included.

The word line WL consists of a lower gate electrode 22w and an upper gate electrode 24w and is electrically connected to any part of the substrate 10. The lower gate electrode 22w and the upper gate electrode 24w may be formed of a conductive film. For example, it may be formed of one single film selected from doped polysilicon, metal silicide, conductive metal nitride, metal, or a combination thereof. Preferably, the lower gate electrode 22w and the upper gate electrode 24w are one selected from doped polysilicon, tungsten silicide, cobalt silicide, nickel silicide, titanium silicide, titanium nitride, tantalum nitride, tungsten, and molybdenum. It may be formed of a single film or a combination thereof.

The active region 26 between the device isolation layers 12 under the word line WL is disposed in a structure that gradually widens from the width W1 to the width W2 as shown. That is, as the active region 26 below the word line WL becomes farther from the sensing line SL, the width becomes gradually wider than the width of the active region 26 below the sensing line SL. In other words, the width of the active region 26 under the word line WL gradually increases from the floating diffusion region 26f to the source region 26s. On the contrary, in an embodiment, the active region 26 below the word line WL is gradually wider than the width of the active region 26 below the sensing line SL as the sensing line becomes closer to the sensing line. This can be widened.

 In general, in a cell array region of a nonvolatile memory device, the active region has a predetermined width and is disposed at a constant pitch. Thus, the channel width of the memory transistor is constant throughout the channel and is formed equal to the channel width of the selection transistor. However, as shown, in one embodiment of the present invention, the active region 26 below the word line WL is formed to gradually increase in width. Accordingly, the active region 26 under the word line WL includes a wider area than the active region 26 under the sensing line SL, and the effective channel width of the memory transistor increases. As a result, the driving current of the memory transistor is increased under the same voltage condition, so that the performance of the transistor can be improved.

An interlayer insulating layer 28 is formed on the entire surface of the substrate 10 on which the sensing line SL and the word line WL are formed. A bit line contact 30 connected to the drain region 26d through the interlayer insulating layer 28 electrically connects the bit line BL disposed on the interlayer insulating layer to the drain region 26d.

5 is a plan view of a Y pyrom according to another embodiment of the present invention.

Referring to FIG. 5, device isolation layers 12 defining active regions 26 are disposed on a semiconductor substrate 10 (hereinafter, referred to as a substrate). The gate insulating layer 14 is formed on the active region 26 of the substrate 10. The gate insulating layer 14 may be formed of a silicon oxide layer having excellent properties, for example, a thermal oxide layer. Source regions 26s, floating diffusion regions 26f, and drain regions 26d, which are spaced at predetermined intervals, are formed in the active region 26.

 A word line WL is disposed between the source region 26s and the floating diffusion region 26f to cross the upper portion of the active region 26, and between the floating diffusion region 26f and the drain region 26d. A sensing line SL is disposed in the upper surface of the active region 26. The sensing line SL includes a floating gate 22s and a control gate electrode 24s.

 The floating gate 22s is disposed on the gate insulating layer 14. The floating gate 22s may be made of doped polysilicon. The control gate electrode 24s is formed on the floating gate 22s to cross the active region 26. The control gate electrode 24s may be formed of a conductive film. For example, it may be formed of a single film selected from doped polysilicon, metal silicide, conductive metal nitride, metal, or a combination thereof. Preferably, the control gate electrode 24s is a single film selected from doped polysilicon, tungsten silicide, cobalt silicide, nickel silicide, titanium silicide, titanium nitride, tantalum nitride, tungsten, molybdenum, or a combination thereof. It can be formed as.

 An inter-gate dielectric 16 is interposed between the floating gate 22s and the control gate electrode 24s. The inter-gate dielectric layer 16 may be formed of an oxide-nitride-oxide (ONO) layer. In contrast, the inter-gate dielectric layer 16 may include a high dielectric layer having a higher dielectric constant than the ONO layer. For example, it may be formed of a metal oxide film such as an aluminum oxide film or a hafnium oxide film.

The word line WL consists of a lower gate electrode 22w and an upper gate electrode 24w and is electrically connected to any part of the substrate 10. The lower gate electrode 22w and the upper gate electrode 24w may be formed of a conductive film. For example, it may be formed of a single film selected from doped polysilicon, metal silicide, conductive metal nitride, metal, or a combination thereof. Preferably, the lower gate electrode 22w and the upper gate electrode 24w are one selected from doped polysilicon, tungsten silicide, cobalt silicide, nickel silicide, titanium silicide, titanium nitride, tantalum nitride, tungsten, and molybdenum. It may be formed of a single film or a combination thereof.

The active region 26 between the device isolation layers 12 under the word line WL is divided into the active region 26 under the word line WL. The first region is divided in parallel with the word line WL. As shown, the width of the active area 26 of the first area A and the second area B, which is far from the sensing line SL, is wide. In other words, the width of the active region 26 of the second region B near the source region 26s is wider than that of the first region A near the floating diffusion region 26f. The first area A is equal to the width of the active area 26 below the sensing line SL. On the contrary, in another embodiment, the active region 26 under the word line WL includes first and second regions B divided in parallel with the word line WL. The width of the active region 26 in a portion of the first region A and the second region B that is close to the sensing line SL may be wide.

Like the first embodiment of the present invention, the active region 26 under the word line WL includes a wider area than the active region 26 under the sensing line SL, and has an effective channel width of the memory transistor. This increases. As a result, the driving current of the memory transistor is increased under the same voltage condition, so that the performance of the transistor can be improved.

An interlayer insulating layer 28 is formed on the entire surface of the substrate 10 on which the sensing line SL and the word line WL are formed. A bit line contact 30 connected to the drain region 26d through the interlayer insulating layer 28 electrically connects the bit line BL disposed on the interlayer insulating layer to the drain region 26d.

The description of the above embodiments is merely given by way of example with reference to the drawings in order to provide a more thorough understanding of the present invention and should not be construed as limiting the invention. In addition, various changes and modifications are possible to those skilled in the art without departing from the basic principles of the present invention.

As described above, according to the present invention, the active area under the word line is formed to include a width of the active area wider than the width of the active area under the sensing line. As a result, the width of the effective channel region of the memory transistor is increased. As a result, the driving current of the memory transistor is increased to improve the performance of the transistor.

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Claims (5)

An isolation layer defining an active region; A sensing line crossing the top of the active region and including a floating gate and a control gate electrode; A word line spaced apart from the sensing line and crossing the upper portion of the active area, And an active area under the word line includes a wider area than an active area under the sensing line. The method of claim 1, The active area under the word line is The width of the non-volatile memory device, characterized in that the wider the distance away from the sensing line. The method of claim 1, The active area under the word line is Non-volatile memory device characterized in that the width is closer to the sensing line. The method of claim 1, The active area under the word line is And a first region and a second region divided in parallel to the word line, wherein the active region of the first region and the second region is far from the sensing line. The method of claim 1, The active area under the word line includes a first area and a second area divided in parallel with the word line, and a wide area of the active area of the first area and the second area close to the sensing line is wide. Non-volatile memory device characterized in that.

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