KR20070020746A - Display device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device, and more particularly, to a display device capable of repairing a main gate driver using a dummy gate driver.

The display device includes a plurality of pixels each including a switching element, a gate line connected to the switching element, and a plurality of first and second stages connected to each other and sequentially generating output signals, respectively. And a first gate driver, and one of the first stages of the first gate driver is connected to the same gate line between the second stage of the second gate driver and the switching element.

As described above, the sub-gate driver having the same structure as the main gate driver may be disposed to easily repair the stage of the main gate driver if the stage is defective.

Display, repair, laser, stage, small to medium size, switching element

Description

Display device {DISPLAY DEVICE}

With reference to the accompanying drawings will be described in detail the embodiments of the present invention to make the present invention clear.

1 is a schematic diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

2 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

3 is an equivalent circuit diagram of one pixel of a liquid crystal display according to an exemplary embodiment of the present invention.

4 is a block diagram of a gate driver according to an exemplary embodiment of the present invention.

FIG. 5 is an example of a circuit diagram of the j-th stage of the shift register for gate driver shown in FIG.

6 is a signal waveform diagram of the gate driver shown in FIG. 4.

FIG. 7 is a diagram illustrating an example of a repaired state in the block diagram shown in FIG. 4.

<Description of Drawing>

3: liquid crystal layer 100: lower display panel

191: pixel electrode 200: upper display panel

230: color filter 270: common electrode

300: liquid crystal panel assembly

400, 400RM, 400LM, 400S: Gate Driver

500: data driver 600: signal controller

650: main FPC 660: input

680: secondary FPC 690: opening

700: integrated chip 800: gray voltage generator

R, G, B: Input image data DE: Data enable signal

MCLK: Main Clock Hsync: Horizontal Sync Signal

Vsync: Vertical Sync Signal CONT1: Gate Control Signal

CONT2: data control signal DAT: output video signal

PX: Pixel Clc: Liquid Crystal Capacitor

Cst: retention capacitor Q: switching element

STV: scan start signal CLK1, CLK2: first and second clock signals

S: set terminal R: reset terminal

GV: gate voltage terminal OUT1, OUT2: output terminal

The present invention relates to a display device.

Recently, an organic light emitting diode display, a plasma display panel, a liquid crystal display (LCD) instead of a heavy and large cathode ray tube (CRT) Flat panel display devices such as are being actively developed.

The PDP is a device for displaying characters or images using plasma generated by gas discharge, and the organic light emitting diode display displays characters or images by using electroluminescence of specific organic materials or polymers. The liquid crystal display device applies an electric field to a liquid crystal layer interposed between two display panels, and adjusts the intensity of the electric field to adjust a transmittance of light passing through the liquid crystal layer to obtain a desired image.

Among such display devices, particularly, small display devices used in cellular phones and the like are actively developing dual display devices each having a display panel portion outside and inside.

The dual display device may include a main flexible display circuit board (FPC) having a main display panel unit mounted therein, a sub display panel unit mounted externally, a wiring for transmitting an input signal from the outside, and a main display panel. Auxiliary FPC connecting the part and the sub-display panel, and an integrated chip for controlling them.

Among the dual display devices, for example, a liquid crystal display and an organic light emitting diode display include a pixel including a switching element, a display panel provided with a display signal line, and a gate on voltage and a gate off voltage applied to a gate line among the display signal lines to switch pixels. A gate driver for turning the device on / off and a data driver for outputting a data voltage to a data line among the display signal lines and applying the data voltage to the pixel through the turned-on switching device; and the integrated chip includes a gate driver and data of the main display panel and the sub-display panel. It generates a control signal and a drive signal for controlling the driver, and is mainly mounted on the main display panel in the form of a chip on glass (COG).

On the other hand, in such a large-sized display device as well as a large display device, in order to reduce costs, the gate driver may be formed in the same process as the switching element of the pixel and integrated in the display panel.

The gate driver includes a plurality of stages that are substantially connected to each other and arranged in a row as a shift register, and the first stage receives a scan start signal to output a gate output while simultaneously carrying a carry output to the next stage. Send to sequentially generate the gate outputs.

On the other hand, the stage of the gate driver is composed of a plurality of transistors, and if any one of these transistors is defective, the output of the stage is not generated, which also affects the next stage and eventually appears as a defect of the gate driver itself. However, repairing these defects is not easy.

Accordingly, an aspect of the present invention is to provide a display device capable of repairing a main gate driver by providing a sub gate driver.

According to an aspect of the present invention, a display device includes a plurality of pixels each including a switching element, a gate line connected to the switching element, and a plurality of output lines connected to each other and sequentially generating output signals. And first and second gate drivers including first and second stages, respectively, wherein one of the first stages of the first gate driver is one of the second stages of the second gate driver and the switching element. Are connected to the same gate line with the gap between them.

When any one of the first stages is a defect stage that cannot generate an output, the second stage connected to the same gate line as the defect stage may generate an output.

At this time, the switching element connected to the gate line between the defect stage and the second stage and the switching element connected to the front gate line of the gate line may be turned on at the same time.

In addition, each of the first and second stages may include first and second terminal lines, and signal lines connected to the second and second terminal lines and connected to the front and rear stages of each stage, respectively. The first and second terminals of the front stage of the second stage, wherein the first and second terminal lines are disconnected and a part of the first terminal lines are shorted to the signal line and connected to the same gate line as the defective stage. A line may be disconnected and a part of the first terminal line may be shorted to the signal line.

In addition, the second terminal line of the second stage connected to the same gate line as the defect stage may be disconnected.

DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a portion of a layer, film, region, plate, etc. is said to be "on top" of another part, this includes not only when the other part is "right on" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

A display device according to an embodiment of the present invention will now be described in detail with reference to the accompanying drawings, and a liquid crystal display device will be described as an example.

1 is a schematic diagram of a liquid crystal display according to an embodiment of the present invention, FIG. 2 is a block diagram of a liquid crystal display according to an embodiment of the present invention, and FIG. 3 is a liquid crystal display according to an embodiment of the present invention. An equivalent circuit diagram for one pixel of the device.

In the following description, the gate driver 400 may be the gate driver 400RM, the gate driver 400LM, or the gate driver 400S, unless otherwise specified.

Referring to FIG. 1, a display device according to an exemplary embodiment of the present invention includes a flexible printed circuit film (FPC) 650 attached to a main display panel 300M, a sub display panel 300S, and a main display panel 300M. , An auxiliary FPC 680 attached between the main display panel 300M and the sub display panel 300S, and an integration chip 700 mounted on the display panel 300M.

The FPC 650 is attached near one side of the main display panel portion 300M. In addition, it has an opening part 690 which exposes a part of main display panel part 300M when FPC 650 is folded in an assembled state. The lower part of the opening 690 is provided with an input unit 660 through which a signal from the outside is input, and electrical connection between the other input unit 660, the integrated chip 700, the integrated chip 700, and the main display panel unit 300M is performed. A plurality of signal lines (not shown) are provided, and these signal lines are generally wider at the point where they are connected to the integrated chip 700 and the point where they are attached to the main display panel part 300M to form a pad (not shown). Achieve.

The auxiliary FPC 680 is attached between the other side of the main panel 300M and one side of the sub-display panel 300S, and has a signal line for electrical connection between the integrated chip 700 and the sub-display panel 300S. SL2, DL).

Each display panel unit 300M and 300S includes display areas 310M and 310S and peripheral areas 320M and 320S forming a screen, and a light blocking layer (not shown) for blocking light in the peripheral areas 320M and 320S. ("Black matrix") may be provided. An FPC 650 and an auxiliary FPC 680 are attached to the light shielding areas 320M and 320S.

As shown in FIG. 2, each display panel unit 300M and 300S is connected to a plurality of display signal lines including a plurality of gate lines G ₁ -G _n and a plurality of data lines D ₁ -D _m . and it includes a gate driver 400 for supplying a signal at about a plurality of pixels (PX) arranged in a matrix, and gate lines (G ₁ -G _n), the pixel and display signal lines (G ₁ -G _n, Most of D ₁ -D _m is positioned in the display regions 310M and 310S, and the gate drivers 400M and 400S are positioned in the peripheral regions 320M and 320S, respectively. The peripheral areas 320M and 320S on the side where the gate drivers 400M and 400S are located have a larger width.

As shown in FIG. 1, some of the data lines D ₁ -D _m of the main display panel unit 300M are connected to the sub display panel unit 300S through the auxiliary FPC 680. That is, the two display panel units 300M and 300S share a part of the data lines D ₁ -D _m , and one of them is shown in the drawing.

Since the upper panel 200 is smaller than the lower panel 100, a portion of the lower panel 100 is exposed and the data lines D ₁ -D _m extend to the area to be connected to the data driver 500. The gate lines G ₁ -G _n also extend to regions covered by the peripheral regions 320M and 320S and are connected to the gate drivers 400RM, 400LM, and 400S.

The display signal lines G ₁ -G _n and D ₁ -D _m are generally wide at the point where they are connected to the FPCs 650 and 680 to form pads (not shown), and the display panel portions 300M and 300S and the FPCs. 650 and 680 are attached by an anisotropic conductive film (not shown) for electrical connection of these pads.

Each pixel PX, for example, the pixel PX connected to the i-th (i = 1, 2,, n) gate line G _i and the j-th (j = 1, 2,, m) data line Dj. ) Includes a switching element Q connected to the signal line G _i D _j , a liquid crystal capacitor Clc, and a storage capacitor Cst connected thereto. Holding capacitor Cst can be omitted as needed.

The switching element Q is a three-terminal element of a thin film transistor or the like provided in the lower panel 100, the control terminal of which is connected to the gate line G _i , and the input terminal of which is connected to the data line D _j . The output terminal is connected to the liquid crystal capacitor Clc and the storage capacitor Cst.

The liquid crystal capacitor Clc has two terminals, the pixel electrode 191 of the lower panel 100 and the common electrode 270 of the upper panel 200, and the liquid crystal layer 3 between the two electrodes 191 and 270 is a dielectric material. Function as. The pixel electrode 191 is connected to the switching element Q, and the common electrode 270 is formed on the front surface of the upper panel 200 and receives the common voltage Vcom. Unlike in FIG. 2, the common electrode 270 may be provided in the lower panel 100. In this case, at least one of the two electrodes 191 and 270 may be formed in a linear or bar shape.

The storage capacitor Cst, which serves as an auxiliary part of the liquid crystal capacitor Clc, is formed by overlapping a separate signal line (not shown) and the pixel electrode 191 provided on the lower panel 100 with an insulator interposed therebetween. A predetermined voltage such as the common voltage Vcom is applied to the separate signal line. However, the storage capacitor Cst may be formed such that the pixel electrode 191 overlaps the front gate line directly above the insulator.

On the other hand, in order to implement color display, each pixel PX uniquely displays one of the primary colors (spatial division) or each pixel PX alternately displays the primary colors over time (time division). The desired color is recognized by the spatial and temporal sum of these primary colors. Examples of the primary colors include three primary colors such as red, green, and blue. FIG. 2 illustrates that each pixel PX includes a color filter 230 representing one of the primary colors in an area of the upper panel 200 corresponding to the pixel electrode 191 as an example of spatial division. Unlike FIG. 2, the color filter 230 may be formed above or below the pixel electrode 191 of the lower panel 100.

At least one polarizer (not shown) for polarizing light is attached to an outer surface of the liquid crystal panel assembly 300.

The gray voltage generator 800 generates two sets of gray voltages (or reference gray voltage sets) related to the transmittance of the pixel PX. One of the two sets has a positive value for the common voltage Vcom and the other set has a negative value.

The gate drivers 400RM, 400LM, and 400S may be connected to the gate lines G ₁ -G _n to turn off the gate-on voltage V _on and the switching element Q, which may turn _{on the} switching element Q. A gate signal composed of a combination of the gate off voltages V _off is applied to the gate lines G ₁ -G _n . The gate drivers 400RM, 400LM, and 400S are formed and integrated in the same process as the switching element Q of the pixel, and are connected to the integrated chip 700 through the signal lines SL1 and SL2, respectively.

Here, the gate drivers 400RM and 400LM of the main display panel 300M are disposed on the left and right to receive the same signal from the integrated chip 700 to perform the same operation, and are connected to the same gate lines G1 -Gn. The gate driver 400S may be disposed on the right side of the sub display panel 300S.

The data driver 500 is connected to the data lines D ₁ -D _m of the liquid crystal panel assembly 300 and selects a gray voltage from the gray voltage generator 800 and uses the data line D ₁ as a data signal. -D _m ). However, when the gray voltage generator 800 provides only a predetermined number of reference gray voltages instead of providing all of the voltages for all grays, the data driver 500 divides the reference gray voltages to divide the gray voltages for all grays. Generate and select the data signal from it.

The signal controller 600 controls the gate driver 400, the data driver 500, and the like.

The integrated chip 700 receives and processes an external signal through a signal line provided in the connection unit 660 and the FPC 650 to the peripheral area 320M and the auxiliary FPC 680 of the main display panel 300M. These are controlled by supplying to the main display panel 300M and the sub display panel 300S through the provided wirings. The gray voltage generator 800, the data driver 500, the signal controller 600, and the like shown in FIG. It includes.

The display operation of such a liquid crystal display device will now be described in detail.

The signal controller 600 receives input image signals R, G, and B and an input control signal for controlling the display thereof from an external graphic controller (not shown). Examples of the input control signal include a vertical sync signal Vsync, a horizontal sync signal Hsync, a main clock MCLK, and a data enable signal DE.

The signal controller 600 properly processes the input image signals R, G, and B based on the input image signals R, G, and B and the input control signal, according to the operating conditions of the liquid crystal panel assembly 300, and gates them. After generating the control signal CONT1 and the data control signal CONT2, the gate control signal CONT1 is sent to the gate driver 400, and the data control signal CONT2 and the processed image signal DAT are transmitted to the data driver 500).

The gate control signal CONT1 includes a scan start signal STV indicating a scan start and at least one clock signal controlling an output period of the gate-on voltage Von. The gate control signal CONT1 may also further include an output enable signal OE that defines the duration of the gate-on voltage Von.

The data control signal CONT2 is a horizontal synchronizing start signal STH indicating the start of image data transfer for one row of pixels PX and a load signal LOAD for applying a data signal to the data lines D ₁ -D _m . ) And a data clock signal HCLK. The data control signal CONT2 is also an inverted signal that inverts the voltage polarity of the data signal relative to the common voltage Vcom (hereinafter referred to as " polarity of the data signal " by reducing the " voltage polarity of the data signal for the common voltage &quot;) RVS) may be further included.

According to the data control signal CONT2 from the signal controller 600, the data driver 500 receives the digital image signal DAT for the pixel PX in one row and corresponds to each digital image signal DAT. The gradation voltage is selected to convert the digital image signal DAT into an analog data signal and then apply it to the data lines D ₁ -D _m .

The gate driver 400 applies the gate-on voltage Von to the gate lines G ₁ -G _n in response to the gate control signal CONT1 from the signal controller 600, thereby applying the gate lines G ₁ -G _n . Turn on the switching element (Q) connected to. Then, the data signal applied to the data lines D ₁ -D _m is applied to the pixel PX through the turned-on switching element Q.

The difference between the voltage of the data signal applied to the pixel PX and the common voltage Vcom is shown as the charging voltage of the liquid crystal capacitor Clc, that is, the pixel voltage. The arrangement of the liquid crystal molecules varies depending on the magnitude of the pixel voltage, thereby changing the polarization of light passing through the liquid crystal layer 3. The change in polarization is represented by a change in transmittance of light by a polarizer attached to the display panel assembly 300.

This process is repeated in units of one horizontal period (also referred to as "1H" and equal to one period of the horizontal sync signal Hsync and the data enable signal DE), thereby all gate lines G ₁ -G _n ), The gate-on voltage Von is sequentially applied to the data signal to all the pixels PX, thereby displaying an image of one frame.

When one frame ends, the state of the inversion signal RVS applied to the data driver 500 is controlled so that the next frame starts and the polarity of the data signal applied to each pixel PX is opposite to the polarity of the previous frame. "Invert frame"). In this case, the polarity of the data signal flowing through one data line is changed (eg, row inversion and point inversion) or the polarity of the data signal applied to one pixel row is different depending on the characteristics of the inversion signal RVS within one frame. (E.g. column inversion, point inversion).

Next, a display device according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 4 to 6.

4 is a block diagram of a gate driver according to an exemplary embodiment of the present invention. FIG. 5 is an example of a circuit diagram of the j-th stage of the shift register for gate driver shown in FIG. 4, and FIG. 6 is a signal waveform diagram of the gate driver shown in FIG.

The gate drivers 400L and 400R shown in FIG. 4 are shift registers including a plurality of stages 410L and 410R which are arranged in a line on the left and right and connected to the gate lines G _{1 to} G _n , respectively. The start signal STV, the plurality of clock signals CLK1 and CLK2 and the gate off voltage V _off are respectively input. However, the scan start signal STV is not input to the sub gate driver 400R positioned on the right side, and the switching unit SW is disposed in the gate lines G ₁ -G _n close to the sub gate driver 400R. .

Each stage 410L, 410R includes a set terminal S, a gate voltage terminal GV, a pair of clock terminals CK1 and CK2, a reset terminal R, and a gate output terminal OUT1 and a carry output terminal. (OUT2), the two output terminals (OUT1, OUT2) are respectively connected to the buffer (BF1, BF2).

Each stage, for example, the set terminal S of the j-th stage STj located on the left or right side, has a carry output of the front stage ST (j-1), that is, a front carry output Cout (j-1). The carry terminal of the rear stage [ST (j + 1)], that is, the rear stage carry output Cout (j + 1), is input to the reset terminal R, and the clock signal (CK1, CK2) is input to the reset terminal R. CLK1 and CLK2 are input, and the gate-off voltage V _off is input to the gate voltage terminal GV. The two output terminals OUT1 and OUT2 output the gate output Gout (N) and the carry output Cout (N) through the gate buffer BUF and the carry buffer CARRY, respectively. The gate output Gout (j) is output to the gate lines G ₁ -G _n connected thereto, and the carry output Cout (j) is the front and rear stages ST (j-1) and ST (j). +1)].

However, the scan start signal STV is input to the first stage ST1 of the main gate driver 400L located on the left instead of the front gate output. When the clock signal CLK1 is input to the clock terminal CK1 of the j th stage ST (j) and the clock signal CLK2 is input to the clock terminal CK2, the (j-1) th and (j) adjacent thereto are The clock signal CLK2 is input to the clock terminal CK1 of the +1) th stage [ST (j-1), ST (j + 1)], and the clock signal CLK1 is input to the clock terminal CK2.

Each clock signal CLK1 and CLK2 is equal to the gate-on voltage V _on when the voltage level is high and the gate-off voltage V _off when the voltage level is high so as to drive the switching element Q of the pixel. It is preferable. As illustrated in FIG. 6, each clock signal CLK1 and CLK2 may have a duty ratio of 50%, and a phase difference between the two clock signals CLK1 and CLK2 may be 180 °.

Referring to FIG. 5, each stage of the gate driver 400, for example, the j th stage, includes a plurality of NMOS transistors T1-T10 and capacitors C1-C3. However, PMOS transistors may be used instead of NMOS transistors. In addition, the capacitors C1-C3 may actually be parasitic capacitances between the gate and the drain / source formed during the process.

The transistor T1 is connected between the clock terminal CK1 and the output terminal OUT1, and the control terminal is connected to the contact J1.

The input terminal and the control terminal of the transistor T2 are commonly connected to the set terminal S, and the output terminal is connected to the contact J1.

The transistors T3 and T4 are connected in parallel between the contact J1 and the gate voltage terminal GV, the control terminal of the transistor T3 is connected to the reset terminal R, and the transistor T4 The control terminal is connected to the contact J2.

The transistors T5 and T6 are connected in parallel between the output terminal OUT1 and the gate voltage terminal GV. The control terminal of the transistor T5 is connected to the contact J2, and the control terminal of the transistor T6 is a clock terminal. Is connected to (CK2).

The transistor T7 is connected between the contact J2 and the gate voltage terminal GV, and the control terminal is connected to the contact J1.

The transistor T8 is connected between the clock terminal CK1 and the output terminal OUT2, and the control terminal is connected to the contact J1.

The transistors T9 and T10 are connected in parallel between the output terminal OUT2 and the gate voltage terminal GV. The control terminal of the transistor T9 is connected to the clock terminal CK2 and the control terminal of the transistor T10 is contacted. Is connected to (J2).

Capacitor C1 is between clock terminal CK1 and contact J2, capacitor C2 is between contact J1 and output terminal OUT1, and capacitor C3 is contact J1 and output terminal OUT2. It is connected between.

Next, the j-th stage STj will be described with reference to the operation of such a stage.

For convenience of explanation, the voltage corresponding to the high level of the clock signals CLK1 and CLK2 is referred to as a high voltage, and the magnitude of the voltage corresponding to the low level of the clock signals CLK1 and CLK2 is equal to the gate off voltage V _off . This is called low voltage.

First, when the clock signal CLK2 and the front gate output Gout (j-1) become high, the transistors T2, T6, and T9 are turned on. Transistor T2 then transfers a high voltage to contact J1 to turn on transistor T7. The transistors T6 and T9 transfer low voltages to the output terminals OUT1 and OUT2, respectively, and the turned-on transistor T7 transfers low voltages to the contact point J2. As a result, the transistors T1 and T8 are turned on to output the clock signal CLK1 to the output terminals OUT1 and OUT2. At this time, since the clock signal CLK1 is low voltage, the gate output Gout (j) and the carry output are output. [Cout (j)] becomes a low voltage. At the same time, the capacitor C1 is not charged because the voltage at both ends is the same, while the capacitors C2 and C3 charge a voltage corresponding to the difference between the high voltage and the low voltage.

At this time, since the clock signal CLK1 and the rear carry output Cout (j + 1) are low and the contact J2 is also low, all the transistors T3, T4, T5, and T10 connected thereto are connected. It is off.

Subsequently, when the clock signal CLK2 and the front carry output Cout (j-1) go low, the transistors T6 and T9 and the transistor T2 are turned off. Accordingly, the two capacitors C2 and C3 having one end connected to the contact J2 become in a floating state, and the transistors T1 and T8 maintain the turned on state.

At this time, since the clock signal CLK1 becomes high, the voltages of the two output terminals OUT1 and OUT2 are turned high, and the potential of the contact J1 is further increased by the high voltage by the capacitors C2 and C3. Although shown in FIG. 6 as the same as the previous voltage, it actually rises further by the high voltage.

At this time, since the rear carry output Cout (j + 1) and the contact J2 are low, the transistors T5, T6, T9, and T10 are also turned off. Therefore, the two output terminals OUT1 and OUT2 are connected only to the clock signal CLK1 and cut off from the low voltage to emit a high voltage.

On the other hand, the capacitor C1 charges a voltage corresponding to the potential difference between both ends.

Subsequently, when the rear carry output Cout (j + 1) and the clock signal CLK2 go high and the clock signal CLK1 goes low, the transistor T3 is turned on to transfer a low voltage to the contact J1. As a result, the transistor T7 having the control terminal connected to the contact J1 is turned off so that the capacitor C1 is in a floating state, and the contact J2 maintains the low voltage, which is the previous voltage. At this time, since the clock signal CLK1 is low, the voltage across the capacitor C1 becomes 0V.

At the same time, the two output terminals OUT1 and OUT2 turn off the transistors T1 and T8, respectively, to be disconnected from the clock signal CLK1, while the transistors T6 and T9 are turned on and connected to the low voltage, respectively. Export.

Next, when the clock signal CLK1 becomes high, the voltage at one end of the capacitor C1 is changed to a high voltage, and the other end of the capacitor C1, that is, the voltage at the contact J2 is also changed to a high voltage, thereby reducing the voltage at both ends of the capacitor C1. Keep it at 0V. Accordingly, since the transistor T4 is turned on to transfer the low voltage to the contact J1, the two transistors T1 and T8 continue to be turned off, and the two transistors T5 and T10 are turned on so that both low voltages are applied. The output terminals OUT1 and OUT2 continue to emit low voltage because they are delivered to the output terminals OUT1 and OUT2.

Thereafter, the voltage at the contact J1 maintains a low voltage until the front carry output Cout (j-1) becomes high, and the voltage at the contact J2 is in response to the clock signal CLK1 due to the capacitor C1. Change in motivation. Therefore, the output terminals OUT1 and OUT2 connect the transistors T5 and T10 with the low voltage when the clock signal CLK1 is high and the clock signal CLK2 is low, and vice versa. Connected to the low voltage.

In this manner, each stage 410L, 410R is based on the front carry signal Cout (j-1) and the back carry signal Cout (j + 1) and in synchronization with the clock signals CLK1, CLK2. Create [Gout (j)].

Then, for example, when the j-th stage STj fails to generate a gate output, the repairing method will be described in detail with reference to FIG. 7. For convenience of description, the scan start signal STV, The clock signals CLK1 and CLK2 and the gate off voltage V _off are not shown. In the drawings, portions cut through laser irradiation are indicated by x marks LC, and portions shorted through laser irradiation are denoted by triangular marks LS.

The main gate driver 400L located on the left side and the sub gate driver 400R located on the right side are disposed symmetrically with each other, and each stage 410L of the main gate driver 400L is disposed of the right gate driver 400R facing each other. The switching unit SW is connected to the same gate line G _{j -2} -G _{j + 2} as the stage 410R, and is disposed closer to the sub gate driver 400R as described above. In the normal operation, the switching unit SW is turned off and turned on as necessary, and a separate control signal for the operation of the switching unit SW may be applied. Alternatively, the gate lines G ₁ -G _n between the main gate driver 400L and the sub gate driver 400R may be disconnected and irradiated with a laser to necessary portions.

Each stage ST (j-2) -ST (j + 2) is connected to the first terminal line TL ₁ and the output terminal OUT2 connected between the switching unit SW and the output terminal OUT1. Is connected to the second terminal line TL ₂ and the second terminal line TL ₂ , and is connected to the front and rear stages, respectively, and includes signal lines SL _j-1 , SL _j , SL _{j + 1} . do.

At this time, the switching unit SW located at the (j-1) th gate line G _j-1 and the switching unit SW located at the j th gate line G _j are turned on, and the sub gate driver 400R is turned on. The terminal lines TL ₁ and TL ₂ extending from the output terminals OUT1 and OUT2 of the (j-1) th stage ST (j-1) of are cut, while the signal lines SL _j-1 and the gate are cut. Short the line (G _j-1 ). Accordingly, the gate output Gout (j-1) is input to the j-th stage STj of the sub gate driver 400R to operate the stage STj.

Similarly, the terminal lines TL ₁ and TL ₂ extending from the output terminals OUT1 and OUT2 of the j-th stage STj of the main gate driver 400L are cut off, and the signal lines SLj and the gate line G _j are cut off. Short circuit. Then, the gate output Gout (j) generated in the j-th stage STj of the sub-gate driver 400L is the (j-1) th stage [ST (j-1)] of the main gate driver 400L. It is input to the set terminal S of the reset terminal R and the (j + 1) th stage ST (j + 1), respectively. On the other hand, the terminal line TL ₂ connected to the output terminal OUT2 of the sub-gate driver 400R is cut off so that the carry output Cout (j) is not input, thereby the (j + 1) th stage [ST (j +). 1)] afterwards to prevent the stage from operating.

As such, the sub-gate driver 400R having the same structure as the main gate driver 400L may be disposed to easily repair the stage 410L of the main gate driver 400L when it is defective.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

Claims (5)

A plurality of pixels each including a switching element, A gate line connected to the switching element, and First and second gate drivers connected to each other and each including a plurality of first and second stages which in turn generate an output signal. Including; Any one of the first stages of the first gate driver is connected to the same gate line with a switching element between any one of the second stages of the second gate driver. Display device. In claim 1, And any one of the first stages is a defect stage that cannot generate an output, wherein the second stage, which is connected to the same gate line as the defect stage, generates an output. In claim 2, And a switching device connected to the gate line between the defect stage and the second stage and a switching device connected to a front gate line of the gate line at the same time. In claim 3, Each of the first and second stages includes first and second terminal lines, and a signal line connected to the second terminal line and connected to the front and rear stages of each stage, The first and second terminal lines of the defect stage are disconnected, a portion of the first terminal line is shorted to the signal line, and the first stage of the front end stage of the second stage is connected to the same gate line as the defect stage. And a second terminal line is disconnected and a part of the first terminal line is shorted to the signal line. Display device. In claim 4, And the second terminal line of the second stage connected to the same gate line as the defective stage is disconnected.

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