CN1877688B - Display device - Google Patents

Abstract

The invention relates to a display device, in particular to a display device capable of repairing gate lines and main gate drivers. The display device includes a plurality of pixels respectively including switching elements, gate lines connected to the switching elements, and first and second gate drivers respectively including a plurality of stages interconnected and successively generating output signals. Either stage of the first gate driver and any stage of the second gate driver are connected to the same gate line. In this way, the gate drivers that produce the same output are located in one gate line on the left and right. Therefore, the disconnected gate line can be repaired without using a laser.

Description

display screen

Cross References to Related Applications

This application claims priority to Korean Patent Applications No. 10-2005-0048299 and No. 10-2005-0074963 filed with the Korean Industrial Property Office on Jun. 7, 2005 and Aug. 16, 2005, the contents of which are hereby Included by reference.

technical field

The present invention relates to a display device.

current technology

Flat panel displays such as organic light emitting diode (OLED) displays, plasma display panels (PDP) and liquid crystal displays (LCD) have been effectively developed to replace heavy and bulky cathode ray tubes (CRTs). The PDP displays characters and/or images by using plasma generated by gas discharge. The OLED display displays characters and domain images by using an electric field emitted by a specific organic body or polymer. The liquid crystal display displays images by applying an electric field to a liquid crystal layer between two display panels and controlling the strength of the electric field to thereby control light transmittance through the liquid crystal layer.

A dual display device for a mobile phone or the like includes an internal main display panel unit and an externally mounted secondary display panel. A flexible printed circuit (FPC) film receives an external input signal, and the sub-FPC is connected to a main display panel and a sub-display panel unit, both of which are controlled by an integrated chip. Each of the aforementioned devices includes a display panel, a large number of pixels, a gate driver, and a data driver, where each pixel has a switching element and a display signal line. An integrated chip for controlling a gate driver and a data driver of the main display panel unit and the sub display panel unit is generally mounted in the main display panel unit in the form of a chip on glass (COG). The gate driver includes a plurality of shift register stages interconnected and arranged in a row.

In order to correct manufacturing defects such as disconnected signal lines, etc., a plurality of repair lines are provided in a peripheral area outside the display area, wherein the repair lines are connected to left and right sides of the plurality of disconnected gate lines, and A gate signal is applied to the repair line. A magnifying lens must be used to find the broken line, after which a laser is used to repair the broken part. In addition, the number of repair lines that may be located in the peripheral area is limited, which makes it impossible to repair multiple disconnected portions. However, defects in any transistor are not easily repairable.

Contents of the invention

The present invention provides a display device in which a gate line can be repaired without using a laser and a main gate driver can be repaired using a sub gate driver. The first stage of the first gate driver and the second stage of the second gate driver are connected to the same gate line, and the switching element is located between the first stage and the second stage, so if any one of the first stage fails so that no output can be produced, the output is produced by a second stage connected to the faulty stage via the same gate line.

Description of drawings

The foregoing objects and features will become more apparent from the ensuing description when read in conjunction with the accompanying drawings, in which:

FIG. 1 is a schematic diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

FIG. 2 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

FIG. 3 is an equivalent circuit diagram illustrating one pixel of a liquid crystal display according to an exemplary embodiment of the present invention.

FIG. 4 is a block diagram of a gate driver according to an exemplary embodiment of the present invention.

FIG. 5 is an exemplary circuit diagram of a j-th stage of a shift register for the gate driver shown in FIG. 4 .

FIG. 6 is a signal waveform diagram of the gate driver shown in FIG. 4 .

FIG. 7 is a block diagram of a gate driver according to another exemplary embodiment of the present invention.

FIG. 8 is a view showing an example of repairing a gate driver in the block diagram shown in FIG. 7 .

Detailed ways

The thickness of the layers is exaggerated in the figures. Throughout the specification, the same reference numerals denote the same elements. When it is described that, eg, a layer, film, region, or panel, any part is on another part, it means that the part is directly on or above the other part with at least one intervening part therebetween. On the other hand, if it is described that any part is directly on another part, it means that there is no intermediate part between these two parts.

In FIG. 1 , unless otherwise specified, the gate driver 400 may be a gate driver 400RM, a gate driver 400LM, or a gate driver 400S. The display device includes a main display panel unit 300M, a sub display panel unit 300S, an FPC 650 attached to the main display panel unit 300M, a sub FPC 680 attached between the main display panel unit 300M and the sub display panel unit 300S, and The integrated chip 700 mounted on the display panel unit 300M.

The FPC 650 is attached near one side of the main display panel unit 300M. Also, the FPC 650 has an opening 690 that exposes a portion of the main display panel unit 300M when the FPC 650 is folded. The input part 660 is located under the opening 690 , wherein an external signal is input to the input part 660 . The FPC 650 also includes a plurality of signal lines (not shown) for electrically connecting other parts of the input part 660 and the integrated chip 700, and electrically connecting the integrated chip 700 and the main display panel unit 300M. These signal lines have a wide width at the points where they are connected to the integrated chip 700 and at the points where they are attached to the main display panel unit 300M, thereby forming spacers (not shown).

The sub FPC 680 is attached between the other side of the main display panel unit 300M and one side of the sub display panel unit 300S, and includes signal lines SL2 and DL for electrically connecting the integrated chip 700 and the sub display panel unit 300S. The display panel unit 300M includes a display area 310M forming a screen, and a peripheral area 320M. The peripheral area 320M may include a light shielding layer (not shown) (“black matrix”) for shielding light. Also, the display panel unit 300S includes a display area 310S forming a screen and a peripheral area 320S. The peripheral area 320S may include a light shielding layer (not shown) (“black matrix”) for shielding light. The FPC 650 and the sub FPC 680 are attached to the peripheral areas 320M and 320S.

As shown in FIG. 2, each display panel unit 300M and 300S includes a plurality of display signal lines having a plurality of gate lines G ₁ -G _n and a plurality of data lines D ₁ -D _m , connected to the gate lines and data lines and a plurality of pixels PX roughly arranged in a matrix form, and a gate driver 400 providing signals to the gate lines G ₁ -G _n . Most of the pixels PX and the display signal lines G ₁ -G _n and D ₁ -D _m are located in the display areas 310M and 310S. Gate drivers 400M and 400S are located in the peripheral regions 320M and 320S. The peripheral regions 320M and 320S on the side where the gate drivers 400M and 400S are located have slightly larger widths.

As shown in FIG. 1 , a part of the data lines D ₁ -D _m of the main display panel unit 300M is connected to the sub display panel unit 300S through the sub FPC 680 . That is, the two display panel units 300M and 300S share a part of the data lines D1 _{-Dm .} In Fig. 1, one of the data lines is shown as DL. The upper board 200 is smaller than the lower board 100, and thus a portion of the lower board 100 is exposed. The data lines D ₁ -D _m extend up to this area and then connect to the data driver 500 . The gate lines G ₁ -G _n also extend upward to the area covered with the peripheral areas 320M and 320S, and then are connected to the gate drivers 400RM, 400LM, and 400S.

The display signal lines G ₁ -G _n and D ₁ -D _m have wide widths at the points where they are connected to the FPCs 650 and 680, thereby forming pads (not shown). The display panel units 300M and 300S and the FPCs 650 and 680 are adhered by an anisotropic conductive layer (not shown) to electrically connect the pads. Each pixel PX (for example, connected to the i-th (i=1, 2, . . . , n) gate line G _i and the j-th (j=1, 2, . . . , m) data line D _j The pixels PX) each include a switching element Q connected to the signal lines G _i and D _j , and a liquid crystal capacitor Clc and a storage capacitor Cst connected to the switching element Q. The storage capacitor Cst can be omitted if appropriate.

The switching element Q may be a three-terminal element provided in the lower board 100 such as a thin film transistor. The switching element Q has a control terminal connected to the gate line _Gi , an input terminal connected to the data line _Dj , and an output terminal connected to the liquid crystal capacitor Clc and the storage capacitor Cst. The liquid crystal capacitor Clc uses the pixel electrode 191 of the lower panel 100 and the common electrode 270 of the upper panel 200 as two terminals. The liquid crystal layer 3 between the two electrodes 191 and 270 acts as a dielectric material. The pixel electrode 191 is connected to the switching element Q. The common electrode 270 is formed on the entire surface of the upper board 200 and receives the common voltage Vcom. Unlike that shown in FIG. 2 , the common electrode 270 may be located in the lower board 100 . In this case, at least one of the two electrodes 191 and 270 may have a linear or rod shape.

The storage capacitor Cst for assisting the liquid crystal capacitor Clc includes an additional signal line (not shown) and a pixel electrode 191 provided in the lower panel 100 with an insulator overlapped therebetween. A common voltage Vcom is applied to the additional signal line. However, in the storage capacitor Cst, the pixel electrode 191 may overlap the gate line immediately above the previous gate line through the intermediary of an insulator.

In order to achieve color display, each pixel PX can uniquely display a primary color (space division), or each pixel PX can alternately display the primary color according to time (time division), so it can be determined by the sum of the space and time of the primary color Identify the desired color. An example of primary colors may include three primary colors such as red, green and blue. As an example of space division, FIG. 3 shows an example in which each pixel PX has a color filter 230 showing a primary color on a region of the upper plate 200 corresponding to the pixel electrode 191 . Unlike FIG. 3 , the color filter 230 may be formed on or under the pixel electrode 191 of the lower panel 100 . At least one polarizer (not shown) for polarizing light is attached to the outside of the liquid crystal panel assembly 300 .

The grayscale voltage generator 800 generates two sets of grayscale voltages (or reference grayscale voltages), wherein the two sets of grayscale voltages are related to the transmittance of the pixel PX. One of the two groups has a positive value with respect to the common voltage Vcom, and the other of the two groups has a negative value with respect to the common voltage Vcom.

The gate drivers 400RM, 400LM, and 400S are connected to the gate lines G ₁ -G _n , and apply gate signals that are a gate-on voltage Von capable of turning on the switching element Q and a voltage Von capable of turning off the switching element Q. The combination of the gate off voltage Voff. The gate drivers 400RM, 400LM, and 400S are conveniently formed and integrated using the same process as the switching element Q of the pixel, and are connected to the integrated chip 700 through signal lines SL1 and SL2. The gate drivers 400RM and 400LM are located on the right and left sides of the main display panel unit 300M, respectively, and are connected to the same gate lines G1-Gn. The gate drivers 400RM and 400LM perform the same operation according to the same signal from the integrated chip 700 . In the sub display panel 300S, the gate driver 400S may also be located on the right side.

The data driver 500 is connected to the data lines D ₁ -D _m of the liquid crystal panel assembly 300 . The data driver 500 selects the grayscale voltage output from the grayscale voltage generator 800 and applies it to the data lines _D1 - _Dm as data signals. However, in the case that the grayscale voltage generator 800 does not provide the voltage of the entire grayscale but only a predetermined number of reference grayscale voltages, the data driver 500 splits the reference grayscale voltage to generate all grayscale voltages. gray-scale voltage, and select the data signal from the generated gray-scale voltage.

The signal controller 600 controls the gate driver 400, the data driver 500, and the like. The integrated chip 700 receives an external signal through the signal line provided in the input part 660 and the FPC 650, and supplies the processed signal to the main display panel unit through the wiring provided in the peripheral area 320M of the main display panel voltage 300M and the sub-FPC 680 300M and the sub display panel unit 300S, thereby controlling the main display panel unit 300M and the sub display panel unit 300S. The integrated chip 700 includes the grayscale voltage generator 800 shown in FIG. 2, the data driver 500, the signal controller 600, and the like.

The display operation of the liquid crystal display constructed according to the above description will be described in detail below. The signal controller 600 receives input image signals R, G, and B from an external graphics controller (not shown), and receives input control signals for controlling the display of these signals. Examples of input control signals may include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a master clock signal MCLK, a data enable signal DE, and the like. The signal controller 600 processes the input image signals R, G, and B in a manner suitable for the operating conditions of the liquid crystal panel assembly 300 based on the input image signals R, G, and B and the input control signal, and generates a gate control signal CONT1, a data control signal CONT2 and so on, transmit the gate control signal CONT1 to the gate driver 400 , and transmit the data control signal CONT2 and the processed image signal DAT to the data driver 500 .

The gate control signal CONT1 includes a scan start signal STV indicating scan start, and at least one clock signal controlling an output period of the gate-on voltage Von. The gate control signal CONT1 may further include an output enable signal (OE) to define a sustain period of the gate-on voltage Von. The data control signal CONT2 includes a horizontal synchronous start signal STH, a load signal LOAD, and a data clock signal HCLK to indicate that data signals are provided to the data lines D ₁ -D _m , wherein the horizontal synchronous start signal informs a row of pixels PX of the start of image data transmission. . The data control signal CONT2 may further include an inversion signal RVS for reversing the voltage polarity of the data signal for the common voltage Vcom (hereinafter, "the voltage polarity of the data signal for the common voltage" will be simplified as "data Polarity of the signal").

The data driver 500 receives the digital image signal DAT about one row of pixels PX in response to the data control signal CONT2 from the signal controller 600, selects a gray scale voltage corresponding to each digital image signal DAT, and converts the digital image signal DAT into an analog data signals, and then apply the converted signals to corresponding data lines D ₁ -D _m . The gate driver 400 applies the gate-on voltage Von to the gate lines _G1 - _Gn in response to the gate control signal CONT1 from the signal controller 600, thereby turning on the gate lines connected to the gate lines _G1 - _Gn . Switching element Q. Accordingly, the data signals applied to the data lines _D1 - _Dm are applied to the corresponding pixels PX through the switched-on switching elements Q.

The difference between the voltage of the data signal applied to the pixel PX and the common voltage Vcom appears as the charging voltage of the liquid crystal capacitor Clc, that is, the pixel voltage. The liquid crystal molecules are aligned according to the pixel voltage amount, thus changing the polarity of light passing through the liquid crystal layer 3 accordingly. A change in this polarity appears as a change in transmittance of light by a polarizer attached to the display panel assembly 300 .

These processes are repeated every horizontal period (this is also called "1H", which is the same as one period of the horizontal synchronization signal Hsync and the data enable signal DE), and the gate-on voltage Von is then applied to all the gate lines G ₁ -G _n , and the data signal is applied to all the pixels PX, thereby displaying an image of one frame. When one frame is completed, the next frame starts, and the state of the inversion signal RVS applied to the data driver 500 is controlled (image inversion), therefore, the polarity of the data signal supplied to each pixel PX becomes the same as the previous one. One frame of image is reversed. At this time, the polarity of the data signal flowing through one data line can be changed according to the characteristics of the inversion signal RVS even within one frame (for example: row inversion, dot inversion), or the data applied to one pixel row The polarity of the signal can be different according to the characteristics of the inversion signal RVS even within one frame (for example: column inversion, dot inversion).

A display device according to an exemplary embodiment of the present invention will be described in detail below with reference to FIGS. 4 to 6 . The gate drivers 400L and 400R shown in FIG. 4 are arranged in series on the left and right sides, and are shift registers including a plurality of stages 410L and 410R, respectively, wherein the plurality of stages are connected to gate lines G ₁ -G _n . A scan start signal STV, a plurality of clock signals CLK1 and CLK2 , and a gate-off voltage Voff are input to the gate drivers 400L and 400R, respectively. Each stage 410L and 410R has a set terminal S, a gate voltage terminal GV, a pair of clock terminals CK1 and CK2 , a reset terminal R, a gate output terminal OUT1 , and a carry output terminal OUT2 . These two output terminals OUT1 and OUT2 are connected to buffers BF1 and BF2, respectively.

Input the carry output of the previous stage ST(j-1) to the input terminal S of each stage (for example, the jth stage STj located on the left or right side) (that is, the previous carry output Cout(j -1)), input the carry output of the next stage ST(j+1) to its reset terminal R (that is, the next carry output Cout(j+1)), and input the clock signal CLK1 to its clock terminals CK1 and CK2 and CLK2, and input the gate off voltage Voff to the gate voltage terminal GV. The two output terminals OUT1 and OUT2 respectively output the output Gout(N) and the carry output Cout(N) through the gate buffer BUF and the carry buffer CARRY. The gate output Gout(j) is output to the gate lines G ₁ -G _n connected thereto. The carry output Cout(j) is output to the preceding and succeeding stages ST(j-1) and ST(j+1).

A scan start signal STV is applied to the first stage, ST1, instead of the previous gate output. If the clock signal CLK1 is applied to the clock terminal CK1 of the j-th stage ST(j), and the clock signal CLK2 is applied to its clock terminal CK2, the (j-1)th stage adjacent to the j-th stage ST(j) and The clock terminal CK1 of the (j+1)th stages ST(j-1) and ST(j+1) is supplied with the clock signal CLK2, and the clock terminal CK2 thereof is supplied with the clock signal CLK1. When the clock signals CLK1 and CLK2 have a high voltage level, each of the clock signals CLK1 and CLK2 can preferably be the same as the gate-on voltage Von, and when the clock signals CLK1 and CLK2 have a low voltage level, each clock Both signals CLK1 and CLK2 may preferably be the same as the gate-off voltage Voff, so that it can drive the switching element Q of the pixel. As shown in FIG. 6, each of the clock signals CLK1 and CLK2 may have a duty ratio of 50%, and a phase difference between the two clock signals CLK1 and CLK2 may be 180°.

Referring to FIG. 5, each stage (eg, jth stage) of a gate driver 400 according to an exemplary embodiment of the present invention includes a plurality of NMOS transistors T1-T10 and capacitors C1-C3. However, it should be understood that PMOS transistors may be used instead of NMOS transistors. Also, capacitors C1-C3 may be parasitic capacitances between gate and drain/source, which may form during build-up.

The transistor T1 is connected between the clock terminal CK1 and the output terminal OUT1, and has a control terminal connected to the node J1. The transistor T2 has an input terminal and a control terminal commonly connected to the input terminal S, and has an output terminal connected to the node J1. Transistors T3 and T4 are connected in parallel between node J1 and gate voltage terminal GV. The transistor T3 has a control terminal connected to the reset terminal R, and the transistor T4 has a control terminal connected to the node J2. Transistors T5 and T6 are connected in parallel between the output terminal OUT1 and the gate voltage terminal GV. Transistor T5 has a control terminal connected to node J2, and transistor T6 has a control terminal connected to clock terminal CK2. The transistor T7 is connected between the node J2 and the gate voltage terminal GV, and has a control terminal connected to the node J1. The transistor T8 is connected between the clock terminal CK1 and the output terminal OUT2, and has a control terminal connected to the node J1. The transistors T9 and T10 are connected in parallel between the output terminal OUT2 and the gate voltage terminal GV. The transistor T9 has a control terminal connected to the clock terminal CK2, and the transistor T10 has a control terminal connected to the node J2.

The capacitor C1 is connected between the clock terminal CK1 and the node J2, the capacitor C2 is connected between the node J1 and the output terminal OUT1, and the capacitor C3 is connected between the node J1 and the output terminal OUT2.

The operation of the stage constructed according to the above will be described below taking the jth stage STj as an example. For the sake of illustration, it will be assumed that the voltages corresponding to the high-level clock signals CLK1 and CLK2 are high voltages, and the voltages corresponding to the low-level clock signals CLK1 and CLK2 are the same as the gate-off voltage Voff, wherein the gate-off voltage Voff cut-off voltage will be referred to as low voltage. If the clock signal CLK2 and the previous gate output Gout(j-1) are high, then the transistors T2, T6 and T9 are turned on. Transistor T2 delivers the high voltage to node J1, turning on transistor T7. Transistors T6 and T9 deliver the low voltage to output terminals OUT1 and OUT2, respectively. Transistor T7 delivers a low voltage to node J2 when turned on. The transistors T1 and T8 are then turned on, so the clock signal CLK1 is output to the output terminals OUT1 and OUT2. At this time, since the clock signal CLK1 is low, the gate output Gout(j) and the carry output Cout(j) become low. Meanwhile, the capacitor C1 is not charged because the voltages across it are the same, and the capacitors C2 and C3 are charged to a voltage corresponding to the difference between the high and low voltages. At this time, since the clock signal CLK1 and the subsequent carry output Cout(j+1) are low and the node J2 is also low, the transistors T3, T4, T5 and T10 to which their control terminals are connected remain off.

Thereafter, if the clock signal CLK2 and the previous carry output Cout(j-1) become low voltages, the transistors T6 and T9 and the transistor T2 are turned off. Consequently, the two capacitors C2 and C3 , each having one terminal connected to node J2 , are floating, and transistors T1 and T8 therefore remain switched on. At this time, the clock signal CLK1 becomes high, and the two output terminals OUT1 and OUT2 become high, and the potential of the node J1 increases as much as the high voltage through the capacitors C2 and C3. It has been shown in FIG. 6 that the potential of the node J1 is the same as before. But actually, the potential increases as much as the high voltage.

At this time, since the subsequent carry output Cout(j+1) and node J2 are low, transistors T5, T6, T9 and T10 also remain off. Therefore, the two output terminals OUT1 and OUT2 are only connected to the clock signal CLK1 and isolated from the low voltage. Therefore, the two output terminals OUT1 and OUT2 output a high voltage. On the other hand, the capacitor C1 is charged to a voltage corresponding to the potential difference between both ends.

Thereafter, if the subsequent carry output Cout(j+1) and the clock signal CLK2 become high, and the clock signal CLK1 becomes low, the transistor T3 turns off and transmits a low voltage to the node J1. Therefore, the transistor T7 whose control terminal is connected to the node J1 is turned off, and the capacitor C1 becomes floating. Also, the node J2 remains at a low voltage (ie, the previous voltage). At this time, since the clock signal CLK1 is low, the voltage across the capacitor C1 becomes 0V.

At the same time, since the transistors T1 and T8 are turned off, the connection of the two output terminals OUT1 and OUT2 to the clock signal CLK1 is disconnected, and since the transistors T6 and T9 are turned on, the two output terminals OUT1 and OUT2 are connected to a low voltage, thereby output low voltage. Thereafter, if the clock signal CLK1 becomes high, when the voltage at one end of the capacitor C1 shifts to a high voltage, the voltage at the other end of the capacitor C1 (ie, node J2 ) shifts to a high voltage. Therefore, the voltage across the capacitor C1 is maintained at 0V. Therefore, both transistors T1 and T8 remain off since transistor T4 is on and delivering a low voltage to node J1 . Also, since the two transistors T5 and T10 are turned on and transmit the low voltage to the two output terminals OUT1 and OUT2, respectively, the output terminals OUT1 and OUT2 continue to output the low voltage.

Then, the voltage of the node J1 remains at a low voltage until the previous carry output Cout(j−1) becomes high. The voltage of the node J2 is synchronized with the clock signal CLK1 due to the capacitor C1, and is changed accordingly. Therefore, when the clock signal CLK1 is high and the clock signal CLK2 is low, the output terminals OUT1 and OUT2 are connected to a low voltage through the transistors T5 and T10, and when the clock signal CLK1 is low and the clock signal CLK2 is high, the output terminals OUT1 and OUT2 is connected to a low voltage through transistors T6 and T9. In this way, each stage 410L and 410R generates a gate output Gout ( j).

Returning to FIG. 4 , the gate driver 400L on the left and the gate driver 400R on the right are symmetrical to each other. Each stage 410L of the gate driver 400L on the left side is connected to the same gate line G ₁ -G _j+1 as each stage 410R of the gate driver 400R on the right side. For example, it can be seen that if the third gate line _G3 and the (j+1)th gate line Gj ₊₁ are disconnected as shown in FIG. Signal. Therefore, an additional step of repairing the gate lines G ₁ -G _n (ie, using laser repair) is not required. Because of this, although more gate lines G ₁ -G _n are disconnected than the number of repair lines (for example, all gate lines G ₁ -G _n are disconnected), they can all be repaired. Therefore, time and cost required for repair are saved, and productivity is improved. Also, where a material other than glass (for example, plastic) is used to form the substrate, it is often inconvenient to use laser radiation for repair. An embodiment of the present invention can solve this problem.

A display device according to another exemplary embodiment of the present invention will be described in detail below with reference to FIGS. 7 and 8 . 7 is a block diagram of a gate driver according to another exemplary embodiment of the present invention, and FIG. 8 is a view illustrating an example of repairing the gate driver in the block diagram shown in FIG. 7 . The gate drivers 400L and 400R shown in FIG. 7 are substantially the same as the gate drivers 400L and 400R shown in FIG. 4 . In other words, the gate drivers 400L and 400R are located on the left and right sides, respectively, and are shift registers respectively including a plurality of stages 410L and 410R connected to the gate lines G ₁ -G _n . A scan start signal STV, a plurality of clock signals CLK1 and CLK2 , and a gate-off voltage Voff are applied to the gate drivers 400L and 400R, respectively. However, the scan start signal STV is not input to the sub gate driver 400R located on the right side, which is different from the gate drivers 400L and 400R shown in FIG. 4 . The switch unit SW is disposed in each gate line G ₁ -G _n close to the sub-gate driver 400R.

A method of repairing a faulty stage such as the jth stage STj will be described in detail below with reference to FIG. 8 . For better understanding and ease of description, the scan start signal STV, the clock signals CLK1 and CLK2, and the gate off voltage Voff are not shown. Also, in FIG. 7, a portion cut by laser radiation is indicated by "x" LC, and a portion shortened by laser radiation is indicated by "triangle" LS. The main gate driver 400L on the left side and the sub gate driver 400R on the right side are symmetrical to each other. Each stage 410L of the main gate driver 400L and each stage 410R of the gate driver 400R opposite to the stage 410L are connected to the same gate line G _j-2 -G _j+2 . As described above, the switching unit SW is disposed close to the sub gate driver 400R. The switching unit SW is kept off during normal operation and can be turned on when appropriate. Additional control signals for the operation of the switching unit SW may be applied. Unlike the above description, the gate lines G ₁ -G _n between the main gate driver 400L and the sub gate driver 400R may be formed in an off state, and may be connected by using a necessary part of laser irradiation. Each stage ST(j-2)-ST(j+2) includes a first terminal line TL ₁ connected between the switch unit SW and the output terminal OUT1, a second terminal line TL ₂ connected to the output terminal OUT2, and Connected to the second terminal line TL ₂ and also to the signal lines SL _j-1 , SL _j and SL _j+1 of the previous and subsequent stages, respectively.

At this time, the switch unit SW located on the (j-1)th gate line G _j-1 and the switch unit SW located on the j-th gate line G _j are turned on, and the (j-1)th gate driver 400R from the sub-gate driver 400R The terminal lines _TL1 and TL2 extended by the output terminals OUT1 and _OUT2 of the stage ST(j-1) are cut off, and the signal line SL _j-1 and the gate line G _j-1 are shortened. Accordingly, the gate output Gout(j-1) is input to the j-th stage STj of the sub-gate driver 400R, and thus operates the stage STj. In a similar manner, the terminal lines _TL1 and _TL2 extending from the output terminals OUT1 and OUT2 of the jth stage STj of the main gate driver 400L may be cut off, and the signal line SLj and the gate line _Gj may be shortened. If so, the gate output Gout(j) generated from the j-th stage STj of the sub-gate driver 400L is respectively input to the reset terminal R of the (j-1)-th stage ST(j-1) of the main gate driver 400L And the insertion terminal S of the (j+1)th stage ST(j+1). Meanwhile, since the terminal line _TL2 connected to the output terminal OUT2 of the sub gate driver 400R is cut off, the carry output Cout(j) is not input to the terminal line _TL2 . Therefore, subsequent stages including the (j+1)th stage ST(j+1) are not run.

As mentioned above, the gate drivers 400L, 400R generate the same output and are connected to the gate lines G ₁ -G _n on the left and right sides of the display panel. Therefore, the disconnected gate lines G ₁ -G _n may be repaired without using a laser. Also, the switching unit SW is included in the main gate driver 400L and the sub gate driver 400R, so a failure occurring in the stage 410L of the main gate driver 400L can be easily repaired. While the invention has been described in connection with what is presently believed to be practicable exemplary embodiments, it should be understood that the invention is not limited to the disclosed embodiments, but rather the invention is to be covered within the spirit and scope of the appended claims Various modifications and equivalent constructions are included.

Claims (16)

1. display device comprises:

The a plurality of pixels that comprise on-off element respectively;

Be connected to the gate line of on-off element; And

Comprise a plurality of grades first and second gate drivers respectively, these level interconnection also produce output signal continuously,

Wherein the respective stages of the first grid driver level and second grid driver is connected to identical gate line and produces identical output.

2. display device as claimed in claim 1, the level that wherein is connected to first and second gate drivers of identical gate line produces output simultaneously.

3. display device as claimed in claim 2, wherein each level all comprises set terminal, reset terminal, grid voltage end, first and second output terminals and first and second clock end.

4. display device as claimed in claim 3, wherein each level all comprises:

Comprise first end that is connected to first clock end, first on-off element that is connected to second end of first node and is connected to the 3rd end of first output terminal;

Comprise first and second ends that are connected to set terminal jointly and the second switch element that is connected to the 3rd end of first node;

Comprise first end that is connected to first node, the 3rd on-off element that is connected to second end of reset terminal and is connected to the 3rd end of gate off voltage end;

Comprise first end that is connected to first node, the 4th on-off element that is connected to second end of Section Point and is connected to the 3rd end of gate off voltage end;

Comprise first end that is connected to first output terminal, the 5th on-off element that is connected to second end of Section Point and is connected to the 3rd end of gate off voltage end;

Comprise first end that is connected to first output terminal, the 6th on-off element that is connected to second end of second clock end and is connected to the 3rd end of gate off voltage end;

Comprise first end that is connected to Section Point, the minion pass element that is connected to second end of first node and is connected to the 3rd end of gate off voltage end;

Comprise first end that is connected to first clock end, the octavo pass element that is connected to second end of first node and is connected to the 3rd end of second output terminal;

Comprise first end that is connected to second output terminal, the 9th on-off element that is connected to second end of second clock end and is connected to the 3rd end of gate off voltage end;

Comprise first end that is connected to second output terminal, the tenth on-off element that is connected to second end of Section Point and is connected to the 3rd end of gate off voltage end;

First capacitor, it is connected between first clock end and the Section Point;

Second capacitor, it is connected between the first node and first output terminal; And

The 3rd capacitor, it is connected between the first node and second output terminal.

5. display device as claimed in claim 4, wherein first to the tenth on-off element is made by amorphous silicon.

6. display device as claimed in claim 5 also comprises:

The display board unit that comprises pixel and signal wire,

Wherein first and second gate drivers are integrated in the display board unit.

7. display device as claimed in claim 6 also comprises the drive circuit chip that is installed in the display board unit.

8. display device as claimed in claim 7 also comprises:

Be connected to the data line of pixel;

Produce data voltage and data voltage is applied to the data driver of data line; And

Generation is used for the signal controller of the control signal of control gate driver and data driver.

9. display device as claimed in claim 8, wherein drive circuit chip comprises data driver and signal controller.

10. display device as claimed in claim 9, wherein display device is a LCD.

11. a display device comprises:

The a plurality of pixels that comprise on-off element respectively;

Be connected respectively to the gate line of on-off element;

The first grid driver that comprises a plurality of first order, these a plurality of first order interconnection also produce output signal continuously; And

Comprise a plurality of partial second grid drivers, this a plurality of second level interconnection also produces output signal continuously,

Wherein the corresponding second level of the first grid driver first order and second grid driver is connected to identical gate line and produces identical output, and wherein on-off element is between them.

12. as the display device of claim 11, be can not produce under the situation of failure level of output in any first order wherein, the second level that is connected to this failure level by identical gate line produces output.

13. as the display device of claim 12, wherein be connected to the on-off element of the gate line between this failure level and the second level, and be connected to this gate line before the on-off element of gate line connect simultaneously.

14. as the display device of claim 13, wherein:

Each first and second grades all comprise first and second end lines, and are connected to second end line and before and the signal wire of each grade afterwards; And first and second end lines of this failure level disconnect, and the part of first end line of this failure level is shorted to signal wire, disconnect with first and second end lines of level before this failure level is connected to identical gate line partial, and be shorted to signal wire with the part of first end line of level before this failure level is connected to identical gate line partial.

15., wherein be connected to partial second end line disconnection of identical gate line with failure level as the display device of claim 14.

16. as the display device of claim 11, wherein display device is a LCD.

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