KR20060002142A - Device Separating Method of Semiconductor Device - Google Patents

Abstract

The present invention discloses a method of forming a device isolation film of a semiconductor device capable of increasing a channel width of an active region. The present invention discloses a method of forming a pad oxide film and a pad nitride film on a silicon substrate; Etching the pad nitride film and the pad oxide film and exposing a substrate portion corresponding to an isolation region; Etching the exposed substrate portion to form a trench; Forming a rounding oxide film on the trench surface; Forming an HDP oxide layer on the rounded oxide layer and the pad nitride layer to fill the trench; CMPing the surface of the HDP oxide layer to expose the pad nitride layer; Removing the pad nitride layer to expose the pad oxide layer; And CMP the surfaces of the HDP oxide film and the pad oxide film to increase the width of the active region.

Description

METHODS FOR FORMING ELEMENT ISOLATION LAYER OF SEMICONDUCTOR DEVICE

1A through 1E are cross-sectional views illustrating processes of forming a device isolation film using a conventional shallow trench isolation (STI) process.

2A to 2E are cross-sectional views of processes for describing a method of forming a device isolation film according to an embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

21 silicon substrate 22 pad oxide film

23: pad nitride film 24: trench

25: rounding oxide film 26: HDP oxide film

26a: device isolation layer 27: gate oxide film

28 polysilicon film 29 tungsten silicide film

The present invention relates to a method of forming a device isolation film of a semiconductor device, and more particularly, to a method of forming a device isolation film of a semiconductor device capable of increasing a channel width of an active region.

With the progress of semiconductor technology, the speed and integration of semiconductor devices have been rapidly progressing. As a result, the demand for miniaturization of patterns and high precision of pattern dimensions is increasing.

This requirement applies not only to patterns formed in device regions, but also to device isolation films that occupy a relatively large area. This is because the width of the device region must decrease in order to increase the width of the device region in the trend that the width of the device region is decreasing toward the highly integrated device.

Here, a conventional device isolation film has been formed by a LOCOS process. As is well known, a bird's-beak having a beak shape is generated at an edge portion of the device isolation film by the locus process. Therefore, there is a disadvantage in that leakage current is generated while increasing the area of the device isolation layer.

Accordingly, a method of forming a device isolation layer using a shallow trench isolation (STI) process having a small width and excellent device isolation characteristics instead of the method of forming a device isolation layer by the locus process has been proposed. The device isolation film is formed by applying an STI process.

A method of forming a device isolation film applying the STI process will be described below with reference to FIGS. 1A to 1E.

1A through 1E are cross-sectional views illustrating processes of forming a device isolation layer using a conventional STI process.                         

As shown in FIG. 1A, the pad oxide film 2, the pad nitride film 3, and the photoresist pattern 4 defining the device isolation region are sequentially formed on the silicon substrate 1.

As shown in FIG. 1B, the exposed portion of the pad nitride film 3 is etched using the photoresist pattern 4 as an etching mask, and then the pad oxide film portion 2 and the semiconductor substrate 1 portion beneath it are etched. Overetch sequentially to form the trench 5 in the semiconductor substrate 1.

As shown in FIG. 1C, after forming the trench etch, an oxide film 6 is formed on the surface of the trench 5, and then an HDP oxide film 7 is formed to fill the trench on the trench surface and the pad nitride film.

As shown in FIG. 1D, the surface of the HDP oxide layer 7 is CMP so that the pad nitride layer 3 is exposed, and the pad nitride layer 3 is removed by wet etching using an H 3 PO 4 solution. Subsequently, the pad oxide layer 2 is removed by wet etching using an HF or BOE solution to form the device isolation layer 7a.

As shown in FIG. 1E, a gate oxide film 8, a polysilicon film 9, and a tungsten silicide film 10 are formed after an ion implantation process for forming a gate on a substrate including the device isolation film 7a. do.

However, the trench gap fill capability of the cell where the cell is formed due to the reduction of the design rule in the device of 0.1 μm or less shows a limitation in the existing equipment. The width is continually decreasing.

In addition, as shown in FIG. 1D, the pad oxide layer is removed through wet etching, and the substrate is exposed. In this case, the exposed substrate region becomes the active region A. FIG. In addition, as shown in FIG. 1E, the active region A is formed into the channel width A ′ of the cell transistor by a subsequent process, and eventually the cell transistors are formed due to the decrease in the width of the active region A. FIG. It causes a serious problem of reducing the required channel width.

Accordingly, an object of the present invention is to provide a method for forming a device isolation layer of a semiconductor device capable of increasing the channel width of a cell transistor by increasing the channel width of an active region. .

The present invention for achieving the above object, the step of sequentially forming a pad oxide film and a pad nitride film on a silicon substrate; Etching the pad nitride film and the pad oxide film and exposing a substrate portion corresponding to an isolation region; Etching the exposed substrate portion to form a trench; Forming a rounding oxide film on the trench surface; Forming an HDP oxide layer on the rounded oxide layer and the pad nitride layer to fill the trench; CMPing the surface of the HDP oxide layer to expose the pad nitride layer; Removing the pad nitride layer to expose the pad oxide layer; And CMP the surfaces of the HDP oxide film and the pad oxide film to increase the width of the active region.

Here, forming a rounding oxide film on the trench surface includes forming a liner nitride film on the rounding oxide film.

The forming of the trench may be performed such that an angle between the substrate and the trench is in the range of 95 to 105 °.

CMPing the surfaces of the HDP oxide film and the pad oxide film removes the substrate in the active region by about 100 to 500 Å to expose the substrate.

(Example)

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2A to 2E are cross-sectional views of processes for describing a method of forming a device isolation film according to an embodiment of the present invention.

As shown in FIG. 2A, a pad oxide film 22, a pad nitride film 23, and a photoresist pattern (not shown) defining an isolation region are sequentially formed on the silicon substrate 21. Subsequently, the exposed portion of the pad nitride layer 23 is etched using the photoresist pattern as an etch mask, and then the over-etched portion of the pad oxide layer 22 and the portion of the semiconductor substrate 21 are sequentially etched to sequentially expose the semiconductor substrate 21. To form a trench 24. At this time, the trench 24 is formed to have a range of 95 to 105 degrees with the substrate.

As shown in FIG. 2B, after forming the trench etch, a rounding oxide process is performed to form a rounding oxide layer 25 on the trench 24 surface. Next, the HDP oxide layer 26 is formed on the rounded oxide layer 25 and the pad nitride layer 23 to fill the trench.                     

As shown in FIG. 2C, the surface of the HDP oxide layer 26 is CMP to expose the pad nitride layer 23. Subsequently, the pad nitride layer 3 is removed by wet etching using a H 3 PO 4 solution. At this time, "B" is the first active area.

As shown in FIG. 2D, the surface of the pad oxide film including the HDP oxide film is CMP to expose the substrate portion, thereby forming the device isolation layer 26a. At this time, the substrate of the active region is removed by about 100 to 500 mV using a CMP process.

Here, " B '" is an active region formed after CMP the surface of the pad oxide film including the HDP oxide film, and this active region B' is the channel width of the cell transistor by a subsequent process, as shown in Fig. 2E. (C) is formed.

In addition, the channel width B 'is considerably larger than the active area B first formed in FIG. 2C, and the width of the active area B' may be increased without improving the gap fill capability of the HDP oxide film. Can be. As a result, the channel width C of the cell transistor is increased, and the threshold voltage, the leakage current, and the refresh characteristics of the cell transistor can be improved, and thus the yield of the semiconductor device can be improved.

As shown in FIG. 2E, after the ion implantation process is performed to form a gate on the substrate including the device isolation layer 26a, the gate oxide layer 27, the polysilicon layer 28, and the tungsten silicide layer 29 are formed. Form.

In the present invention, only a round oxide is formed on the trench surface, but a liner nitride may be formed on the round oxide surface.

In the above, the present invention has been described with reference to some examples, but the present invention is not limited thereto, and a person of ordinary skill in the art may make many modifications and variations without departing from the spirit of the present invention. I will understand.

As described above, according to the present invention, after the CMP of the HDP oxide surface is removed, the pad nitride film is removed by wet etching, and then the CMP of the HDP oxide film and the pad oxide film is exposed so that the substrate is exposed, without improving the gap fill capability of the HDP oxide film. The width of the active area can be increased. As a result, the channel width of the cell transistor is increased, and the threshold voltage, leakage current, and refresh characteristics of the cell transistor can be improved.

Therefore, the yield of the device can be improved by improving the electrical characteristics of the device.

Claims (4)

Sequentially forming a pad oxide film and a pad nitride film on the silicon substrate; Etching the pad nitride film and the pad oxide film and exposing a substrate portion corresponding to an isolation region; Etching the exposed substrate portion to form a trench; Forming a rounding oxide film on the trench surface; Forming an HDP oxide layer on the rounded oxide layer and the pad nitride layer to fill the trench; CMPing the surface of the HDP oxide layer to expose the pad nitride layer; Removing the pad nitride layer to expose the pad oxide layer; And And CMP the surfaces of the HDP oxide film and the pad oxide film to increase the width of the active region. The method of claim 1, wherein the forming of the rounding oxide layer on the trench surface comprises forming a liner nitride layer on the rounding oxide layer. The method of claim 1, wherein the forming of the trench is performed such that angles of the substrate and the trench are in a range of 95 ° to 105 °. 2. The method of claim 1, wherein the CMP of the surfaces of the HDP oxide film and the pad oxide film removes about 100 to 500 microseconds of the active region substrate so that the substrate is exposed.

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