JP2000323564A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To form a plurality of element isolation grooves which differ in the width of isolation and depth of isolation within a semiconductor substrate, without using microloading effect or sharp increase in number of processes. SOLUTION: This manufacturing method of a semiconductor device for forming a first element isolation groove 22, which has a first width of isolation and a second element isolation groove 24 having a second width of isolation larger than the first width of isolation, within a semiconductor substrate 10. At this time, a mask corresponding to the first and second widths of isolation is made on the semiconductor substrate 10, and using this mask, the first and second element isolating grooves 22 and 24 are etched into the semiconductor substrate 10 until the depths of isolation substantially become the same and then are subjected to heat treatment so that the depth of the isolation of the first element isolation groove 22 is shallower than the depth of the isolating of the second element isolation groove 24.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming element isolation grooves having different isolation widths and isolation depths in a semiconductor substrate formed based on fine design rules. More particularly, the present invention relates to a method for manufacturing a semiconductor device suitable for the present invention.

[0002]

2. Description of the Related Art As semiconductor devices such as flash memories are miniaturized, it is necessary to electrically isolate a large number of transistor elements formed in the semiconductor device. As this electrical isolation method, LOCOS (Local) for selectively oxidizing the surface of a semiconductor substrate in an element isolation region has been conventionally used.
Oxidation of Silicon) technology has been employed.

However, in the LOCOS method, a bird's beak is generated by isotropically oxidizing not only in the depth direction but also in the width direction of the semiconductor substrate, so that an unnecessary spread occurs in the isolation region. With miniaturization of semiconductor devices, useless space on chips due to bird's beaks cannot be ignored.

Therefore, in order to reduce the area occupied by the inter-element isolation region, an element isolation groove (trench) is formed in the semiconductor substrate, and a trench isolation in which a dielectric material such as a silicon oxide film is embedded in the element isolation groove. Technology has come to the fore.

Here, a conventional manufacturing method for manufacturing a semiconductor device (flash memory) using this trench isolation technique will be described with reference to FIGS. 4 (a) to 4 (c).

First, as shown in FIG. 4A, a silicon oxide film 56 is formed on a silicon substrate 50 by thermal oxidation.
Further, a silicon nitride film 58 is deposited thereon by a CVD method. Here, the silicon substrate 50 is divided into a memory cell formation region 52 and a peripheral circuit region 54.

Next, as shown in FIG. 4B, a photoresist 60 is applied, and patterning for forming an element isolation groove is performed in a photolithography (PR) process. The portions of the silicon nitride film 58 and the silicon oxide film 56 are removed by etching.

Next, as shown in FIG. 4C, after the photoresist 60 is stripped, the silicon substrate 50 is etched using the remaining silicon nitride film 58 and silicon oxide film 56 as a mask to form a first device. Separation groove 62 (in the figure, as an example,
(Two isolation grooves are shown) and a second element isolation groove 64 are formed.

FIG. 5 shows a plan view at this stage, and a cross-sectional view taken along the line BB 'in FIG. 5 corresponds to FIG. As shown in FIG. 5, the first isolation trench 62 is formed in the memory cell region 52, and the second isolation trench 64 is formed in the peripheral circuit region 54.

After that, a silicon oxide film is buried in the first and second element isolation trenches, and a CMP (Chemical
A flattening process is performed by Mechanical Polishing, and a silicon nitride film 58 and a silicon oxide film 56 are formed.
Is removed, element isolation (trench isolation) is performed.

In the semiconductor device thus manufactured,
The depth of the groove is defined between the first isolation groove 62 having a small isolation width formed in the memory cell region 52 and the second isolation groove 64 having a large isolation width formed in the peripheral circuit region 54. Are the same. Such a semiconductor device (flash memory)
Then, there are the following problems.

If the depth of the element isolation groove is too large, the first element isolation groove 62 in the memory cell region 52 having a small isolation width will have a large aspect ratio between the groove depth and the isolation width, and the bottom portion of the groove will be reduced. In addition, defects due to heat treatment in a later step are likely to occur, and a junction leak occurs, which causes a failure.

However, if the isolation trench depth is too shallow, a high voltage (about 15 to 20 V) is applied to the source / drain (SD) region 84 of the transistor in the peripheral circuit region 54 as shown in FIG. 2, the distance between the high-concentration impurity region 86 and the SD region 84, which is formed at the depth of the bottom of the element isolation groove 64 and is necessary for electrical isolation, becomes too close to ensure the junction breakdown voltage. Become.

For this reason, it is difficult to manufacture a flash memory using a trench element isolation capable of securing a junction breakdown voltage of a transistor in the peripheral circuit region 54 while suppressing a junction leak in the memory cell region 52. there were.

Therefore, there has been a need for a method of manufacturing a semiconductor device in which the isolation trench having a small isolation width is made shallow and the isolation trench having a large isolation width is made deep without greatly increasing the number of steps. One example of such a manufacturing method is disclosed in Japanese Patent Application Laid-Open No. 9-26048.
No. 5.

In this prior art, a plurality of element isolation grooves (trench) having different isolation widths and isolation depths are simultaneously formed in a semiconductor substrate by a single etching step. Specifically, in the process of forming the plurality of isolation trenches, the opening width of the shallow isolation trench is set to be smaller than the opening width of the deep isolation trench, and a microloading effect occurs in the shallow isolation trench. Is adopted.

Here, the microloading effect is
As is well known, this is a phenomenon in which the etching rate decreases in a structure in which the opening width of the etching mask is small and the aspect ratio of the opening of the film to be etched including this etching mask is large. This microloading effect occurs when the aspect ratio is about 3 or more.

[0018]

As described above, the above prior art uses the microloading effect at the time of etching a silicon substrate, and is used only when the aspect ratio of a narrow isolation trench is about 3 or more. It was a problem because I could not do it.

Therefore, the present invention has been made in view of the above-mentioned problems of the prior art, and an object of the present invention is to provide a semiconductor device having a plurality of element isolation trenches having different isolation widths and isolation depths. Is to provide a method for manufacturing a semiconductor device which can be formed without using a microloading effect and without a significant increase in the number of steps.

[0020]

In order to achieve the above object, according to the present invention, a first element isolation groove having a first isolation width and a second element isolation groove having a first isolation width larger than the first isolation width are formed in a semiconductor substrate. In the method of manufacturing a semiconductor device for forming a second element isolation groove having an isolation width of, a mask corresponding to the first and second isolation widths is formed on a semiconductor substrate, and using this mask, The first and second isolation trenches are etched in the semiconductor substrate until the isolation depths are substantially the same, and then the isolation depth of the first isolation trench is reduced to the second isolation depth. The heat treatment is performed so as to be shallower than the separation depth of the separation groove.

Preferably, the etching is performed under such a condition that the taper angle at the narrowest portion of the first element isolation groove is in the range of about 70 to 80 degrees.

In this case, the portion having the narrowest separation width is as follows:
This is the bottom of the first isolation groove.

Preferably, the etching is performed under the condition that the aspect ratio of the first element isolation groove is 1.5 or more and the aspect ratio of the second element isolation groove is 1 or less.

In this case, it is preferable that the aspect ratio of the first element isolation groove is less than about 3.

Preferably, the heat treatment is performed after the pretreatment with hydrofluoric acid.

The heat treatment is performed, for example, in a hydrogen atmosphere.

The heat treatment may be performed in a halogen gas atmosphere.

The heat treatment may be performed in an atmosphere of a mixed gas of hydrogen and a halogen gas.

Further, the heat treatment may be performed in an atmosphere of a mixed gas of hydrogen and a halogen compound.

The heat treatment is performed so as to round the bottom of the first element isolation groove which has been sharpened at the time of etching.

Here, the semiconductor device is a flash memory, the first element isolation groove is formed in a memory cell area, and the second element isolation groove is formed in a peripheral circuit area.

The mask is formed by forming a silicon oxide film on a semiconductor substrate and forming a silicon nitride film thereon,
A photoresist is applied on the entire surface, and then patterned by a photolithography process, and then the silicon oxide film and the silicon nitride film are removed based on the patterned resist pattern.

Further, the first groove having a different groove depth due to the heat treatment.
After forming the first and second isolation trenches, the first and second isolation trenches are formed.
After the silicon oxide film is buried in the element isolation trench and a planarization process is performed, the mask is removed.

[0034]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) A method of manufacturing a semiconductor device (for example, a flash memory) in which an isolation trench having a small isolation width is made shallow and an isolation trench having a large isolation width is made deeper. Will be described with reference to FIGS.

First, as shown in FIG. 1A, a silicon oxide film 16 is formed on a silicon substrate 10 by thermal oxidation.
Further, a silicon nitride film 18 is formed thereon by CVD (Che).
The deposition is performed by a physical vapor deposition (Metal Vapor Deposition) method. Here, the silicon substrate 10 is divided into a memory cell region 12 and a peripheral circuit region 14.

Next, as shown in FIG. 1B, a photoresist 20 is applied, and patterning of the element isolation groove is performed in a photolithography (PR) process. The nitride film 18 and the silicon oxide film 16 are removed by etching.

Next, as shown in FIG. 1C, after the photoresist 20 is removed, the silicon substrate 10 is etched using the remaining silicon nitride film 18 and silicon oxide film 16 as a mask, and the first element is etched. Separation groove 22 (in the figure, as an example, 2
And two second isolation grooves 24 are formed. Here, the first element isolation groove 22 is formed in the memory cell region 12, and the second element isolation groove is formed in the peripheral circuit region 14.

The etching condition at this time is such that the taper angle at the narrowest separation width is 70 to 80 degrees, like the first element isolation groove 22 in the memory cell region 12.

At this time, the depth of the groove is determined by the first element isolation groove 22 having a small isolation width in the memory cell region 12 and having an aspect ratio of 1.5 or more in the first isolation groove 22 and a second isolation groove having a large isolation width in the peripheral circuit region 14. The element isolation groove 24 is set so that the aspect ratio becomes 1 or less.

For example, the isolation width of the first element isolation groove 22 in the memory cell region 12 is 0.2 μm and the second element isolation groove 22 in the peripheral circuit region 14 is
The isolation width of the element isolation groove 24 is 0.4 μm and the silicon substrate 10
The groove depth immediately after the etching is set to 0.3 μm.

Here, the taper angle and the aspect ratio will be described with reference to FIG.

FIG. 2 shows a first element isolation groove 22 formed in the memory cell region 12. The taper angle at the narrowest portion of the first element isolation groove 22 indicates the taper angle at the bottom of the isolation groove 22 in the illustrated example. The aspect ratio is represented by a ratio between a separation width and a separation depth, as shown in the figure.

Returning to FIG. 1, as shown in FIG. 1 (d), after performing a pretreatment with hydrofluoric acid, a heat treatment at about 950 ° C. in a hydrogen atmosphere at a pressure of about 100 Torr is performed. Do this for about a second. As a result, the silicon on the surface moves, and the first isolation groove in the memory cell region 12 having a small isolation width.
22 becomes shallower. At this time, if the groove depth immediately after the etching of the silicon substrate 10 is, for example, 0.3 μm,
By the high-temperature hydrogen treatment, the depth of the first element isolation groove 22 in the memory cell region 12 becomes 0.25 to 0.28 μm.

After the pretreatment with hydrofluoric acid, the movement of silicon on the surface by heat treatment in a hydrogen atmosphere is more likely to occur as the surface energy increases. That is, the silicon on the surface moves in a high-temperature hydrogen atmosphere such that the surface energy of the silicon on the surface is stabilized at the lowest level.

As described above, immediately after the etching, the aspect ratio between the groove depth and the isolation width of the element isolation groove 22 becomes 1.5 or more, and the taper angle of the etching of the silicon substrate becomes 7 or more.
0-80 degrees. When etching is performed under such conditions, an acute angle is formed at the bottom of the element isolation groove 22. In such a state, the bottom is rounded and the groove depth is shallow to stabilize the surface energy.

Here, FIG. 3 shows a plan view at this stage, and a cross-sectional view taken along the line AA ′ corresponds to FIG.
As shown in FIG. 3, the first element isolation groove 22 is
The second element isolation trench 2 formed in the memory cell region 12
4 is formed in the peripheral circuit region 14.

Thereafter, a silicon oxide film is buried in the first element isolation groove 22 and the second element isolation groove 24,
(Chemical Mechanical Poli
shing) and silicon nitride film
By removing 18 and silicon oxide film 16, element isolation is formed.

By using such a method, the first element isolation groove 22 having a small isolation width in the memory cell region 12 can be reduced in depth and the isolation width in the peripheral circuit region 14 can be reduced without greatly increasing the number of steps. The second element isolation groove 24 can be made deeper. As a result, it is possible to manufacture a flash memory using the trench element isolation in which the junction breakdown voltage of the transistor in the peripheral circuit region 14 is ensured while suppressing the junction leak in the memory cell region 12.

(Second Embodiment) In the first embodiment, a method of reducing the depth of an element isolation groove having a small isolation width by moving silicon on the surface in a high-temperature hydrogen atmosphere is described. Was. However, the same effect can be obtained in an atmosphere such as a halogen gas, a mixed gas of hydrogen and halogen, or a mixed gas of hydrogen and halogen compound.

In addition, if the taper angle of the first element isolation groove 22 in the memory cell region 12 having a small isolation width during the etching of the silicon substrate is made as small as possible, it is possible to reduce the taper angle in FIG.
Since the state shown in FIG. 1D can be changed from the state shown in FIG.
It is possible to reduce the depth of the isolation trench having a small isolation width and to increase the depth of the isolation trench having a large isolation width.

Also in this case, the bottom portion of the element isolation groove has an acute angle, and if left as it is, a defect is generated in a heat treatment in a later step and causes a defect. Is preferably rounded.

In the above embodiment, the groove depth at the time of etching is set to 1.5 or more in the first element isolation groove 22 having a small isolation width in the memory cell region 12, but the micro-loading is performed. To avoid the effect, about 3
It is preferable to set the aspect ratio below.

In the above embodiment, the semiconductor device is
Although the description has been made taking the flash memory as an example, the present invention is not limited to the flash memory, but may be a CMOS (Complete).
The present invention is also applicable to other semiconductor devices such as a central MOS.

[0054]

According to the present invention, a plurality of isolation trenches having different isolation widths and isolation depths are formed in a semiconductor substrate without using a microloading effect and without a significant increase in the number of steps. be able to.

Further, when the present invention is applied to a flash memory, it is possible to effectively secure a junction breakdown voltage of a transistor in a peripheral circuit region while suppressing a junction leak in a memory cell region.

[Brief description of the drawings]

FIGS. 1A to 1D are cross-sectional views illustrating manufacturing steps of a semiconductor device (flash memory) of the present invention.

FIG. 2 is a cross-sectional view showing an aspect ratio and a taper angle of a first element isolation groove formed in a semiconductor device (flash memory) of the present invention.

FIG. 3 is a plan view of the semiconductor device of the present invention immediately after the step shown in FIG.

FIGS. 4A to 4C are cross-sectional views illustrating a process for manufacturing a conventional semiconductor device (flash flash).

FIG. 5 is a plan view of the conventional semiconductor device immediately after the step shown in FIG.

FIG. 6 is a cross-sectional view showing a peripheral circuit region of a conventional semiconductor device (flash memory).

[Explanation of symbols]

 Reference Signs List 10 silicon substrate 12 memory cell region 14 peripheral circuit region 16 silicon oxide film 18 silicon nitride film 20 photoresist 22 first element isolation groove 24 second element isolation groove

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI theme coat ゛ (Reference) H01L 29/788 29/792 F-term (Reference) 5F001 AD53 AD60 AG28 AG31 5F032 AA35 AA39 AA44 BA02 BA03 CA17 CA20 CA23 DA02 DA22 DA24 DA53 DA74 DA78 5F043 AA02 BB27 DD02 DD15 FF01 FF07 GG05 5F083 ER22 GA24 GA27 GA28 GA30 NA01 PR05 PR12 PR21 PR33 PR38

Claims (14)

[Claims] A first isolation trench having a first isolation width and a second isolation trench having a second isolation width larger than the first isolation width are formed in the semiconductor substrate. In the method of manufacturing a semiconductor device, a mask corresponding to the first and second separation widths is formed on a semiconductor substrate, and the first and second masks are formed in the semiconductor substrate using the mask.
Is etched until the isolation depth becomes substantially the same, and then the isolation depth of the first isolation trench is smaller than the isolation depth of the second isolation trench. A method for manufacturing a semiconductor device, comprising performing heat treatment. 2. The etching method according to claim 1, wherein the taper angle at the narrowest portion of the first element isolation groove is about 70.
2. The method of manufacturing a semiconductor device according to claim 1, wherein the method is performed under a condition such that the angle falls within a range of degrees to 80 degrees. 3. The method of manufacturing a semiconductor device according to claim 2, wherein the portion having the narrowest isolation width is a bottom of the first isolation trench. 4. The method according to claim 1, wherein the etching is performed under a condition that an aspect ratio of the first isolation trench is 1.5 or more and an aspect ratio of the second isolation trench is 1 or less. Item 10. A method for manufacturing a semiconductor device according to item 1. 5. The method according to claim 4, wherein an aspect ratio of the first isolation trench is less than about 3. 6. The method according to claim 1, wherein the heat treatment is performed after a pretreatment with hydrofluoric acid is performed. 7. The method according to claim 1, wherein the heat treatment is performed in a hydrogen atmosphere. 8. The method according to claim 1, wherein the heat treatment is performed in a halogen gas atmosphere. 9. The method according to claim 1, wherein the heat treatment is performed in an atmosphere of a mixed gas of hydrogen and a halogen gas. 10. The method according to claim 1, wherein the heat treatment is performed in an atmosphere of a mixed gas of hydrogen and a halogen compound. 11. The method of manufacturing a semiconductor device according to claim 1, wherein the heat treatment is performed so as to round the bottom of the first element isolation groove that has become an acute angle during etching. 12. The semiconductor device according to claim 1, wherein the semiconductor device is a flash memory, wherein the first isolation trench is formed in a memory cell region, and the second isolation trench is formed in a peripheral circuit region. Item 10. A method for manufacturing a semiconductor device according to item 1. 13. The mask is formed by forming a silicon oxide film on a semiconductor substrate, forming a silicon nitride film on the silicon oxide film, applying a photoresist on the entire surface, and then performing patterning by a photolithography process. 2. The method according to claim 1, wherein the silicon oxide film and the silicon nitride film are formed by removing the silicon oxide film and the silicon nitride film based on the patterned resist pattern. 14. The method according to claim 1, further comprising, after forming first and second element isolation grooves having different groove depths by heat treatment, burying a silicon oxide film in the first and second element isolation grooves. And a step of removing the mask after performing a planarization process.