KR20030090412A - Semiconductor device realizing shallow junction by using gate sidewall oxide as gate oxide and fabricating method thereof - Google Patents

Abstract

PURPOSE: A semiconductor device of a shallow junction using a gate sidewall oxide layer as a gate oxide and a fabricating method therefor are provided to repeatedly form a source/drain of a shallow junction and improve an electrical characteristic of the semiconductor device by using the gate oxide and silicon epitaxy without an additional junction ion implantation. CONSTITUTION: An insulation layer pattern(110), a doped polysilicon pattern(120) and a capping layer(130) are sequentially stacked on the active region of a silicon substrate(105) to form a gate. The sidewall of the doped polysilicon pattern is thermally oxidized to form a vertical gate oxide. High density impurity-doped silicon epitaxially grows on the active region outside the gate and the gate oxide to form a source/drain(150,155). A gate spacer(160) surrounds the sidewall of the doped polysilicon pattern and the capping layer outside the gate oxide. A vertical overlap(157) is formed between the source/drain and the gate.

Description

Semiconductor device realizing shallow junction by using gate sidewall oxide as gate oxide and manufacturing method thereof

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device such as a MOSFET and a method of manufacturing the same, and more particularly, to a semiconductor device having a source / drain having a shallow junction depth and a method of manufacturing the same.

1 shows a conventional MOSFET formed on a silicon substrate 5. Referring to FIG. 1, the role of the source 10 / drain 20 is to connect an inversion channel formed by the gate 30 with an external terminal to flow a current. In order to perform the role, an overlap of a certain length is required between the source 10 / the drain 20 and the gate 30 as shown by reference numeral 40. If the source / drain and the gate do not overlap, no current flows through the circuit open. Such a device using a deep junction becomes smaller in size and drains the source 10 and drain. Punchthrough (50) occurred between (20). A shallow junction has been proposed to prevent punchthrough, which is formed using ion implantation.

In shallow junctions, however, defects formed by ion implantation in subsequent heat treatment processes promote diffusion of ion atoms to expand the source / drain junction region. As a result, the separation distance from the adjacent junction becomes narrow, resulting in generation of a leakage current. In addition, when the low energy ion implantation method is used, the depth of the junction becomes shallow, but there is a problem in that the contact resistance increases due to an increase in diffusion at the surface. In addition, due to an increase in the parasitic resistance of the source and drain, there is a problem that the device current drops sharply. Because of this, there is a difficulty in actively implementing sufficiently shallow junctions.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a semiconductor device having a sufficiently shallow junction by preventing an increase in parasitic resistance.

Another object of the present invention is to provide a method of manufacturing a semiconductor device to achieve a sufficiently shallow junction by preventing an increase in parasitic resistance.

1 illustrates a conventional MOSFET.

2 to 5 are cross-sectional views illustrating a semiconductor device and a method of manufacturing the same according to a first embodiment of the present invention.

6 is a cross-sectional view for describing a semiconductor device and a method of manufacturing the same according to the second embodiment of the present invention.

7 to 9 are cross-sectional views illustrating a semiconductor device and a method of manufacturing the same according to a third embodiment of the present invention.

10 is a cross-sectional view for describing a semiconductor device and a method of manufacturing the same according to a fourth embodiment of the present invention.

11 to 13 are graphs comparing ET (Electrical Test) data of a DRAM cell transistor according to an embodiment of the present invention and a normal structure DRAM cell transistor according to the prior art.

14 is a result of simulating a change in current intensity according to a thickness of a gate oxide of a gate sidewall in a DRAM cell transistor according to an exemplary embodiment of the present invention.

* Description of the symbols for the main parts of the drawings *

105: silicon substrate, 110: insulating film pattern,

120: doped polysilicon pattern, 130: capping layer,

140a: gate oxide, 145: nitride film spacer,

150, 180: source, 155, 185: drain,

160: gate spacer,

157, 187: overlap between source / drain and gate,

170 and 175: undoped silicon epitaxial layer

In accordance with another aspect of the present invention, a semiconductor device includes a gate formed by stacking an insulating layer pattern, a doped polysilicon pattern, and a capping layer on an active region of a silicon substrate, and a sidewall of the doped polysilicon pattern. It includes a vertical gate oxide formed by thermal oxidation. On the active region outside the gate and the gate oxide, a source / drain formed by epitaxially growing silicon doped with a high concentration of impurities is provided. A gate spacer surrounds the sidewalls of the doped polysilicon pattern and capping layer outside the gate oxide.

An undoped silicon epitaxial layer may be further included between the source / drain and the silicon substrate. The semiconductor device may further include a nitride spacer covering the gate oxide between the gate oxide and the source / drain.

In the semiconductor device of the present invention, a thermal oxide film formed on the sidewall of a doped polysilicon pattern used as a gate electrode is used as a gate oxide, and silicon, which is heavily doped with impurities and grown epitaxially, is used as a source / drain. The drain-gate overlap is a vertical change from what was previously horizontal to the silicon substrate.

In the method of manufacturing a semiconductor device according to the present invention for achieving the above technical problem, a gate is formed by stacking an insulating film pattern, a doped polysilicon pattern and a capping layer on an active region of a silicon substrate, and then the doped polysilicon Oxides are formed by thermally oxidizing the sidewalls of the pattern and the surface of the silicon substrate. The oxide is anisotropically etched to reveal the surface of the silicon substrate, thereby forming a vertical gate oxide on the sidewalls of the doped polysilicon pattern. Source / drain is formed by epitaxially growing silicon doped with a high concentration of impurity on active regions outside the gate and gate oxide, and then anisotropically etches an insulating film on the resultant material on which the source / drain is formed to form the source / drain. A gate spacer is formed to surround the sidewalls of the doped polysilicon pattern and the capping layer.

After forming the gate oxide, the method may further include epitaxially growing undoped silicon on the gate and the active region outside the gate oxide. After the forming of the gate spacer, the method may further include heat treating a resultant product on which the gate spacer is formed.

In particular, after the forming of the vertical gate oxide, forming a nitride spacer covering the gate oxide by anisotropic etching and covering the nitride film on the resultant product on which the gate oxide is formed, and cleaning the resultant product on which the nitride film spacer is formed. Further performing the step of eliminating, the step of subsequently epitaxially growing a high concentration of impurity doped silicon to form a source / drain is effectively performed.

According to the present invention, there is an advantage that the ion implantation process conventionally used to form the source / drain is omitted, it is easier to make a shallow junction, there is little parasitic resistance in the shallow junction, subsequent contact pad formation The contact resistance can be significantly improved in the process.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, embodiments of the present invention may be modified in many different forms, and the scope of the present invention should not be construed as being limited to the embodiments described below.

(First embodiment)

2 to 5 are cross-sectional views illustrating a semiconductor device and a method of manufacturing the same according to a first embodiment of the present invention. Hereinafter, the manufacturing method will be described with reference to FIGS. 2 to 5.

First, as shown in FIG. 2, an isolation layer (not shown) is formed on the silicon substrate 105 to define an active region and an inactive region, and then an insulating layer is formed. For example, the silicon substrate 105 is thermally oxidized to form an oxide film. Next, doped polysilicon is deposited, and an insulating material for capping is deposited to protect the doped polysilicon. Doped polysilicon may be formed at a temperature of 500 ° C. to 700 ° C. by LPCVD. After depositing polysilicon without doping the dopant, arsenic (As) or phosphorus (P) may be doped by ion implantation to have conductivity, and doping the dopant in-situ during deposition. It can also be deposited in the doped polysilicon state. As the insulating material for capping, silicon nitride may be deposited.

By patterning the capping insulating material, the doped polysilicon, and the insulating layer in sequence using a gate mask, a gate including the capping layer 130, the doped polysilicon pattern 120, and the insulating layer pattern 110 is formed on the active region. Form. Subsequently, the oxide 140 is formed by thermally oxidizing the sidewall of the doped polysilicon pattern 120 and the surface of the silicon substrate 105. By thermal oxidation, the effect of removing damage caused during gate patterning and removing residual polysilicon residues can also be obtained.

Next, as shown in FIG. 3, the oxide 140 is anisotropically etched to expose the surface of the silicon substrate 105 to form a vertical gate oxide 140a on the sidewall of the doped polysilicon pattern 120. Dry etching may be used as the anisotropic etching. The thickness of the gate oxide 140a may be 0.5 to 1.5 times the thickness of the insulating layer pattern 110. For example, the thickness of the gate oxide 140a may be 10 kPa to 100 kPa.

Referring to FIG. 4, a source / drain, which is conventionally formed by ion implantation, is formed by silicon epitaxy doped with high concentration impurity. The thickness grown by epitaxy may be 50 kPa to 1000 kPa. Since the silicon substrate 105 is grown as a base, a source 150 / drain 155 region is formed on an active region outside the gate and gate oxide 140a, and an overlap between the source / drain and the gate ( 157 is formed vertically. Instead of using ion implantation for the source / drain, it is formed of highly doped impurity-doped silicon to prevent an increase in parasitic resistance.

Next, as shown in FIG. 5, the gate spacer 160 is formed on the sidewall of the gate. First, the insulating film is covered on the resultant of FIG. 4, and the spacer is etched or etched back to surround the doped polysilicon pattern 120 and the capping layer 130 outside the gate oxide 140a. Next, when the heat treatment is performed, each of the bonding surfaces 150a and 155a of the source 150 / drain 155 region may be slightly inserted into the silicon substrate 105. In subsequent processes, contact pads may be formed in contact with the source 150 and drain 155 regions, respectively.

The semiconductor device formed by the above method includes a gate formed by stacking an insulating layer pattern 110, a doped polysilicon pattern 120, and a capping layer 130 on an active region of a silicon substrate 105, and a doping layer. It includes a vertical gate oxide (140a) formed by thermally oxidizing the side wall of the polysilicon pattern 120. On the active region outside the gate and gate oxide 140a, a source 150 / drain 155 formed by epitaxially growing highly doped impurity silicon is provided. The gate spacer 160 surrounds sidewalls of the doped polysilicon pattern 120 and the capping layer 130 outside the gate oxide 140a. Source 150 / drain 155 and gate-overlap 157 are vertical. That is, the structure according to the present invention is characterized in that it includes a vertically overlapped source / drain (hereinafter referred to as "VOD").

According to the above embodiments, a shallow junction implementation is realized by using a gate oxide and silicon epitaxy, not an ion implantation method, and no additional junction ion implantation is required. Therefore, there is an advantage that the ion implantation used to form a junction conventionally is omitted, and a shallow junction can be made more easily. The parasitic resistance is reduced, resulting in a sufficiently shallow junction.

(2nd Example)

6 is a cross-sectional view for describing a semiconductor device and a method of manufacturing the same according to the second embodiment of the present invention. In FIG. 6, the same reference numerals as in the above-described drawings indicate the same members, and repeated descriptions thereof will be omitted.

First, as described with reference to FIGS. 2 and 3, a gate is formed by stacking an insulating layer pattern 110, a doped polysilicon pattern 120, and a capping layer 130 on an active region of the silicon substrate 105. After thermally oxidizing the sidewall of the doped polysilicon pattern 120, the silicon substrate 105 is exposed to form a vertical gate oxide 140a on the sidewall of the doped polysilicon pattern 120.

Next, as shown in FIG. 6, silicon is epitaxially grown on the active region outside the gate and gate oxide 140a without impurity doping to form undoped silicon epitaxial layers 170 and 175. The thickness of the undoped silicon epitaxial layers 170 and 175 may be 50 kPa to 1000 kPa.

Next, high concentration impurity doped silicon epitaxy is performed to form source 150 / drain 155 on the active region outside the gate and gate oxide 140a. The thickness grown by epitaxy may be 50 kPa to 1000 kPa. Accordingly, the overlap 187 between the source / drain and the gate is vertically formed. That is, VOD is implemented.

Next, the gate spacer 160 is formed to surround the doped polysilicon pattern 120 and the capping layer 130 outside the gate oxide 140a. Heat treatment may allow each junction surface 180a, 185a of the source 150 / drain 155 to enter the undoped silicon epitaxial layers 170, 175 slightly.

(Third Embodiment)

7 to 9 are cross-sectional views illustrating a semiconductor device and a method of manufacturing the same according to a third embodiment of the present invention. 7 to 9, the same reference numerals as in the above-described drawings indicate the same members, and repeated descriptions thereof will be omitted.

First, as described with reference to FIGS. 2 and 3, a gate is formed by stacking an insulating layer pattern 110, a doped polysilicon pattern 120, and a capping layer 130 on an active region of the silicon substrate 105. After thermally oxidizing the sidewall of the doped polysilicon pattern 120, the silicon substrate 105 is exposed to form a vertical gate oxide 140a on the sidewall of the doped polysilicon pattern 120.

Next, referring to FIG. 7, a nitride film spacer 145 covering the gate oxide 140a is formed by covering the nitride film and anisotropically etching the resultant material on which the gate oxide 140a is formed. In this case, the sum of the thicknesses of the gate oxide 140a and the nitride film spacer 145 may be 0.5 to 1.5 times the thickness of the insulating film pattern 110. For example, the sum of the thicknesses of the gate oxide 140a and the nitride film spacer 145 may be 10 kPa to 100 kPa. Next, the resultant in which the nitride film spacers 145 are formed is washed to remove the oxide film remaining on the semiconductor substrate 105.

However, after thermally oxidizing the sidewalls of the doped polysilicon pattern 120, the nitride film may be covered and anisotropically etched to form the gate oxide 140a and the nitride film spacer 145, and then the resultant may be cleaned.

8, a source / drain, which was conventionally formed by ion implantation, is formed by high concentration impurity doped silicon epitaxy. The thickness grown by epitaxy may be 50 kPa to 1000 kPa. Since the silicon substrate 105 is grown as a base, the source 150 / drain 155 region is formed on the active region outside the gate and the gate oxide 140a. Since the overlap 157 between the source / drain and the gate is formed vertically, VOD is implemented.

In the step described with reference to FIG. 7, since epitaxy is performed after the remaining oxide film is removed through the cleaning process, a good quality single crystal film may be formed. In the above embodiments, it is preferable to perform a cleaning process for removing an oxide film in order to form a good quality single crystal film. However, when wet cleaning using a cleaning solution is performed while the gate oxide 140a is exposed, the gate oxide ( 140a) may be severely damaged. In this embodiment, the nitride film spacer 145 protects the gate oxide 140a.

9, a gate spacer 160 is formed on sidewalls of the gate. First, the insulating film is covered on the resultant of FIG. 8, and the spacer is etched or etched back to form the gate spacer 160 to surround the polysilicon pattern 120 and the capping layer 130 doped outside the gate oxide 140a. Next, when the heat treatment is performed, each of the bonding surfaces 150a and 155a of the source 150 / drain 155 region may be slightly inserted into the silicon substrate 105. In subsequent processes, contact pads may be formed in contact with the source 150 and drain 155 regions, respectively.

The semiconductor device formed by the above method includes a gate formed by stacking an insulating layer pattern 110, a doped polysilicon pattern 120, and a capping layer 130 on an active region of a silicon substrate 105, and a doping layer. It includes a vertical gate oxide (140a) formed by thermally oxidizing the side wall of the polysilicon pattern 120. Also, a nitride film spacer 145 covering the gate oxide 140a is included. On the active region outside the gate and gate oxide 140a, a source 150 / drain 155 formed by epitaxially growing highly doped impurity silicon is provided. The gate spacer 160 surrounds sidewalls of the doped polysilicon pattern 120 and the capping layer 130 outside the gate oxide 140a. That is, the nitride film spacer 145 and the gate spacer 160 are dually formed on the sidewall of the gate and have a VOD.

(Example 4)

10 is a cross-sectional view for describing a semiconductor device and a method of manufacturing the same according to a fourth embodiment of the present invention. In FIG. 10, the same reference numerals as in the above-described drawings indicate the same members, and repeated descriptions thereof will be omitted.

This embodiment is a method for combining the second embodiment and the third embodiment, which will be easily understood by those skilled in the art from the above descriptions. That is, after forming the nitride spacer 145 on the sidewalls of the gate, silicon is epitaxially grown on the active region without impurity doping to form the undoped silicon epitaxial layers 170 and 175, and the heavily doped impurity doped silicon. Epitaxy is performed to form the source 150 / drain 155.

According to the present exemplary embodiment, the nitride film spacer 145 and the gate spacer 160 are formed on the sidewalls of the gate, and the VOD is formed, and the bonding surfaces 180a and 185a are formed in the undoped silicon epitaxial layers 170 and 175. It is characterized by having

Experimental Example

The characteristics of the VOD structure semiconductor device of the present invention as shown in FIGS. 5, 6, 9, and 10 were compared with the normal structure through the device simulators Tsuprem and Medici. As a result of simulation, the improvement of punch-through between source / drain due to shallow junction and improvement of saturation current (Idsat) due to parasitic resistance are confirmed. It is assumed that the thickness of the insulating film between the gate and the semiconductor substrate in each element (it is simply an insulating film pattern in the structure of the present invention, but functions as a gate insulating film in the normal structure) is 50 kV. The thickness of the insulating film on the gate sidewall (corresponding to the gate oxide and / or nitride spacer in the structure of the present invention, and the gate sidewall oxide film in the normal structure) is 50 kV in the case of the structure of the present invention, and the normal value (usually greater than 50 kV in the case of the normal structure) Is assumed to be).

1) Source / drain potential comparison at drain-to-source voltage (Vds) = 10V

It was found that the structure of the present invention prevents the punch-through from the normal structure to Vds = 10V, so that the potential of the drain is transferred to the source.

2) Source-drain Punchthrough Current Flow Comparison at Vds = 10V

In the normal structure, severe punch-through current flows at Vds = 10V, but the punch-through current is confirmed in the structure of the present invention.

3) Identify the role of gate sidewall oxide as gate oxide in the structure of the present invention.

From the electric field and current flow diagrams under Vds = 2.2V and gate-to-source voltage (Vgs) = 2.2V, the gate sidewall oxide acts as a vertical gate oxide, and the heavily doped silicon epitaxial layer acts as a source / drain. It was confirmed that.

4) ET (Electrical Test) data comparison (simulating DRAM cell transistors as an example)

Threshold voltage Vth is set to 1.1V in both the normal structure and the structure of the present invention. Referring to FIG. 11, the x axis of the graph is a gate voltage Vgate and the left y axis is a drain-source current Ids. The right y-axis is the maximum conductance (Gm). As shown in FIG. 11, Ids (◆) according to the structure of the present invention was higher than Ids (▲) according to the normal structure. In addition, it can be seen that the structure of the present invention exhibits excellent Gm (■) characteristics due to the reduction of parasitic resistance. Gm (×) according to the normal structure was lower than the Gm (■) of the present invention.

Referring to Fig. 12, the x-axis is Vds when Vgs = 2.2V, and the y-axis is Ids. 12, Ids (◆) according to the structure of the present invention is higher than Ids (■) according to the normal structure, which is seen as a result of the reduction of parasitic resistance. It can be seen that Idsat increases by about 30% in the structure of the present invention.

Referring to FIG. 13, the x-axis is Vds, and the y-axis is a leakage current Idoff at stand-by time of the transistor. The BV (■) of the normal structure shows a punchthrough phenomenon at Vds = 6V, but the Idoff (◆) of the present invention shows that there is no punchthrough even at Vds = 10V in the structure according to the present invention.

5) Saturation Current According to Gate Oxide Thickness

A structure easily confused with the VOD structure according to the present invention is a raised source / drain structure in which selective epitaxial growth (SEG) is applied to the source / drain. The difference between the VOD structure and the conventional raised source / drain structure according to the present invention is firstly that the present structure overlaps vertically without the need of source / drain ion implantation to overlap the gate after gate formation, and the raised structure is gated. The ion implantation may be performed after formation, or the source / drain may be diffused and overlapped by an excessive thermal process after realizing the raised structure and ion implantation process.

Second, the thickness difference between the insulating film on the gate sidewall (corresponding to the gate oxide and / or nitride spacer in the structure of the present invention, and the gate sidewall oxide film in the normal structure). In this structure, in order that the gate electric field is transferred to the source / drain, the thickness of the gate oxide and / or nitride spacer is operated at the thickness of the insulating film pattern, and when it is larger, the Idsat reduction is very severe. As can be seen from the simulation results of FIG. 14, the current decreases as the gate oxide thickness of the gate sidewall increases in the order of 50 mA, 80 mA, and 150 mA under Vgs = 2.2V.

Although the embodiments of the present invention have been described above, the present invention is not limited to the above embodiments, and various changes and modifications are possible. The invention includes alternatives, modifications and equivalents that may be included within the spirit and scope of the invention as defined by the appended claims.

According to the present invention described above, it is an advantage that the shallow junction is implemented by the gate oxide and the silicon epitaxy, not the ion implantation method, and no additional junction ion implantation is required. Simulation of the source-drain breakdown voltage improvement, which is the advantage of shallow junctions, can be confirmed. The reduction of the parasitic resistance increases the saturation current (Idsat), and the highly doped silicon epitaxial layer can significantly reduce the contact resistance in subsequent contact pad formation. A source / drain having a shallow junction depth can be formed reproducibly, and can be advantageously applied to high integration of a semiconductor device as well as to improve electrical characteristics of the semiconductor device.

Claims (20)

A gate formed by stacking an insulating layer pattern, a doped polysilicon pattern, and a capping layer on the active region of the silicon substrate; A vertical gate oxide formed by thermally oxidizing sidewalls of the doped polysilicon pattern; A source / drain formed by epitaxially growing silicon doped with a high concentration of impurities on the active region outside the gate and gate oxide; And And a gate spacer surrounding a sidewall of the doped polysilicon pattern and a capping layer outside the gate oxide, such that a vertical overlap is formed between the source / drain and the gate. The semiconductor device of claim 1, further comprising an undoped silicon epitaxial layer between the source / drain and the silicon substrate. The semiconductor device of claim 1, wherein the gate oxide has a thickness of 0.5 to 1.5 times the thickness of the insulating film pattern. The semiconductor device according to claim 1 or 2, wherein the gate oxide has a thickness of 10 GPa to 100 GPa. The semiconductor device of claim 1, further comprising a nitride spacer covering the gate oxide between the gate oxide and the source / drain. The semiconductor device of claim 5, wherein the sum of the thicknesses of the gate oxide and the nitride film spacer is 0.5 to 1.5 times the thickness of the insulating film pattern. 6. The semiconductor device of claim 5, wherein the sum of the thicknesses of the gate oxide and the nitride film spacer is in the range of 10 GPa to 100 GPa. The semiconductor device according to claim 1, wherein the epitaxially grown silicon having a high concentration of impurity doped silicon to form the source / drain is 50 mW to 1000 mW. The semiconductor device according to claim 2, wherein the epitaxially grown silicon having a high concentration of impurity doped silicon to form the source / drain is 50 kPa to 1000 kPa, and the thickness of the undoped silicon epitaxial layer is 50 kPa to 1000 kPa. . The semiconductor device of claim 2, wherein a source / drain junction surface is formed in the undoped silicon epitaxial layer. Stacking an insulating film pattern, a doped polysilicon pattern, and a capping layer on the active region of the silicon substrate to form a gate; Thermally oxidizing a sidewall of the doped polysilicon pattern and a surface of the silicon substrate to form an oxide; Anisotropically etching the oxide to reveal a surface of the silicon substrate, thereby forming a vertical gate oxide on the sidewalls of the doped polysilicon pattern; Epitaxially growing heavily doped silicon on the active region outside the gate and gate oxide to form a source / drain; And Covering the insulating film on the resultant source / drain formation and anisotropically etching to form a gate spacer outside the gate oxide to surround the sidewalls of the doped polysilicon pattern and the capping layer, thereby forming a gate spacer between the source / drain and the gate. A semiconductor device manufacturing method having a vertical overlap (overlap) is formed. 12. The method of claim 11, further comprising epitaxially growing non-doped silicon on the active region outside the gate and gate oxide after forming the gate oxide. The method of claim 11, further comprising, after forming the gate spacer, heat treating a resultant product on which the gate spacer is formed. The method of claim 11 or 12, wherein after forming the vertical gate oxide, Forming a nitride film spacer covering the gate oxide by anisotropically etching the nitride film on the resultant product on which the gate oxide is formed; And And removing the remaining oxide film by cleaning the resultant material on which the nitride film spacer is formed. The method of claim 14, wherein the sum of the thicknesses of the gate oxide and the nitride film spacer is 0.5 to 1.5 times the thickness of the insulating film pattern. 15. The method of claim 14, wherein the sum of the gate oxide and the nitride spacer is 10 kPa to 100 kPa. The method of claim 11 or 12, wherein the gate oxide has a thickness of 0.5 to 1.5 times the thickness of the insulating film pattern. The method according to claim 11 or 12, wherein the gate oxide has a thickness of 10 kPa to 100 kPa. 12. The method of claim 11, wherein the epitaxially grown silicon having a high concentration of impurity doped to form the source / drain is 50 mW to 1000 mW. 13. The method of claim 12, wherein the epitaxially grown silicon having a high concentration of impurity doped silicon to form the source / drain is 50 kPa to 1000 kPa, and the thickness of the undoped silicon epitaxial layer is 50 kPa to 1000 kPa. Semiconductor device manufacturing method.