CN111162074B - Semiconductor structure and method of forming the same - Google Patents

Abstract

A semiconductor structure and a method for forming the same, the forming method includes: forming a base, the base includes a PMOS region, the base includes a substrate and a semiconductor pillar protruding from the substrate, the semiconductor pillar in the PMOS region includes a first semiconductor pillar and a semiconductor pillar located in the first semiconductor In the second semiconductor column on the column, the molar volume percentage of Ge in the second semiconductor column is greater than the molar volume percentage of Ge in the first semiconductor column; a PMOS drain region is formed in the bottom of the first semiconductor column in the PMOS region; after the PMOS drain region is formed , forming a gate structure surrounding the semiconductor column, the gate structure of the PMOS region covers the junction of the first semiconductor column and the second semiconductor column and exposes the top of the second semiconductor column, and the semiconductor column covered by the gate structure serves as the channel layer ; After the gate structure is formed, a PMOS source region is formed in the top of the second semiconductor pillar. The embodiments of the present invention are beneficial to improve the stability of the PMOS transistor, such as the hot carrier effect and the self-heating effect.

Description

Semiconductor structure and method of forming the same

technical field

The present invention relates to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for forming the same.

Background technique

With the rapid development of semiconductor manufacturing technology, semiconductor devices are developing in the direction of higher component density and higher integration, and the development trend of semiconductor process nodes following Moore's Law is decreasing. As the most basic semiconductor device, transistors are currently being widely used. Therefore, with the increase in the component density and integration of semiconductor devices, in order to adapt to the reduction of process nodes, the channel length of transistors must be continuously shortened.

The shortening of the transistor channel length has the benefit of increasing the die density of the chip, increasing the switching speed, etc. However, with the shortening of the channel length, the distance between the source and the drain of the transistor is also shortened, and the gate's ability to control the channel becomes worse, resulting in the phenomenon of subthreshold leakage, the so-called short channel. Effects (short-channel effects, SCE) are more likely to occur, and the channel leakage current of the transistor increases.

Therefore, in order to better meet the requirement of scaling down the device size, the semiconductor process gradually begins to transition from planar transistors to three-dimensional transistors with higher power efficiency, such as gate-all-around (GAA) transistors . In a fully surrounding gate transistor, the gate surrounds the area where the channel is located. Compared with a planar transistor, the gate of a fully surrounding gate transistor has stronger control over the channel and can better suppress short-channel effects. . All-around gate transistors include lateral gate-all-around (LGAA) transistors and vertical gate-all-around (VGAA) transistors, wherein the channel of VGAA is perpendicular to the lining. Extending in the direction of the bottom surface is beneficial to improve the area utilization efficiency of the semiconductor structure, and thus is beneficial to achieve further feature size reduction.

SUMMARY OF THE INVENTION

The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, so as to optimize the performance of the semiconductor device.

To solve the above problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: forming a substrate including a PMOS region, the substrate including a substrate and a semiconductor pillar protruding from the substrate, and the PMOS region has The semiconductor pillar includes a first semiconductor pillar and a second semiconductor pillar located on the first semiconductor pillar, the mole percentage of Ge in the second semiconductor pillar is greater than the mole percentage of Ge in the first semiconductor pillar; in the PMOS A PMOS drain region is formed in the bottom of the first semiconductor pillar; after the PMOS drain region is formed, a gate structure surrounding the semiconductor pillar is formed, and the gate structure of the PMOS region covers the first semiconductor pillar and the second semiconductor pillar. At the junction of the semiconductor pillars and exposing the top of the second semiconductor pillar, the semiconductor pillar covered by the gate structure serves as a channel layer; after the gate structure is formed, on the top of the second semiconductor pillar A PMOS source region is formed within.

Correspondingly, an embodiment of the present invention further provides a semiconductor structure, comprising: a base, the base includes a PMOS region, the base includes a substrate and a semiconductor pillar protruding from the substrate, the semiconductor pillar of the PMOS region comprising a first semiconductor column and a second semiconductor column located on the first semiconductor column, the mole percentage of Ge in the second semiconductor column is greater than the mole percentage of Ge in the first semiconductor column; the PMOS drain region is located in the the bottom of the first semiconductor pillar in the PMOS region; a gate structure surrounding the semiconductor pillar, the gate structure covering the junction of the first semiconductor pillar and the second semiconductor pillar and exposing the top of the second semiconductor pillar , the semiconductor pillar covered by the gate structure serves as a channel layer; the PMOS source region is located in the top of the second semiconductor pillar.

Compared with the prior art, the technical solutions of the embodiments of the present invention have the following advantages:

In the embodiment of the present invention, the semiconductor pillar of the PMOS region includes a first semiconductor pillar and a second semiconductor pillar located on the first semiconductor pillar, and the mole percentage of Ge in the second semiconductor pillar is greater than the mole percentage of Ge in the first semiconductor pillar After the channel layer is subsequently formed in the semiconductor pillar, the PMOS drain region is formed in the bottom of the first semiconductor pillar in the PMOS region, and the PMOS source region is formed in the top of the second semiconductor pillar, the PMOS region is close to the source region The mole percentage of Ge in the channel layer is greater than the mole percentage of Ge in the channel layer near the drain region. In the semiconductor field, the voltage of the PMOS drain region is usually higher than that of the source region, so the electric field in the channel layer near the drain region is stronger. , by making the molar percentage of Ge in the channel layer of the PMOS region close to the source region higher, it is beneficial to improve the mobility of carriers in the channel layer of the PMOS transistor close to the source region, thereby improving the electrical performance of the PMOS transistor; The molar percentage of Ge in the channel layer of the PMOS region close to the drain region is lower, which is beneficial to make the mobility of carriers in the channel layer of the PMOS region close to the drain region lower, thereby helping to improve the PMOS transistor close to the drain region. The stability problems such as Hot Carrier Effect (HCI) and Self-Heating Effect (SHE) of the channel layer of the channel layer are improved, thereby improving the electrical performance of the semiconductor structure.

Description of drawings

1 is a schematic structural diagram of a semiconductor structure;

2 is a schematic structural diagram of another semiconductor structure;

3 to 9 are schematic structural diagrams corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention.

Detailed ways

Semiconductor devices still suffer from poor performance. The reasons for the poor performance of the device are now analyzed by combining the two semiconductor structures.

Referring to FIG. 1, a schematic structural diagram of a semiconductor structure is shown.

The semiconductor structure includes: a base including a PMOS region I, the base including a substrate 10 and a semiconductor pillar 15 protruding from the substrate 10 , the material of the semiconductor pillar 15 in the PMOS region I is Si; a drain region 11 , located in the bottom of the semiconductor pillar 15 ; the gate structure 16 surrounds the semiconductor pillar 15 , the gate structure 16 covers the semiconductor pillar 15 and exposes the top of the semiconductor pillar 15 , the semiconductor covered by the gate structure 16 The pillar 15 serves as the channel layer 12 ; the source region 13 is located in the top of the semiconductor pillar 15 .

The material of the PMOS region I semiconductor pillar 15 is Si, and the material of the PMOS region I channel layer 12 is correspondingly Si, so the carrier mobility of the PMOS transistor channel layer 12 is relatively low, and accordingly, The PMOS transistor has a low probability of occurrence of stability problems such as hot carrier effect and self-heating effect, but the low carrier mobility of the PMOS transistor channel layer 12 may easily lead to poor performance of the PMOS transistor.

Referring to FIG. 2, a schematic structural diagram of another semiconductor structure is shown.

The semiconductor structure is the same as the semiconductor structure in FIG. 1 and will not be repeated here. The difference between the semiconductor structure and the semiconductor structure in FIG. 1 is that the material of the semiconductor column 25 in the PMOS region I is SiGe.

Correspondingly, the material of the I-channel layer 22 in the PMOS region is also SiGe, and the SiGe material can provide tensile stress to the channel layer 22 of the PMOS transistor, so the carrier mobility of the channel layer 22 of the PMOS transistor is high. In the semiconductor field, the voltage of the PMOS drain region 23 is usually higher than that of the source region 21, so the electric field in the channel layer 22 near the drain region 23 is stronger, and the carrier mobility in the channel layer 22 near the drain region 23 of the PMOS transistor is Higher, it is easy to cause stability problems such as hot carrier effect and self-heating effect in the channel layer 22 close to the drain region 23 of the PMOS transistor, thereby reducing the electrical performance of the semiconductor structure.

In order to solve the technical problem, in the embodiment of the present invention, the semiconductor pillar of the PMOS region includes a first semiconductor pillar and a second semiconductor pillar located on the first semiconductor pillar, and the mole percentage of Ge in the second semiconductor pillar is greater than that of the first semiconductor pillar. Molar percentage of Ge in a semiconductor pillar, after forming a channel layer in the semiconductor pillar, forming a PMOS drain region in the bottom of the first semiconductor pillar in the PMOS region, and forming a PMOS source region in the top of the second semiconductor pillar, The mole percentage of Ge in the channel layer near the source region of the PMOS region is greater than the mole percentage of Ge in the bottom of the channel layer near the drain region. In the semiconductor field, the voltage of the PMOS drain region is usually higher than the source region, so it is close to the drain region. The electric field in the channel layer of the PMOS region is stronger, and by making the mole percentage of Ge in the channel layer of the PMOS region close to the source region higher, it is beneficial to improve the mobility of carriers in the channel layer of the PMOS transistor close to the source region, Thereby, the electrical performance of the PMOS transistor is improved; by making the mole percentage of Ge in the channel layer of the PMOS region close to the drain region lower, it is beneficial to make the mobility of carriers in the channel layer of the PMOS region close to the drain region lower, Therefore, it is beneficial to improve the stability problems such as the hot carrier effect and the self-heating effect of the channel layer of the PMOS transistor close to the drain region, thereby improving the electrical performance of the semiconductor structure.

In order to make the above objects, features and advantages of the embodiments of the present invention more clearly understood, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

3 to 9 are schematic structural diagrams corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention.

Referring to FIGS. 3 to 5 , a base is formed, including the PMOS region I, the base includes a substrate 112 (as shown in FIG. 5 ) and a semiconductor pillar 120 (as shown in FIG. 5 ) protruding from the substrate 112 , The semiconductor pillar 120a of the PMOS region I includes a first semiconductor pillar 113 (as shown in FIG. 5 ) and a second semiconductor pillar 114 (as shown in FIG. 5 ) on the first semiconductor pillar 113 (as shown in FIG. 5 ). The mole percentage of Ge in the semiconductor pillars 114 is greater than the mole percentage of Ge in the first semiconductor pillars 113 .

By making the mole percentage of Ge in the second semiconductor pillar 114 larger than the mole percentage of Ge in the first semiconductor pillar 113 , a channel layer is subsequently formed in the semiconductor pillar 120 and the first semiconductor pillar 113 in the PMOS region I is formed. After the PMOS drain region is formed in the bottom of the second semiconductor pillar 114 and the PMOS source region is formed in the top of the second semiconductor pillar 114, the mole percentage of Ge in the channel layer near the source region of the PMOS region I is greater than the mole percentage of Ge in the channel layer near the drain region. In the semiconductor field, the voltage of the PMOS drain region is usually higher than that of the source region, so the electric field is stronger in the channel layer near the drain region, by making the PMOS region I The mole percentage of Ge in the channel layer near the source region is higher , it is beneficial to improve the mobility of the carriers in the channel layer of the PMOS transistor close to the source region; by making the mole percentage of Ge in the channel layer of the PMOS region I close to the drain region lower, it is beneficial to make the PMOS region I close to the drain region. The mobility of the carriers in the channel layer is low, which is beneficial to improve the stability problems such as the hot carrier effect and the self-heating effect of the channel layer near the drain region of the PMOS transistor.

The base of the PMOS region I is used to form PMOS transistors.

It should be noted that, in this embodiment, the substrate further includes an NMOS region II, and the substrate of the NMOS region II is used to form an NMOS transistor.

The substrate 112 provides a process platform for subsequent formation of semiconductor structures.

In this embodiment, the substrate 112 is a silicon substrate. In other embodiments, the material of the substrate may also be germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate may also be a silicon-on-insulator substrate or germanium-on-insulator substrate.

The semiconductor pillars 120 are used to form drain regions, source regions and channel layers.

The first semiconductor pillars 113 are used to form drain regions and channel layers of PMOS and NMOS.

In this embodiment, the first semiconductor pillars 113 and the substrate 112 are obtained by etching the same semiconductor material layer, the first semiconductor pillars 113 and the substrate 112 are correspondingly integrated, and the materials of the substrate 112 are corresponding Also Si. In other embodiments, according to actual process requirements, the materials of the first semiconductor pillar and the substrate may be different, and in order to further improve the carrier mobility of the PMOS transistor, the material of the first semiconductor pillar may be SiGe .

In this embodiment, the first semiconductor pillar 113 is a single-layer structure. That is to say, the first semiconductor pillar 113 only includes a single semiconductor layer, which can simplify the process flow and reduce the difficulty of the process operation.

In other embodiments, the first semiconductor pillar may further include a plurality of semiconductor layers sequentially located on the substrate, and, in the first semiconductor pillar, from the distance from the second semiconductor pillar to the position close to the second semiconductor pillar direction, the mole percentage of Ge in the semiconductor layer gradually increases, therefore, the mole percentage of Ge in the first semiconductor column decreases sequentially from top to bottom, which is beneficial to further improve the hot carrier of the channel layer near the drain region of the PMOS transistor effects and self-heating effects.

The second semiconductor pillars 114 are used to form a PMOS source region and a channel layer.

The material of the second semiconductor pillar 114 is SiGe, and the SiGe material can provide compressive stress to the channel layer of the PMOS transistor, thereby helping to improve the carrier mobility of the PMOS transistor.

It should be noted that, in this embodiment, the second semiconductor column 114 includes a plurality of semiconductor layers (not shown) sequentially located on the first semiconductor column 113, and in the second semiconductor column 114, the The mole percentage of Ge in the semiconductor layer gradually increases from the direction close to the first semiconductor pillar 113 to the direction away from the first semiconductor pillar 113 . Therefore, the mole percentage of Ge in the second semiconductor pillar 114 decreases sequentially from top to bottom. There are It is beneficial to further improve the mobility of carriers in the channel layer of the PMOS transistor near the source region, and to improve the stability issues such as the hot carrier effect and the self-heating effect of the channel layer of the PMOS transistor near the drain region. In other embodiments, the second semiconductor pillar may also include only a single semiconductor layer, which is beneficial to simplify the process flow.

In this embodiment, the semiconductor pillar 120 b of the NMOS region I includes a first semiconductor pillar 113 and a third semiconductor pillar 115 located on the first semiconductor pillar 113 .

In this embodiment, the materials of the third semiconductor pillars 115 and the first semiconductor pillars 113 are the same, and the material of the third semiconductor pillars 115 is correspondingly Si. Therefore, the material of the semiconductor pillars 120b of the NMOS region II is Si. , which is not only beneficial to improve the process compatibility, but also to improve the carrier mobility of the II channel layer in the NMOS region.

Specifically, the step of forming the PMOS region I substrate includes:

Referring to FIG. 3 , a first semiconductor material layer 100 is provided, a second semiconductor material layer 110 is formed on the first semiconductor material layer 100 , and the molar percentage of Ge in the second semiconductor material layer 110 is greater than that of the first semiconductor material The mole percent of Ge in layer 100.

The first semiconductor material layer 100 is used for the subsequent formation of the substrate 112 and the first semiconductor pillars 113 .

The second semiconductor material layer 110 is used for the subsequent formation of the second semiconductor pillars 114 .

In this embodiment, the step of forming the second semiconductor material layer 110 on the first semiconductor material layer 100 includes: using an epitaxial growth process to sequentially grow a plurality of semiconductor material films on the first semiconductor material layer 100 (Fig. Not shown), the plurality of semiconductor material films serve as the second semiconductor material layers 110 .

The thin film obtained by the epitaxial growth process has high purity and few defects, and is favorable for obtaining a single crystal thin film and improving the formation quality of the second semiconductor material layer 110 .

In this embodiment, the material of the second semiconductor material layer 110 is SiGe, therefore, the gases used in the epitaxial growth process are SiH ₄ , Si ₂ H ₆ , GeH ₄ and Ge ₂ H ₆ gases. By controlling the ratios of the SiH ₄ and Si ₂ H ₆ gases and the GeH ₄ and Ge ₂ H ₆ gases, changes in the molar percentage of Ge in different semiconductor material films can be achieved during the epitaxial growth process.

It should be noted that, referring to FIG. 4 , in this embodiment, after the second semiconductor material layer 110 is formed, the forming method further includes: removing the second semiconductor material layer 110 on the NMOS region II; A third semiconductor material layer 111 is formed on the first semiconductor material layer 100 in the NMOS region II, and the material of the third semiconductor material layer 111 and the first semiconductor material layer 100 is the same.

The first semiconductor material layer 100 and the third semiconductor material layer 111 in the NMOS region II are used to form the substrate 112 and the semiconductor pillars 120b in the NMOS region II.

In this embodiment, the material of the first semiconductor material layer 100 is Si, and the material of the third semiconductor material layer 111 is correspondingly Si. After the semiconductor pillars 120b of the NMOS region II are formed subsequently, it is beneficial to improve the NMOS The carrier mobility of the transistor.

In this embodiment, a wet etching process is used to remove the second semiconductor material layer 110 on the NMOS region II.

The wet etching process has a high etching rate, and the wet etching process has a relatively high etching selection for SiGe material and Si, so it is beneficial to completely remove the second semiconductor material layer 110 of the NMOS region II, Moreover, damage to the first semiconductor material layer 100 during the process of removing the second semiconductor material layer 110 of the NMOS region II can be reduced.

In order to improve the film quality of the third semiconductor material layer 111 and obtain a single crystal film, in this example, an epitaxial growth process is used to form the third semiconductor material layer 111 on the first semiconductor material layer 100 .

5 , after the second semiconductor material layer 110 and the third semiconductor material layer 111 are formed, the second semiconductor material layer 110 and the first semiconductor material layer 100 are etched in sequence. In the PMOS region I The substrate 112 and the semiconductor pillars 120a protruding from the substrate 112 are formed thereon.

In this embodiment, the substrate further includes the NMOS region II. Therefore, in the step of etching the second semiconductor material layer 110 and the first semiconductor material layer 100, the NMOS region II is also etched in sequence. The third semiconductor material layer 111 and the first semiconductor material layer 100, a substrate 112 and a semiconductor pillar 120b protruding from the substrate 112 are formed on the NMOS region II, and the semiconductor pillar 120b in the NMOS region II includes the first A semiconductor pillar 113 and a third semiconductor pillar 115 located on the first semiconductor pillar 113 .

By forming the substrate 112 of the PMOS region I and the NMOS region II and the semiconductor pillars 120 protruding from the substrate 112 in the same step, it is beneficial to improve process compatibility and process manufacturing efficiency.

In this embodiment, a dry etching process is used to sequentially etch the second semiconductor material layer 110 and the first semiconductor material layer 100 in the PMOS region I, and the third semiconductor material layer 111 and the first semiconductor material layer 111 in the NMOS region II. A semiconductor material layer 100 forms a substrate 112 and semiconductor pillars 120 protruding from the substrate 112 .

The dry etching process has better controllability of the etching profile, which is beneficial to make the topography of the semiconductor pillar 120 and the substrate 112 meet the process requirements. In other embodiments, according to actual process requirements, a wet etching process or a combination of dry and wet processes may also be used to etch the second semiconductor material layer and the first semiconductor material layer in the PMOS region, and The third semiconductor material layer and the first semiconductor material layer of the NMOS region.

It should be noted that, in this embodiment, a buffer layer 121 (as shown in FIG. 5 ) and a hard mask located on the buffer layer 121 are further formed on the second semiconductor pillar 114 and the third semiconductor pillar 115 . Membrane layer 122 (shown in FIG. 5 ).

The hard mask layer 122 is used as an etching mask for etching the second semiconductor material layer 110 , the third semiconductor material layer 111 , and the first semiconductor material layer 111 to form the substrate 112 and the semiconductor pillar 120 . The hard mask layer 122 can also protect the tops of the semiconductor pillars 120 in subsequent processes. In this embodiment, the material of the hard mask layer 122 is silicon nitride.

The silicon nitride material is more stressed when heated, so it passes between the hard mask layer 122 and the second semiconductor pillar 114 and between the hard mask layer 122 and the third semiconductor pillar 115 The way of forming the buffer layer 121 makes the buffer layer 121 play the role of stress buffer, so as to improve the hard mask layer 122 and the second semiconductor pillars 114 , the hard mask layer 122 and the third semiconductor pillars 115 adhesion. In this embodiment, the material of the buffer layer 121 is silicon oxide.

Referring to FIG. 6, a PMOS drain region 125a is formed in the bottom of the first semiconductor pillar 113 of the PMOS region I.

In this embodiment, the mole percentage of Ge in the second semiconductor pillar 114 is greater than the mole percentage of Ge in the first semiconductor pillar 113. Therefore, after the channel layer is subsequently formed in the semiconductor pillar 120a of the PMOS region I, the The mole percentage of Ge in the channel layer of the PMOS region I close to the drain region 125a is relatively small. In the semiconductor field, the voltage of the PMOS drain region is higher and the electric field is stronger, so it is beneficial to reduce the channel of the PMOS transistor close to the drain region 125a. The carrier mobility of the layer can be reduced, thereby reducing the probability of stability problems such as hot carrier effect and self-heating effect occurring in the drain region 125a of the PMOS transistor.

Specifically, using an ion implantation process, a PMOS region drain region 125a is formed in the bottom of the first semiconductor pillar 113 of the PMOS region I.

In this embodiment, the substrate further includes the NMOS region II, therefore, the step of forming the PMOS drain region 125a in the bottom of the first semiconductor pillar 113 of the PMOS region I includes: forming a protection on the substrate of the NMOS region II layer (not shown), only the substrate of the PMOS region I is exposed; the first ion doping treatment is performed on the bottom of the first semiconductor pillar 113 of the PMOS region I to form the PMOS region drain region 125a; the PMOS region I drain region 125a is formed After that, the protective layer on the substrate of the NMOS region II is removed.

In this embodiment, after the PMOS drain region 125a is formed, the forming method further includes: forming an NMOS drain region 125b in the bottom of the first semiconductor pillar 113 in the NMOS region II.

Specifically, the step of forming the NMOS drain region 125b includes: forming a protective layer on the substrate of the PMOS region I, exposing only the substrate of the NMOS region II; A second ion doping treatment is performed to form an NMOS drain region 125b; after the NMOS drain region 125b is formed, the protective layer on the substrate of the PMOS region I is removed. In other embodiments, the PMOS drain region may also be formed after the NMOS drain region is formed.

The first ion doping treatment is used to form the PMOS drain region 125a, so the doping ions in the first ion doping treatment are P-type ions, wherein the P-type ions are B ions, Ga ions or In ions; The second ion doping treatment is used to form the NMOS drain region 125b, so the doping ions in the second ion doping treatment are N-type ions, wherein the N-type ions are P ions, As ions or Sb ions.

It should be noted that, in the process of forming the PMOS drain region 125a in the bottom of the first semiconductor pillar 113 in the PMOS region I, and forming the NMOS drain region 125b in the bottom of the first semiconductor pillar 113 in the NMOS region II, the The substrate 112 is also exposed to the process environment, so the ions are also doped into part of the substrate 112 so that the PMOS drain region 125a and the NMOS drain region 125b are also formed in part of the substrate 112 Inside. In addition, by forming the PMOS drain region 125a and the NMOS drain region 125b in part of the substrate 112, it is also beneficial to reduce the drain that is electrically connected to the PMOS drain region 125a and the NMOS drain region 125b in the subsequent formation. The process difficulty of the contact hole plug in the area is improved, and the process compatibility is improved.

It should also be noted that, referring to FIG. 7 , in this embodiment, after the PMOS drain region 125 a is formed, the forming method further includes: forming a first isolation layer 130 on the substrate 112 exposed by the semiconductor pillar 120 , The first isolation layer 130 surrounds part of the PMOS drain region 125a.

The first isolation layer 130 is used for isolating adjacent devices, and after the gate structure surrounding the semiconductor pillar 120 is subsequently formed, the first isolation layer 130 is also used for isolating the substrate 112 from all other devices. the gate structure.

In this embodiment, the material of the first isolation layer 130 is silicon oxide. Silicon oxide is a commonly used and low-cost dielectric material, and has high process compatibility, which is beneficial to reduce the process difficulty and process cost of forming the first isolation layer 130; in addition, the dielectric constant of silicon oxide is relatively high. It is also beneficial to improve the function of the first isolation layer 130 for isolating adjacent devices and isolating the substrate 112 and the gate structure. In other embodiments, the material of the first isolation layer may also be other insulating materials such as silicon nitride and silicon oxynitride.

In this embodiment, the substrate further includes the NMOS region II. Therefore, in the step of forming the first isolation layer 130 , the first isolation layer 130 also surrounds part of the NMOS drain region 125b.

Specifically, the step of forming the first isolation layer 130 includes: forming a first isolation film (not shown) on the exposed substrate 112 of the semiconductor pillars 120 , the first isolation film surrounding the semiconductor pillars 120 ; Etch back the first isolation film, and the remaining first isolation film is used as the first isolation layer 130 .

In this embodiment, the first isolation layer 130 surrounds part of the PMOS drain region 125a and exposes part of the first semiconductor pillar 113, so that the gate structure of the subsequent PMOS region I can cover the first semiconductor At the junction of the pillar 113 and the second semiconductor pillar 114, the channel layer of the PMOS region I can span the second semiconductor pillar 114 and the first semiconductor pillar 113, so that the PMOS region I is close to the drain region 125a The mole percentage of Ge in the channel layer is lower.

Referring to FIG. 8 , after the PMOS drain region 125a is formed, a gate structure 140 surrounding the semiconductor pillar 120 is formed, and the gate structure 140 of the PMOS region I covers the first semiconductor pillar 113 and the second semiconductor pillar 114 The junction of the second semiconductor pillar 114 is exposed and the top of the second semiconductor pillar 114 is exposed, and the semiconductor pillar 120 covered by the gate structure 140 serves as a channel layer (not shown). Specifically, the gate structure 140 is formed on the first isolation layer 130 .

In this embodiment, the gate structure 140 is a fully surrounding gate structure and covers the junction of the first semiconductor pillar 113 and the second semiconductor pillar 114, so the channel layer of the PMOS region I can span the second semiconductor pillar 114 and the second semiconductor pillar 114. A semiconductor pillar 113, the molar percentage of Ge in the channel layer of the PMOS region I close to the drain region 125a is relatively low, thereby helping to improve stability problems such as hot carrier effect and self-heating effect near the drain region 125a of the PMOS transistor; After the PMOS source region is subsequently formed in the top of the second semiconductor pillar 114, the molar percentage of Ge in the channel layer of the PMOS region I close to the source region is higher, which is beneficial to improve the carrier mobility of the PMOS transistor.

It should be noted that, in this embodiment, the gate structure 140 of the NMOS region II also covers the junction of the first semiconductor pillar 113 and the third semiconductor pillar 115 and exposes the top of the third semiconductor pillar 115 .

The gate structure 140 exposes the tops of the second semiconductor pillars 114 and the third semiconductor pillars 115 , so that a PMOS source region can be subsequently formed in the tops of the second semiconductor pillars 114 and the tops of the third semiconductor pillars 115 An NMOS source region is formed inside.

In this embodiment, the gate structure 140 is a metal gate structure, and the gate structure 140 includes a gate oxide layer 131 surrounding the semiconductor pillar 120 , a gate dielectric layer 132 surrounding the gate oxide layer 131 , and a gate dielectric layer 132 surrounding the gate dielectric layer 132 . The gate electrode layer 133 .

In this embodiment, the gate oxide layer 131 covers the surface of the semiconductor pillar 120 exposed by the first isolation layer 130 .

In this embodiment, the material of the gate oxide layer 131 is silicon oxide. In other embodiments, the material of the gate oxide layer may also be silicon oxynitride.

In this embodiment, the material of the gate dielectric layer 132 is a high-k dielectric material, wherein the high-k dielectric material refers to a dielectric material with a relative permittivity greater than that of silicon oxide. Specifically, the material of the gate dielectric layer 132 is HfO ₂ . In other embodiments, the material of the gate dielectric layer may also be selected from ZrO ₂ , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al ₂ O ₃ and the like.

It should be noted that, in this embodiment, the gate dielectric layer 132 is also located between the first isolation layer 130 and the gate structure 140 because the gate dielectric layer 132 and the first isolation layer 130 are both insulating materials. It does not affect the performance of the transistor and helps to simplify the process flow. In other embodiments, the gate dielectric layer between the first isolation layer and the gate structure may also be removed.

The material of the gate electrode layer 133 is Al, Cu, Ag, Au, Pt, Ni, Ti or W. In this embodiment, the material of the gate electrode layer 133 is W.

In other embodiments, the gate structure may also be a polysilicon gate structure. Correspondingly, the gate structure includes a gate oxide layer and a gate layer surrounding the gate oxide layer.

It should be noted that, in this embodiment, a hard mask layer 122 (as shown in FIG. 7 ) and a buffer layer 121 (as shown in FIG. 7 ) are also formed on top of the semiconductor pillars 120 . After the first isolation layer 130 and before the gate structure 140 is formed, the forming method further includes: removing the hard mask layer 122 and the buffer layer 121 to expose the surface of the semiconductor pillar 120 .

Continuing to refer to FIG. 8 , after the gate structure 140 is formed, a PMOS source region 145 a is formed in the top of the second semiconductor pillar 114 .

In this embodiment, the mole percentage of Ge in the channel layer of the PMOS region I close to the source region 145a is greater than the mole percentage of Ge in the channel layer close to the drain region 125a. Therefore, the PMOS region I is close to The carrier mobility of the channel layer of the source region 145a is relatively high, thereby improving the electrical performance of the PMOS transistor.

Specifically, a PMOS source region 145 a is formed in the top of the second semiconductor pillar 114 by using an ion implantation process.

In this embodiment, the substrate further includes the NMOS region II, so the step of forming the PMOS source region 145a in the top of the second semiconductor pillar 114 includes: forming a protection covering the gate structure 140 of the NMOS region II and the top of the third semiconductor pillar 115 layer (not shown), only the top of the second semiconductor pillar 114 in the PMOS region I is exposed; the third ion doping treatment is performed on the top of the second semiconductor pillar 114 in the PMOS region I to form the PMOS source region 145a; after the PMOS region source region 145a is formed , remove the protective layer of the NMOS region II.

It should be noted that, in this embodiment, after the PMOS source region 145a is formed, the forming method further includes: forming an NMOS source region 145b in the top of the third semiconductor pillar 115 .

Specifically, the step of forming the NMOS source region 145b includes: forming a protective layer (not shown) covering the gate structure 140 of the PMOS region I and the top of the second semiconductor pillar 114, and only exposing the third semiconductor of the NMOS region II The top of the pillar 115; the fourth ion doping treatment is performed on the top of the third semiconductor pillar 115 in the NMOS region II to form the NMOS source region 145b; after the NMOS source region 145b is formed, the protective layer of the PMOS region I is removed. In other embodiments, the source region of the PMOS region may also be formed after the source region of the NMOS region is formed.

The doping ions of the third ion doping treatment are the same as the doping ions of the first ion doping treatment, therefore, the doping ions of the third ion doping treatment are also P-type ions, wherein the P-type ions are B ions, Ga ions or In ions; the doping ions of the fourth ion doping treatment are the same as the doping ions of the second ion doping treatment, therefore, the doping ions of the fourth ion doping treatment are N-type ions, wherein, The N-type ions are P ions, As ions or Sb ions.

With reference to FIG. 9 , it should be noted that, after forming the PMOS source region 145a, the forming method further includes: forming a second isolation layer 150 surrounding the PMOS source region 145a, and the second isolation layer 150 is located at the on the gate structure 140 and covering the top of the semiconductor pillar 120 .

The second isolation layer 150 is used to provide a process platform for the subsequent formation of contact holes and contact hole plugs electrically connected to the PMOS source region 145a, and the second isolation layer 150 is also used to isolate adjacent devices.

In this embodiment, the substrate further includes an NMOS region II. Therefore, in the step of forming the second isolation layer 150, the second isolation layer 150 also surrounds the NMOS source region 145b.

In this embodiment, in order to improve process compatibility, the material of the second isolation layer 150 and the first isolation layer 130 are the same, and the material of the second isolation layer 150 is correspondingly silicon oxide. In other embodiments, the material of the second isolation layer may also be other insulating materials such as silicon nitride and silicon oxynitride.

It should be noted that, referring to FIG. 8 , the gate oxide layer 131 covers the surface of the semiconductor pillar 120 exposed by the first isolation layer 130 , therefore, a third ion doping is performed on the top of the second semiconductor pillar 114 During the process of forming the PMOS source region 145a and the fourth ion doping process on the top of the third semiconductor pillar 115 to form the NMOS source region 145b, the ions are also doped into the gate oxide exposed by the gate structure 140. within layer 131. In order to reduce the influence on the electrical performance of the semiconductor structure, and to subsequently form a contact hole plug electrically connected to the PMOS source region 145a, in this embodiment, the second isolation is formed after the source PMOS source region 145a is formed. Before the layer 150 , the forming method further includes: removing the gate oxide layer 131 exposed by the gate electrode layer 133 .

In this embodiment, a dry etching process is used to remove the gate oxide layer 131 exposed by the gate electrode layer 133 .

When the dry etching process is used, the bias voltage can be adjusted to adjust the amount of lateral etching, so that the gate oxide layer 131 on the top of the semiconductor pillar 120 can be removed, and the semiconductor exposed by the gate electrode layer 133 can also be removed. The gate oxide layer 131 on the sidewall of the pillar 120 .

Continuing to refer to FIG. 9 , after the second isolation layer 150 is formed, the second isolation layer 150 on top of the PMOS source region 145 a is etched, and a contact hole (not shown) is formed in the second isolation layer 150 . The contact hole exposes the top of the PMOS source region 145a; a contact hole plug 160 is formed in the contact hole.

The contact hole is used to provide a space for forming the contact hole plug 160 .

In this embodiment, the substrate further includes the NMOS region II. Therefore, in the step of etching the second isolation layer 150 on the top of the PMOS source region 145a, the second isolation layer 150 on the top of the NMOS source region 145b is also etched. That is to say, the contact hole is also located in the second isolation layer 150 of the NMOS region II.

The contact hole plug 160 is used for electrical connection with the PMOS source region 145a. In this embodiment, the contact hole plug 160 is further formed in the contact hole of the NMOS region II, and the contact hole plug 160 is also electrically connected to the NMOS source region 145b.

In this embodiment, the material of the contact hole plug 160 is tungsten. In other embodiments, the material of the contact hole plug may also be one or more of metal nitride, titanium nitride and thallium nitride.

It should be noted that, after forming the contact hole and before forming the contact hole plug 160 in the contact hole, the forming method further includes: the surfaces of the PMOS source region 145a and the NMOS source region 145b exposed in the contact hole A silicide layer 155 is formed.

The silicide layer 155 is located on the surface of the PMOS source region 145a and the NMOS source region 145b exposed by the contact hole, and is beneficial to reduce the size of the contact hole plug 160 that is electrically connected to the PMOS source region 145a and the NMOS source region 145b. The contact resistance between the PMOS source region 145 a and the contact hole plug 160 , and the NMOS source region 145 b and the contact hole plug 160 .

In this embodiment, the material of the silicide layer 155 may be TiSi, NiSi, or CoSi, or the like.

Correspondingly, the present invention also provides a semiconductor structure. Referring to FIG. 9 , a schematic structural diagram of an embodiment of the semiconductor structure of the present invention is shown.

The semiconductor structure includes: a base including a PMOS region I, the base including a substrate 112 and a semiconductor pillar 120 protruding from the substrate 112, the semiconductor pillar 120a of the PMOS region I including a first semiconductor pillar 113 and The second semiconductor pillar 114 located on the first semiconductor pillar 113, the mole percentage of Ge in the second semiconductor pillar 114 is greater than the mole percentage of Ge in the first semiconductor pillar 113; the PMOS drain region 125a, located in the In the bottom of the first semiconductor pillar 113 in the PMOS region I; the gate structure 140 surrounds the semiconductor pillar 120, the gate structure 140 covers the junction of the first semiconductor pillar 113 and the second semiconductor pillar 114 and exposes the On the top of the second semiconductor pillar 114 , the semiconductor pillar 120 covered by the gate structure 140 serves as a channel layer (not shown); the PMOS source region 145 a is located in the top of the second semiconductor pillar 114 .

In the semiconductor field, the voltage of the PMOS drain region 145a is generally higher than that of the source region 125a, and the electric field near the drain region 145a is stronger. By making the mole percentage of Ge in the second semiconductor pillar 114 larger than that in the first semiconductor pillar 113 The mole percentage of Ge is such that the mole percentage of Ge in the channel layer near the source region 145a of the PMOS region I is greater than the mole percentage of Ge in the channel layer near the drain region 125a, and the PMOS region I is near the channel of the source region 145a. The higher molar percentage of Ge in the channel layer is beneficial to improve the mobility of carriers in the channel layer of the PMOS transistor close to the source region 145a, thereby improving the electrical performance of the PMOS transistor; the PMOS region I is close to the channel of the drain region 125a The lower molar percentage of Ge in the layer is beneficial to lower the mobility of carriers in the channel layer of the PMOS region I close to the drain region 125a, thereby helping to improve the hot carrier effect and spontaneous flow near the drain region 125a of the PMOS transistor Thermal effects and other stability problems, thereby improving the electrical properties of the semiconductor structure.

The base of the PMOS region I is used to form PMOS transistors. It should be noted that, in this embodiment, the substrate further includes an NMOS region II, and the substrate of the NMOS region II is used to form an NMOS transistor.

In this embodiment, the semiconductor pillar 120 b of the NMOS region II includes a first semiconductor pillar 113 and a third semiconductor pillar 115 located on the first semiconductor pillar 113 .

The semiconductor structure further includes: an NMOS drain region 125b located in the bottom of the first semiconductor pillar 113 of the NMOS region II; and an NMOS source region 145b located in the top of the third semiconductor pillar 115 .

The substrate 112 provides a process platform for the formation of semiconductor structures.

In this embodiment, the substrate 112 is a silicon substrate. In other embodiments, the material of the substrate may also be germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate may also be a silicon-on-insulator substrate or germanium-on-insulator substrate.

The PMOS region I semiconductor pillar 120a is used to form the PMOS drain region 125a, the source region 145a and the channel layer.

In this embodiment, the semiconductor pillar 120a of the PMOS region I includes a first semiconductor pillar 113 and a second semiconductor pillar 114 located on the first semiconductor pillar 113, and the mole percentage of Ge in the second semiconductor pillar 114 is greater than The mole percentage of Ge in the first semiconductor pillars 113 .

The first semiconductor pillars 113 of the PMOS region I are used to form the PMOS drain region 125a and the channel layer, and the first semiconductor pillars 113 of the NMOS region II are used to form the NMOS drain region 125b and the channel layer.

In this embodiment, the first semiconductor pillars 113 and the substrate 112 are obtained by etching the same semiconductor material layer. Correspondingly, it is also Si. In other embodiments, according to actual process requirements, the materials of the first semiconductor column and the substrate may also be different, and in order to further improve the carrier mobility of the PMOS transistor, the first semiconductor column The material can be SiGe.

In this embodiment, the first semiconductor column 113 is a single-layer structure, that is, the first semiconductor column 113 only includes a single semiconductor layer (not shown), which can simplify the process flow and reduce the difficulty of the process operation. In other embodiments, the first semiconductor pillar may further include a plurality of semiconductor layers sequentially located on the substrate, and, in the first semiconductor pillar, from far from the second semiconductor pillar to close to the In the direction of the second semiconductor column, the mole percentage of Ge in the semiconductor layer gradually increases. Therefore, the mole percentage of Ge in the first semiconductor column decreases sequentially from top to bottom, which is beneficial to further improve the channel of the PMOS transistor near the drain region. Stability issues such as the hot carrier effect of the layer and the self-heating effect.

The second semiconductor pillar 114 is used to form the PMOS source region 145a and the channel layer.

The material of the second semiconductor pillar 114 is SiGe, and the SiGe material can provide compressive stress to the channel layer of the PMOS transistor, thereby helping to improve the carrier mobility of the PMOS transistor.

It should be noted that, in this embodiment, the second semiconductor pillar 114 includes a plurality of semiconductor layers sequentially located on the first semiconductor pillar 113 , and in the second semiconductor pillar 114 , the From the first semiconductor pillar 113 to the direction away from the first semiconductor pillar 113 , the mole percentage of Ge in the semiconductor layer gradually increases. Therefore, the mole percentage of Ge in the second semiconductor pillar 114 decreases sequentially from top to bottom, which is beneficial to The mobility of carriers in the channel layer of the PMOS transistor near the source region 145a is further improved, and the stability problems such as hot carrier effect and self-heating effect of the channel layer of the PMOS transistor near the drain region 125a are improved. In other embodiments, the second semiconductor pillar may also include only a single semiconductor layer, which is beneficial to simplify the process flow.

In this embodiment, the material of the third semiconductor pillar 115 and the first semiconductor pillar 113 are the same, and the material of the third semiconductor pillar 115 is correspondingly Si. Therefore, the material of the semiconductor pillar 120b in the NMOS region II is Si, which is beneficial to improve the Process compatibility, and carrier mobility of the NMOS transistor channel layer.

The PMOS drain region 125a is doped with P-type ions, wherein the P-type ions are B ions, Ga ions or In ions; the NMOS drain region 125b is doped with N-type ions, wherein the N-type ions are Type ions are P ions, As ions or Sb ions.

It should be noted that the PMOS drain region 125a and the NMOS drain region 125b are formed by ion doping the bottom of the first semiconductor pillar 113. During the ion doping process, the substrate 112 is also Exposed to the process environment, the ions are also doped into part of the substrate 112 so that the PMOS drain region 125a and the NMOS drain region 125b are also located in part of the substrate 112 . Moreover, by making the PMOS drain region 125a and the NMOS drain region 125b also located in part of the substrate 112, it is beneficial to reduce the subsequent formation of drain contacts electrically connected to the PMOS drain region 125a and the NMOS drain region 125b. The process difficulty of the hole plug is improved, and the process compatibility is improved.

It should also be noted that, in this embodiment, the semiconductor structure further includes: a first isolation layer 130 located between the substrate 112 and the gate structure 140 and surrounding a part of the PMOS drain region 125a.

The first isolation layer 130 is used to isolate adjacent devices, and the first isolation layer 130 is also used to isolate the substrate 112 and the gate structure 140 .

In this embodiment, the material of the first isolation layer 130 is silicon oxide. Silicon oxide is a commonly used and low-cost dielectric material, and has high process compatibility, which is beneficial to reduce the difficulty of forming the first isolation layer 130 and the process cost; It is beneficial to improve the function of the first isolation layer 130 for isolating adjacent devices, isolating the substrate 112 and the gate structure 140 . In other embodiments, the material of the first isolation layer may also be other insulating materials such as silicon nitride and silicon oxynitride.

In this embodiment, the substrate further includes an NMOS region II, and accordingly, the first isolation layer 130 also surrounds a part of the NMOS drain region 125b accordingly.

In this embodiment, the first isolation layer 130 surrounds part of the PMOS drain region 125a and exposes part of the first semiconductor pillar 113, so that the gate structure of the PMOS region I can cover the first semiconductor pillar 113 and the junction of the second semiconductor pillar 114, so the channel layer of the PMOS region I can span the second semiconductor pillar 114 and the first semiconductor pillar 113 so that the PMOS region I is close to the drain region 125a The mole percentage of Ge in the channel layer is low.

In this embodiment, the gate structure 140 is a fully surrounding gate structure and covers the junction of the first semiconductor pillar 113 and the second semiconductor pillar 114, so the channel layer of the PMOS region I can span the second semiconductor pillar 114 and the first semiconductor pillar 113, the molar percentage of Ge in the channel layer of the PMOS region I near the drain region 125a is relatively low, thereby helping to improve the stability of the hot carrier effect and the self-heating effect near the drain region 125a of the PMOS transistor The PMOS region I has a higher molar percentage of Ge in the channel layer close to the source region 145a, which is beneficial to improve the carrier mobility of the PMOS transistor.

It should be noted that, in this embodiment, the gate structure 140 of the NMOS region II also covers the junction of the first semiconductor pillar 113 and the third semiconductor pillar 115 and exposes the top of the third semiconductor pillar 115 .

The gate structure 140 exposes the top of the second semiconductor pillar 114 and the third semiconductor pillar 115 so that the PMOS source region 145a can be formed in the top of the second semiconductor pillar 114, enabling the NMOS The source region 145b can be formed in the top of the third semiconductor pillar 115 .

In this embodiment, the gate structure 140 is a metal gate structure, and the gate structure 140 includes a gate oxide layer 131 surrounding the semiconductor pillar 120 , a gate dielectric layer 132 surrounding the gate oxide layer 131 , and a gate dielectric layer 132 surrounding the gate oxide layer 131 . The gate electrode layer 133 of the gate dielectric layer 132 is described.

In this embodiment, the material of the gate oxide layer 131 is silicon oxide. In other embodiments, the material of the gate oxide layer may also be silicon oxynitride.

In this embodiment, the material of the gate dielectric layer 132 is a high-k dielectric material, wherein the high-k dielectric material refers to a dielectric material with a relative permittivity greater than that of silicon oxide. Specifically, the material of the gate dielectric layer 132 is HfO ₂ . In other embodiments, the material of the gate dielectric layer may also be selected from ZrO ₂ , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al ₂ O ₃ and the like.

In this embodiment, the gate dielectric layer 132 is also located between the first isolation layer 130 and the gate structure 140 , because the gate dielectric layer 132 and the first isolation layer 130 are both insulating materials, which will not affect the performance of transistors, and is conducive to simplifying the process flow. In other embodiments, the gate dielectric layer may only be located between the gate oxide layer and the gate electrode layer.

The material of the gate electrode layer 133 is Al, Cu, Ag, Au, Pt, Ni, Ti or W. In this embodiment, the material of the gate electrode layer 133 is W.

In other embodiments, the gate structure may also be a polysilicon gate structure. Correspondingly, the gate structure includes a gate oxide layer and a gate layer surrounding the gate oxide layer.

In this embodiment, the PMOS source region 145 a is located in the top of the second semiconductor pillar 114 , and the NMOS source region 145 b is located in the top of the third semiconductor pillar 115 .

The doped ions in the PMOS source region 145a and the drain region 125a are the same, the doping ions in the PMOS source region 145b and the drain region 125b are the same, and the doped ions in the PMOS source region 145a and the NMOS source region 145b are the same. For details of the doping ions, reference may be made to the foregoing description of the doping ions in the PMOS drain region 125a and the NMOS drain region 125b, which will not be repeated here.

It should also be noted that the semiconductor structure further includes: a second isolation layer 150 surrounding the PMOS source region 145a, the second isolation layer 150 is located on the gate structure 140 and the top of the second isolation layer 150 is higher than the semiconductor The top of the pillar 120; the contact hole plug 160, located in the second isolation layer 150 and electrically connected to the PMOS source region 145a.

The second isolation layer 150 is used to provide a process platform for forming the contact hole plug 160, and the second isolation layer 150 is also used to isolate adjacent devices.

In this embodiment, the substrate further includes an NMOS region II, therefore, the second isolation layer 150 also surrounds the NMOS source region 145b.

In this embodiment, in order to improve process compatibility, the material of the second isolation layer 150 and the first isolation layer 130 are the same, and the material of the second isolation layer 150 is correspondingly silicon oxide. In other embodiments, the material of the second isolation layer may also be other insulating materials such as silicon nitride and silicon oxynitride.

The contact hole plug 160 is electrically connected to the PMOS source region 145a. Correspondingly, the contact hole plug 160 is also located in the second isolation layer 150 of the NMOS region II, and the contact hole plug 160 is also electrically connected to the NMOS source region 145b.

In this embodiment, the material of the contact hole plug 160 is tungsten. In other embodiments, the material of the contact hole plug may also be one or more of metal nitride, titanium nitride and thallium nitride.

In addition, in this embodiment, the semiconductor structure further includes: a silicide layer 155 located between the PMOS source region 145 a and the contact hole plug 160 and the NMOS source region 145 b and the contact hole plug 160 .

The silicide layer 155 is used to reduce the contact resistance between the PMOS source region 145a and the contact hole plug 160 , and the NMOS source region 145b and the contact hole plug 160 .

In this embodiment, the material of the silicide layer 155 may be TiSi, NiSi, or CoSi, or the like.

The semiconductor structure may be formed by the formation method described in the foregoing embodiments, or may be formed by other formation methods. For the specific description of the semiconductor structure in this embodiment, reference may be made to the corresponding descriptions in the foregoing embodiments, which will not be repeated in this embodiment.

Although the present invention is disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be based on the scope defined by the claims.

Claims (20)

1. A method of forming a semiconductor structure, comprising:

forming a base, wherein the base comprises a PMOS (P-channel metal oxide semiconductor) region, the base comprises a substrate and a semiconductor column protruding out of the substrate, the semiconductor column of the PMOS region comprises a first semiconductor column and a second semiconductor column positioned on the first semiconductor column, and the mole percentage of Ge in the second semiconductor column is greater than that in the first semiconductor column;

forming a PMOS drain region in the bottom of the first semiconductor pillar in the PMOS region;

after the PMOS drain region is formed, a grid structure surrounding the semiconductor column is formed, the grid structure of the PMOS region covers the junction of the first semiconductor column and the second semiconductor column and exposes the top of the second semiconductor column, and the semiconductor column covered by the grid structure is used as a channel layer;

and forming a PMOS source region in the top of the second semiconductor column after the gate structure is formed, wherein in the PMOS region, the molar percentage of Ge in the channel layer close to the source region is greater than that in the channel layer close to the drain region.

2. The method of forming a semiconductor structure according to claim 1, wherein the second semiconductor pillar includes a plurality of semiconductor layers sequentially located on the first semiconductor pillar, and wherein, in the second semiconductor pillar, a molar percentage of Ge in a semiconductor layer gradually increases from a direction close to the first semiconductor pillar to a direction away from the first semiconductor pillar.

3. The method of claim 1 or 2, wherein the first semiconductor pillar comprises a plurality of semiconductor layers sequentially located on the substrate, and wherein a molar percentage of Ge in a semiconductor layer in the first semiconductor pillar gradually increases from a direction away from the second semiconductor pillar to a direction closer to the second semiconductor pillar.

4. The method of forming a semiconductor structure according to claim 1, wherein a material of the first semiconductor pillar is Si or SiGe.

5. The method of forming a semiconductor structure according to claim 1, wherein a material of the second semiconductor pillar is SiGe.

6. The method of forming a semiconductor structure of claim 1, wherein forming the PMOS region base comprises: providing a first semiconductor material layer, and forming a second semiconductor material layer on the first semiconductor material layer, wherein the mole percentage of Ge in the second semiconductor material layer is greater than that in the first semiconductor material layer;

and sequentially etching the second semiconductor material layer and the first semiconductor material layer, and forming a substrate and a semiconductor column protruding out of the substrate on the PMOS region.

7. The method for forming a semiconductor structure according to claim 6, wherein the second semiconductor material layer and the first semiconductor material layer are sequentially etched by a dry etching process.

8. The method of claim 6, wherein the process of forming the second layer of semiconductor material on the first layer of semiconductor material is an epitaxial growth process.

9. The method of claim 8, wherein the second semiconductor material layer is SiGe, and the epitaxial growth process uses SiH as a gas ₄ 、Si ₂ H ₆ 、GeH ₄ And Ge ₂ H ₆ A gas.

10. The method of forming a semiconductor structure of claim 6, wherein the substrate further comprises an NMOS region;

the step of forming the NMOS region substrate comprises the following steps: after the second semiconductor material layer is formed, removing the second semiconductor material layer on the NMOS area; forming a third semiconductor material layer on the first semiconductor material layer of the NMOS region, wherein the third semiconductor material layer and the first semiconductor material layer are made of the same material;

in the process of etching the second semiconductor material layer and the first semiconductor material layer of the PMOS region, sequentially etching the third semiconductor material layer and the first semiconductor material layer of the NMOS region, and forming the substrate and a semiconductor column protruding from the substrate on the NMOS region, wherein the semiconductor column of the NMOS region comprises the first semiconductor column and a third semiconductor column positioned on the first semiconductor column;

forming an NMOS drain region in the bottom of the first semiconductor pillar of the NMOS region;

in the step of forming the gate structure, the gate structure also covers the boundary of the first semiconductor pillar and the third semiconductor pillar and exposes the top of the third semiconductor pillar;

after the gate structure is formed, the forming method further comprises: and forming an NMOS source region in the top of the third semiconductor column.

11. The method of forming a semiconductor structure of claim 1, wherein after forming the PMOS drain region and before forming the gate structure, the method further comprises: forming a first isolation layer on the substrate exposed out of the semiconductor pillar, wherein the first isolation layer surrounds part of the PMOS drain region;

in the step of forming a gate structure surrounding the semiconductor pillar, the gate structure is formed on the first isolation layer.

12. The method of forming a semiconductor structure of claim 1, wherein the method of forming further comprises, after forming the PMOS source region: forming a second isolation layer surrounding the PMOS source region, wherein the second isolation layer is positioned on the grid structure and covers the top of the semiconductor column;

etching the second isolation layer on the top of the PMOS source region, and forming a contact hole in the second isolation layer, wherein the contact hole exposes the top of the PMOS source region;

and forming a contact hole plug in the contact hole.

13. A semiconductor structure, comprising:

the semiconductor pillar of the PMOS region comprises a first semiconductor pillar and a second semiconductor pillar positioned on the first semiconductor pillar, and the mole percentage of Ge in the second semiconductor pillar is greater than that in the first semiconductor pillar;

a PMOS drain region located within a bottom of the PMOS region first semiconductor pillar;

the grid structure surrounds the semiconductor pillar, covers the junction of the first semiconductor pillar and the second semiconductor pillar and exposes the top of the second semiconductor pillar, and the semiconductor pillar covered by the grid structure is used as a channel layer;

a PMOS source region located within a top portion of the second semiconductor pillar; and in the PMOS region, the mole percentage of Ge in the channel layer close to the source region is larger than that in the channel layer close to the drain region.

14. The semiconductor structure of claim 13, wherein the second semiconductor pillar comprises a plurality of semiconductor layers sequentially located on the first semiconductor pillar, and wherein a mole percentage of Ge in a semiconductor layer gradually increases in the second semiconductor pillar from near the first semiconductor pillar to far away from the first semiconductor pillar.

15. The semiconductor structure of claim 13 or 14, wherein the first semiconductor pillar comprises a plurality of semiconductor layers sequentially located on the substrate, and wherein a molar percentage of Ge in a semiconductor layer gradually increases in the first semiconductor pillar from a direction away from the second semiconductor pillar to a direction closer to the second semiconductor pillar.

16. The semiconductor structure of claim 13, wherein the material of the first semiconductor pillar is Si or SiGe.

17. The semiconductor structure of claim 13, wherein the material of the second semiconductor pillar is SiGe.

18. The semiconductor structure of claim 13, wherein the substrate further comprises an NMOS region;

the semiconductor pillar of the NMOS region comprises a first semiconductor pillar and a third semiconductor pillar positioned on the first semiconductor pillar, and the third semiconductor pillar and the first semiconductor pillar are made of the same material;

the gate structure also covers the intersection of the first semiconductor pillar and a third semiconductor pillar and exposes the top of the third semiconductor pillar;

the semiconductor structure further includes: an NMOS drain region located within a bottom of the NMOS region first semiconductor pillar; an NMOS source region located within a top portion of the third semiconductor pillar.

19. The semiconductor structure of claim 13, wherein the semiconductor structure further comprises: and the first isolation layer is positioned between the substrate and the gate structure and surrounds part of the PMOS drain region.

20. The semiconductor structure of claim 13, wherein the semiconductor structure further comprises: the second isolation layer surrounds the PMOS source region, is positioned on the grid structure and has the top higher than the top of the semiconductor column;

and the contact hole plug is positioned in the second isolation layer and is electrically connected with the PMOS source region.

Images