KR20020007862A - Method for forming a flash memory cell - Google Patents

Abstract

The present invention relates to a method of manufacturing a flash memory cell, comprising the steps of sequentially forming a tunnel oxide film, a first polysilicon layer, a first oxide film and a nitride film on a semiconductor substrate on which a field oxide film is formed, the nitride film, the first oxide film, Patterning the first polysilicon layer and the tunnel oxide film sequentially, and forming a second oxide film on the entire upper surface thereof, and then polishing the second oxide film until the nitride film is exposed by chemical mechanical polishing to planarize the surface. And sequentially removing the remaining nitride film and the second oxide film, and forming silicon spacers on both sides of the patterned first polysilicon layer, and removing the second oxide film and the natural oxide film remaining on the surface. The selective metastable polysilicon forming process is performed to make the surface of the silicon spacer into an uneven structure. Heat treating the silicon spacers to be conductive; forming a dielectric film on the entire upper surface of the silicon spacer including a floating gate including the first polysilicon layer and the silicon spacer; and then forming a second polysilicon layer and a metal silicide on the dielectric film. Forming a layer sequentially, and patterning the metal silicide layer and the second polysilicon layer sequentially to form a control gate.

Description

Method for manufacturing a flash memory cell {Method for forming a flash memory cell}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a flash memory cell, and more particularly, to a method of manufacturing a flash memory cell in which a capacitance between a control gate and a floating gate is increased so that program and erase operations can be performed even at a low voltage. will be.

In general, a flash memory cell includes a gate in which a tunnel oxide layer, a floating gate, a dielectric layer, and a control gate are stacked on an upper portion of a channel region of a semiconductor substrate, and a junction region formed on a semiconductor substrate at both sides of the gate. electrons are programmed as they are injected and erased as the injected electrons are discharged by FN tunneling.

In order to inject or discharge hot electrons, a positive or negative high voltage must be applied to the control gate. To do this, a high voltage (for example, 9V, 12V) is applied using a power supply voltage (for example, 5V). The charge pump circuit (Charge pump circuit) for generating a) is required, and accordingly a high voltage transistor having a thick gate oxide film should be formed. In fact, a low voltage transistor having a thickness of 120 mV and a high voltage transistor of 200 mW is formed in one die in which 85 memory cells are formed. Therefore, since the process of controlling the thickness of the gate oxide film must be performed differently, it is difficult to develop the process.

In order to reduce the voltage applied to the control gate during the program and erase operations, the coupling ratio of the memory cell must be increased. Here, the coupling ratio means the ratio of the capacitance (C _ONO ) between the control gate and the floating gate and the capacitance (C _TUN ) between the floating gate and the tunnel oxide, that is, C _ONO / (C _ONO + C _TUN ). Increasing the capacitance applied to the dielectric film of the ONO structure consisting of a nitride film and an oxide film increases the effective voltage applied to the tunnel oxide film, thereby enabling programming and erasing operation even at a low voltage.

However, the conventional flash memory cell has a limitation in increasing the coupling ratio due to the flat surface of the floating gate, thereby limiting the size reduction of the memory cell. For reference, a conventional flash memory cell has a coupling ratio of 0.6 or less.

Therefore, the present invention can solve the above-mentioned disadvantages by forming a silicon spacer on both sides of the polysilicon pattern and then forming a selective metastable polysilicon process so that the surface of the silicon spacer becomes an uneven structure. It is an object of the present invention to provide a method for manufacturing a flash memory cell.

1 to 10 are cross-sectional views of devices for explaining a method of manufacturing a flash memory cell according to the present invention.

<Explanation of symbols for the main parts of the drawings>

1: semiconductor substrate 2: field oxide film

3: tunnel oxide film 4: first polysilicon layer

5: first oxide film 6: nitride film

7: second oxide film 8: silicon film

8A: Silicon Spacer 9: Dielectric Film

10: second polysilicon layer 11: metal silicide layer

A method of manufacturing a flash memory cell according to the present invention comprises the steps of sequentially forming a tunnel oxide film, a first polysilicon layer, a first oxide film and a nitride film on a semiconductor substrate on which a field oxide film is formed, and a nitride film, a first oxide film, and a first poly film. Patterning the silicon layer and the tunnel oxide film sequentially, forming a second oxide film on the entire upper surface, and then polishing the second oxide film to planarize the surface until the nitride film is exposed by a chemical mechanical polishing process; Forming a silicon spacer on both sides of the patterned first polysilicon layer after sequentially removing the nitride film and the second oxide film, and removing the natural oxide film remaining on the second oxide film and the surface, and then forming a selective metastable polysilicon. To make the surface of the silicon spacer into an uneven structure, and then heat the silicon spacer Forming a dielectric film on the entire top surface including the floating gate made of the first polysilicon layer and the silicon spacer, and subsequently forming a second polysilicon layer and a metal silicide layer on the dielectric film; Patterning the silicide layer and the second polysilicon layer sequentially to form a control gate.

In addition, the surface of the semiconductor substrate is cleaned using a DHF and SC-1 solution before forming the tunnel oxide film, and the DHF and SC-1 solution is used to remove the native oxide film and particles before forming the dielectric film.

The selective metastable polysilicon forming process includes loading and heating a semiconductor substrate into a device at a temperature of 550 to 560 ° C., flowing a silicon source gas in an amount of 10 to 100 sccm, and forming a silicon seed on the surface of the silicon spacer. Or growing silicon grains present in the silicon spacers and performing plasma heat treatment such that the surface becomes an uneven structure by the movement of silicon atoms.

Next, the present invention will be described in detail with reference to the accompanying drawings.

1 to 10 are cross-sectional views of devices for explaining a method of manufacturing a flash memory cell according to the present invention.

1 shows a tunnel oxide film 3, a first polysilicon layer 4, a first oxide film 5 and a nitride film 6 sequentially formed on a semiconductor substrate 1 on which a field oxide film 2 is formed. In cross section, the surface of the semiconductor substrate 1 is diluted with DHF (HF: H ₂ O = 50 to 100: 1) and SC-1 (NH ₄ OH / H ₂ O) before the tunnel oxide film 3 is formed. ₂ / H ₂ O) solution.

The tunnel oxide film 3 is formed by a wet oxidation method using hydrogen (H ₂ ) and oxygen (O ₂ ) at a temperature of 750 to 800 ° C., and has an interface with the semiconductor substrate 1 by controlling the thickness to about 50 to 100 μs. Ensure defect density is minimized. In addition, after the oxidation process is heat-treated for 20 to 30 minutes at a temperature of 900 to 910 ℃ and nitrogen (N ₂ ) gas atmosphere.

The first polysilicon layer 4 is deposited by low pressure chemical vapor deposition (LPCVD) using a silicon source gas such as SiH ₄ or Si ₂ H ₆ at a temperature of 550 to 620 ° C. and a pressure of 0.1 to 3.0 Torr. It is made of doped polysilicon and is formed to a thickness of 500-1500 mm 3.

The first oxide film 5 is formed of a thermal oxide film, a DCS (SiH ₂ Cl ₂ ) -hot oxide film (Hot Temperature Oxide), or a CVD oxide film using TEOS, and is formed to a thickness of 50 to 100 kPa. At this time, the column when using the oxide film to form a dry oxidation method at a temperature of 750 to _{950 ℃, DCS (SiH 2 Cl} 2) - Heat the case of using the oxide film at a pressure and 750 to a temperature of 850 ℃ of 1Torr or less SiH ₂ Cl _{It is} formed using ₂ and N ₂ O gas.

The nitride film 6 is formed by low pressure chemical vapor deposition (LPCVD) using NH ₃ and DCS (SiH ₂ Cl ₂ ) gas at a temperature of 730 to 780 ° C. and a pressure of 1 Torr or less, and has a thickness of 1500 to 2500 내지. Is formed.

FIG. 2 is a cross-sectional view of the nitride film 6, the first oxide film 5, the first polysilicon layer 4, and the tunnel oxide film 3 sequentially patterned, wherein the field oxide film 2 and the tunnel The loss of the oxide film 3 is prevented from occurring.

3 is a cross-sectional view of the second oxide film 7 formed on the entire upper surface with a thickness of 5000 to 10000 kPa, and the second oxide film 7 is made of a high density plasma oxide.

FIG. 4 is a cross-sectional view of the second oxide film 7 polished until the nitride film 6 is exposed by chemical and mechanical polishing, to planarize the surface thereof, and the process margin of the chemical mechanical polishing process. In order to ensure the thickness, the thickness of the second oxide film 7 must be properly controlled.

FIG. 5 is a cross-sectional view of the nitride film 6 remaining by dipping in a H ₃ PO ₄ solution, and FIG. 6 is a view of using a DHF (diluted with HF: H ₂ O = 50 to 100: 1) solution. A cross-sectional view of the silicon film 8 formed on the entire upper surface after the removal of the second oxide film 5 by a cleaning process to form a thickness of 500 to 1500 kPa, wherein the silicon film 8 is undoped or low. Concentrated lightly doped amorphous silicon.

In this case, when undoped amorphous silicon is used by low pressure chemical vapor deposition (LPCVD) using SiH ₄ or Si ₂ H ₆ as a source gas at a temperature of 510 to 550 ° C. and a pressure of 3 Torr or less, and a low concentration of dope When using amorphous silicon, a low pressure chemical vapor deposition (LPCVD) method using SiH ₄ or Si ₂ H ₆ as a source gas is carried out at a temperature of 510 to 550 ° C. and a pressure of 3 Torr or less, and a P-type impurity ion is 1.0. In-situ doping is carried out at low concentrations of up to E20 atoms / cc.

FIG. 7 shows that the silicon spacer 8 is etched entirely so that silicon spacers 8A are formed on sidewalls of the second oxide film 7, that is, on both sides of the patterned first polysilicon layer 4. As a cross-sectional view, if the upper shape of the spacer 8A becomes a sharp horn, it may be damaged during the subsequent process, so that the thickness of the silicon film 8 should be controlled sufficiently thick.

FIG. 8 shows the second oxide film 7 and the surface using piranha (PIRANHA (H ₂ SO ₄ / H ₂ O ₂ )) and DHF (diluted with HF: H ₂ O = 50 to 100: 1) solution. After removing the remaining natural oxide film (not shown), a process of forming a Selective Metastable Poly Silicon (SMPS) is performed so that the surface of the silicon spacer 8A has an uneven structure and then the silicon spacer 8A. ) Is a cross-sectional view of the in-situ plasma PH ₃ heat-treated to have conductivity.

The selective metastable polysilicon forming process includes loading the semiconductor substrate into a device at a temperature of 550 to 560 ° C. to heat up for a predetermined time, and a silicon source such as SiH ₄ and Si ₂ H _6. Si seeds are formed on the surface of the silicon spacer 8A or silicon grains present in the silicon spacer 8A are grown by flowing a gas in an amount of 10 to 100 sccm. The heat treatment is performed such that the surface is a concave-convex structure by the migration of silicon atoms. The density and size of the grains are improved by minimizing the transfer time of silicon (Si) atoms during the heat treatment. , Growth is promoted.

The silicon (Si) seeds are selectively grown on the surface of undoped or low concentration of dope amorphous silicon having a selectivity superior to that of polysilicon or a semiconductor substrate. However, in this case, in order to prevent deposition of polysilicon having a thickness of several tens of micrometers on the exposed semiconductor substrate, the seed formation time should be minimized.

In addition, the heat treatment is performed using a high frequency power (RF Power) at a pressure of 10 ^-7 Torr or less and a temperature condition of 620 to 670 ℃, the high frequency power 30 to 100 watts (W) in the exposed portion of the semiconductor substrate Adjust low to minimize doping.

The selective metastable polysilicon forming process as described above is performed in a single wafer type chemical vapor deposition (CVD) apparatus having two chambers. Therefore, the selective metastable polysilicon forming process as described above is performed in one equipment.

FIG. 9 shows natural oxide films and particles produced by a cleaning process using DHF (diluted with HF: H ₂ O = 50 to 100: 1) and SC-1 (NH ₄ OH / H ₂ O ₂ / H ₂ O) solution. After removing the particles, the dielectric film 9 is formed on the entire upper surface of the patterned first polysilicon layer 4 and the floating gate 4A including the silicon spacer 8A having a concavo-convex structure. As a cross-sectional view of the state, the dielectric film 9 is formed in an ONO structure composed of a lower oxide film (SiO ₂ ), a nitride film (Si ₃ N ₄ ), and an upper oxide film (SiO ₂ ), and the dielectric film 9 is formed. Immediately afterwards, a steam heat treatment (wet oxidation) process is performed at a temperature of 750 to 790 ° C. to enhance the interfacial properties between the films.

The lower and upper oxide films are a low pressure thermal oxide film using DCS (SiH ₂ Cl ₂ ) and N ₂ O having good time dependent dielectric breakdown (TDDB) characteristics as a source gas under a pressure of 0.5 Torr or less and a temperature condition of 810 to 850 ° C. It is formed by depositing by chemical vapor deposition (LPCVD) method, the nitride film is deposited by low pressure chemical vapor deposition (LPCVD) method using NH ₃ and DCS (SiH ₂ Cl ₂ ) as the source gas.

FIG. 10 is a cross-sectional view of sequentially forming a second polysilicon layer 10 and a metal silicide layer 11 on the entire upper surface, wherein the second polysilicon layer 10 is a undoped polysilicon layer and an undoped layer. It is made of a polysilicon film, the metal silicide layer 11 is made of tungsten silicide (WSix).

The second polysilicon layer 10 is formed in a double structure so as not to increase the thickness of the oxide layer forming the dielectric layer 9 by diffusion of fluorine (F) when the metal silicide layer 11 is formed. First, a dope polysilicon film was formed by low pressure chemical vapor deposition (LPCVD) using a silicon source gas such as SiH ₄ or Si ₂ H ₆ and a PH ₃ gas at a temperature of 510 to 550 ° C. and a pressure of 1 Torr or less. Afterwards, the supply of the PH ₃ gas is stopped so that the undoped polysilicon film is deposited on the doped polysilicon film. At this time, the deposition ratio of the doped polysilicon film and the undoped polysilicon film is 5 to 7: 1, and the total thickness is to be 500 to 1000Å.

In addition, the tungsten silicide (WSix) is to be deposited by the reaction of fluorine (F) concentration and low stress (Stress) and high adhesion DCS (SiH ₂ Cl ₂ ) and WF ₆ at a temperature of 300 to 500 ℃, The stoichiometric ratio is adjusted to about 2.0 to 2.8 so that the self-resistance (Rs) is minimized by good layer covering.

Subsequently, an antireflection film (not shown) is formed on the metal silicide layer 11 using SiOxNy or Si ₃ N ₄ , and the metal silicide layer 11 and the second polysilicon layer 10 are formed by a photolithography and an etching process. Patterning to form the control gate.

As described above, in the present invention, after forming a polysilicon pattern, silicon spacers are formed on both sides thereof, and a selective metastable polysilicon forming process is performed so that the surface of the silicon spacer has an uneven structure. Therefore, as the surface area of the floating gate is increased, the capacitance between the floating gate and the control gate is increased, thereby increasing the coupling ratio of the memory cell to 0.9 or more.

Therefore, in the present invention, first, the memory cell can be programmed and erased using a low voltage, such as a power supply voltage. Second, the size of the memory cell can be reduced by increasing the coupling ratio. It becomes possible to manufacture the device which has). Third, since the formation of the high voltage transistor is not necessary, the thickness of the gate oxide film can be unified, thereby simplifying the process to increase the yield of the device, and fourth, the construction of the additional circuit for generating the high voltage is omitted. Easy to design

Claims (26)

Sequentially forming a tunnel oxide film, a first polysilicon layer, a first oxide film, and a nitride film on a semiconductor substrate having a field oxide film formed thereon; Sequentially patterning the nitride film, the first oxide film, the first polysilicon layer, and the tunnel oxide film; Forming a second oxide film on the entire upper surface and polishing the second oxide film until the nitride film is exposed by a chemical mechanical polishing process to planarize the surface; Removing the remaining nitride film and the second oxide film sequentially and forming silicon spacers on both sides of the patterned first polysilicon layer; Removing the second oxide film and the natural oxide film remaining on the surface, and then performing a selective metastable polysilicon forming process to make the surface of the silicon spacer into an uneven structure, and then heat treating the silicon spacer to have conductivity; Forming a dielectric film on the entire upper surface including the floating gate including the first polysilicon layer and the silicon spacer, and sequentially forming a second polysilicon layer and a metal silicide layer on the dielectric film; And patterning the metal silicide layer and the second polysilicon layer sequentially to form a control gate. The method of claim 1, And cleaning the surface of the semiconductor substrate using a DHF and SC-1 solution prior to forming the tunnel oxide film. The method of claim 1, The tunnel oxide film is subjected to a wet oxidation process using hydrogen (H ₂ ) and oxygen (O ₂ ) at a temperature of 750 to 800 ° C .; Method of manufacturing a flash memory cell, characterized in that formed by a heat treatment for 20 to 30 minutes at a temperature of 900 to 910 ℃ and nitrogen (N ₂ ) gas atmosphere. The method of claim 1, The tunnel oxide film is a method of manufacturing a flash memory cell, characterized in that formed in a thickness of 50 to 100Å. The method of claim 1, The first polysilicon layer is made of doped polysilicon, the method of manufacturing a flash memory cell, characterized in that formed in a thickness of 500 to 1500Å. The method of claim 5, The doped polysilicon is deposited by low pressure chemical vapor deposition using a silicon source gas of any one of SiH ₄ and Si ₂ H ₆ at a temperature of 550 to 620 ℃ and a pressure of 0.1 to 3.0 Torr Method of manufacturing a memory cell. The method of claim 1, The first oxide film is any one of a thermal oxide film, a DCS (SiH ₂ Cl ₂ ) -thermal oxide film and a CVD oxide film using TEOS, the method of manufacturing a flash memory cell, characterized in that formed in a thickness of 50 to 100 내지. The method of claim 7, wherein The thermal oxide film is formed by dry oxidation at a temperature of 750 to 950 ° C., and the DCS (SiH ₂ Cl ₂ ) -thermal oxide film is SiH ₂ Cl ₂ and N ₂ at a pressure of 1 Torr or less and a temperature of 750 to 850 ° C. A method of manufacturing a flash memory cell, characterized in that it is formed by O gas. The method of claim 1, The nitride film is formed by low pressure chemical vapor deposition using NH ₃ and DCS (SiH ₂ Cl ₂ ) gas at a temperature of 730 to 780 ° C. and a pressure of 1 Torr or less, and has a thickness of 1500 to 2500 kPa. Method of manufacturing a memory cell. The method of claim 1, The second oxide film is made of a high density plasma oxide film, the method of manufacturing a flash memory cell, characterized in that formed in a thickness of 5000 to 10000 내지. The method of claim 1, And the nitride film is removed with a H ₃ PO ₄ solution. The method of claim 1, And the second oxide film is removed with a DHF solution. The method of claim 1, And the silicon film is one of undoped amorphous silicon and low concentration of doped amorphous silicon. The method of claim 13, The undoped amorphous silicon is formed by low pressure chemical vapor deposition using any one of SiH ₄ and Si ₂ H ₆ at a temperature of 510 to 550 ° C. and a pressure of 3 Torr or less, and the doped amorphous silicon of the low concentration. Is deposited by low pressure chemical vapor deposition using a silicon source gas at a temperature of 510 to 550 ° C. and a pressure of 3 Torr or less, and then in-situ doped to a concentration of 1.0E20 atoms / cc or less. Manufacturing method. The method of claim 1, And the second oxide film and the native oxide film are removed with piranha and DHF solution. The method of claim 1, The selective metastable polysilicon forming process may include loading and heating the semiconductor substrate into equipment at a temperature of 550 to 560 ° C .; Flowing silicon source gas in an amount of 10 to 100 sccm and allowing silicon seeds to be formed on the surface of the silicon spacers or silicon grains present in the silicon spacers to grow; Plasma heat treatment is carried out so that the surface may become an uneven structure by the movement of a silicon atom, The manufacturing method of the flash memory cell characterized by the above-mentioned. The method of claim 16, The plasma heat treatment is performed at a pressure of 10 ⁻⁷ Torr or less and a temperature condition of 620 to 670 ° C. A method of manufacturing a flash memory cell. The method of claim 1, The method of claim 1, further comprising the step of cleaning using DHF and SC-1 solution to remove the native oxide film and particles before forming the dielectric film. The method of claim 1, The dielectric film may be formed by sequentially forming a lower oxide film, a nitride film, and an upper oxide film; A method of manufacturing a flash memory cell, characterized by the step of steam heat treatment at a temperature of 750 to 790 ℃ to enhance the interfacial properties between the films. The method of claim 19, The lower and upper oxide films are thermal oxide films deposited by a low pressure chemical vapor deposition method using DCS and N ₂ O as a source gas at a pressure of 0.5 Torr or less and a temperature of 810 to 850 ° C. Way. The method of claim 19, The nitride film is a method of manufacturing a flash memory cell, characterized in that deposited by a low pressure chemical vapor deposition method using NH ₃ and DCS as the source gas. The method of claim 1, The second polysilicon layer is made of a doped polysilicon film and an undoped polysilicon film, the total thickness is a manufacturing method of a flash memory cell, characterized in that 500 to 1000Å. The method of claim 1, Forming the doped polysilicon layer using a low pressure chemical vapor deposition method using a silicon source gas and a PH ₃ gas at a temperature of 510 to 550 ° C. and a pressure of 1 Torr or less; And depositing an undoped polysilicon film on the doped polysilicon film while the supply of the PH ₃ gas is stopped. The method of claim 23, And a deposition ratio of the doped polysilicon film and the undoped polysilicon film is 5 to 7: 1. The method of claim 1, The metal silicide layer is made of tungsten silicide (WSix). The method of claim 25, The tungsten silicide (WSix) is deposited by the reaction of DCS and WF ₆ at a temperature of 300 to 500 ℃, the stoichiometric ratio is a method of manufacturing a flash memory cell, characterized in that adjusted to 2.0 to 2.8.