CN1209811C

CN1209811C - A Method for Reducing Random Bit Faults in Flash Memory

Info

Publication number: CN1209811C
Application number: CN02107299.XA
Authority: CN
Inventors: 黄文信; 张国华
Original assignee: Macronix International Co Ltd
Current assignee: Macronix International Co Ltd
Priority date: 2002-03-29
Filing date: 2002-03-29
Publication date: 2005-07-06
Anticipated expiration: 2022-03-29
Also published as: CN1449023A

Abstract

A method for reducing random bit failures in a flash memory, comprising the steps of: providing a semiconductor substrate; forming a stack layer on the channel region of the substrate; performing ion implantation to form a buried source and a drain; oxidizing the substrate in the stacked layer and the bit line region to simultaneously form an in-situ vapor growth film on the surfaces of the polysilicon layer and the sacrificial layer; depositing a dielectric layer to cover the channel region and the bit line region, wherein the thickness of the dielectric layer on the bit line region is larger than that of the polysilicon layer but smaller than that of the stacked layer; removing a portion of the dielectric layer and a portion of the in-situ vapor grown film over the channel region and the bit line region to expose a portion of the sacrificial layer; and completely removing the sacrificial layer; the in-situ steam growth film can strengthen and protect the interface between the dielectric layer and the polysilicon layer, and avoid acid corrosion gap between the interface between the dielectric layer and the polysilicon layer during the acid soaking and cleaning process.

Description

A kind of method that reduces random bit failure of flash memory

Technical field

The present invention provides a kind of high grid coupling efficiency (gate coupling ratio that has, GCR) and the manufacture method of the flash memory of high reliability (reliability), especially refer to a kind of random bit failure (randombit failure) that is produced when utilizing an ISSG (in-situsteam growth) film to make flash memory, and improve the method for reliability of flash memory to reduce simultaneously.

Background technology

In recent years, along with the increase in demand of Portable (portable) electronic product, also increasingly mature expansion is used in the technology of quickflashing (flash) memory and market.These portable electronic products include egative film, mobile phone, game machine (video game apparatus), personal digital assistant (personal digitalassistant, memory PDA), telephone answering and recording device and programmable IC or the like of digital camera.Flash memory is a kind of non-volatility memorizer (non-volatile memory), its operation principles be control the grid passage by the threshold voltage (threshold voltage) that changes transistor or memory cell switch to reach the purpose of storage data, the data that are stored in the memory can not disappeared because of power interruptions.

Generally, the gate junction structure of flash memory is configured to two types, and a kind of is stack type grid (stacked-gate), and another kind is separable grid (split-gate).The stack type grid flash memory comprises that mainly a floating grid (floating gate) and that is used for store charge is used for the control grid (control gate) of control data access and is stacked on the floating grid, and isolates by the dielectric layer and the floating grid of an ONO (oxide-nitride-oxide) structure.So memory can utilize the principle of similar electric capacity, charge inducing is stored in the stack type grid, make memory deposit signal " 1 " in.Change the data in the memory if desired, only need resupply a little extra energy, erasing is stored in electronics in the floating grid, just can carry out data more again and write.

Please refer to Fig. 1 to Fig. 4, Fig. 1 to Fig. 4 makes the method schematic diagram of a dibit (dual bit) stack type grid flash memory for prior art.At first, as shown in Figure 1, semiconductor wafer 10 comprises a silicon base 12, be located on the silicon base 12 by an oxidation (field oxide) layer 14 active region of being isolated (active area) 11, and two grid structures 21 is located in the active region 11.Grid structure 21 has a grid oxic horizon 16 to be located on silicon base 12 surfaces, and a polysilicon layer 18 is located on the grid oxic horizon 16, and a silicon nitride layer 20 is located on the polysilicon layer 18.

As shown in Figure 2, carry out an ion and inject manufacture process, the silicon base 12 surface doping ions beyond grid structure 21.Carry out an oxidation manufacture process then, make dopant ion be activated diffusion, form an ion diffusion layer 22, be used as flash memory bury the drain electrode with source electrode (buried drainand source, BD/BS).Simultaneously, on ion diffusion layer 22, can form a thermal oxide layer or be called BD/BS oxide layer 24.As shown in Figure 3, subsequently nitrogen silicon layer 20 is removed fully, and on the polysilicon layer 18 on semiconductor wafer 10 surfaces, formed a polysilicon layer 26.Wherein polysilicon layer 18 forms a floating grid 28 with the polysilicon layer 26 that covers thereon.

Subsequently, as shown in Figure 4, the dielectric layer 30 that formation one is made up of ONO (oxide-nitride-oxide) structure on each floating grid surface, it comprises one first oxide layer (not shown), one nitration case (not shown) is located on first oxide layer, and one second oxide layer (not shown) is located on the nitration case.Go up in semiconductor wafer 10 surfaces more at last and form a polysilicon layer 32, make it cover the surface of dielectric layer 30 and thermal oxide layer 24.Polysilicon layer 32 is intended for this non-volatility memorizer control grid of (or claiming permanent memory).

Because prior art manufacture process method is to utilize the high-temperature thermal oxidation manufacture process, form thermal oxide layer 24 to go up in silicon base 12 surfaces, cause the thickness of thermal oxide layer 24 to become inhomogeneous in the extreme, and can destroy the lattice structure on silicon base 12 surfaces, obviously influence the reliability of flash memory.And, the thermal oxidation manufacture process that is used for forming thermal oxide layer 24 also can excessively become to being doped in the ion in drain electrode and the source electrode, and then floating grid 28 passage lengths have relatively been shortened, even cause generation abnormal electrical perforation (punch through) between drain electrode and source electrode, or cause short-channel effect to worsen more.In addition, the formed memory construction of art methods exists grid coupling efficiency (gate coupling ratio, GCR) Bu Zu problem.

Summary of the invention

Therefore, main purpose of the present invention promptly is to provide a kind of manufacture method of high GCR piled grids non-volatility memorizer, has an ISSG film, can effectively improve the reliability of memory.

Another object of the present invention promptly is to provide a kind of manufacture method of flash memory, not only can avoid the elevated temperature heat manufacture process to cause the uneven problem of BD/BS oxidated layer thickness, and can accurately control each passage length that is formed at the stack type grid on the semiconductor wafer and BD/BS thickness of oxide layer, and then dwindle each component size effectively, and increase the reliability of this kind element.

Another object of the present invention promptly in the process of making flash memory, utilizes an ISSG film effectively to prevent the acid accumulator penetration phenomenon, can reduce because acid solution corrodes the random bit failure (random bitfailure) that is produced.

According to the preferred embodiment of the inventive method, the inventive method comprises following key step:

(1) provides a substrate, comprise a passage area and a bit line zone;

(2) on the passage area of this substrate, form a stack layer, wherein this stack layer comprise a polysilicon layer and a sacrifice layer be formed at this polysilicon layer directly over;

(3) this substrate in this stack layer of oxidation and this bit line zone is to form an ISSG film simultaneously on this polysilicon layer and this sacrificial layer surface;

(4) deposition one dielectric layer on this ISSG film covers this passage area and this bit line zone, and wherein this medium thickness on this bit line zone is greater than this polysilicon layer thickness, but less than this stack layer thickness;

(5) part is removed this dielectric layer and this ISSG film, to expose this sacrifice layer of part; And

(6) remove this sacrifice layer fully.

The inventive method can obviously increase the control grid of follow-up formation and the capacity area between the floating grid, make GCR improve about 60 to 70%, and then the electrical performance (electricperformance) of raising memory, and the energy consume (energy dissipation) of reduction flash memory.And the interface of this dielectric layer and this polysilicon layer can be strengthened and protect to this ISSG film, avoids the interface of this dielectric layer and this polysilicon layer to clean manufacture process or produce an acid attack slit (acid-corroded seam) phenomenon in the process of this dielectric layer of wet etching in this acid soak.In addition, form the employed ISSG technology of ISSG film and can not cause the doping profile of BD/BS obviously to change, therefore can keep the electrically stable and high integration of memory component.

Description of drawings

Fig. 1 to Fig. 4 makes the method schematic diagram of stacked type grid fast-flash memory for prior art; And

Fig. 5 to Figure 11 is the generalized section of making a high grid coupling efficiency flash memory cells in the inventive method preferred embodiment.

The symbol description of accompanying drawing

10 semiconductor wafers, 11 active regions

12 silicon base, 14 field oxides

16 grid oxic horizons, 18 polysilicon layers

20 silicon nitride layers, 21 grid structures

22 ion diffusion layer 24BD/BS oxide layers

26 polysilicon layers, 28 floating grids

30 dielectric layers, 32 polysilicon layers

100 semiconductor wafers, 110 active regions

113 passage area, 115 bit line zones

120 silicon base, 160 tunnel oxides

180 polysilicon layers, 200 sacrifice layers

210 grid structures, 212 arsenic ions inject manufacture process

220 bury drain electrode and source electrode 230ISSG film

240HDP oxide layer 240a first

240b second portion 252 projections structure

260 polysilicon layers, 280 floating grids

290 ONO dielectric layers, 300 control grids

Embodiment

Please refer to Fig. 5 to Figure 11, Fig. 5 to Figure 11 is the generalized section of making high grid coupling efficiency (GCR) flash memory cells in the inventive method preferred embodiment.The present invention for convenience of description, Fig. 5 to Figure 11 only show the part flash memory zone relevant with the inventive method.Be to be the example explanation in the preferred embodiment of the inventive method with a dibit flash memory cells.At first, as shown in Figure 5, semiconductor wafer 100 comprises a silicon base 120, by a shallow isolating trough (shallow trench isolation, STI) zone 140 active regions of being isolated (active area) 110 are located on the silicon base 120, and two grid structures 210 are located in the active region 110.Grid structure 210 has a grid oxic horizon or is called tunnel oxide 160 to be located on silicon base 120 surfaces, a polysilicon layer or be called PL1 layer 180 and be located at tunnel oxide 160 tops, and a sacrifice layer 200 is located at polysilicon layer 180 tops.As shown in Figure 5, grid structure 210 is further divided into a passage area 113 and a bit line zone 115 with active region 110.

In a preferred embodiment of the invention, silicon base 120 is that a P type mixes and to have＜monocrystal silicon substrate of 100〉lattice arrangement directions.Yet the present invention is not limited thereto, and silicon base 120 can also (silicon-on-insulator, SOI) substrate, extension (epitaxy) silicon base or other have the silicon base of different crystalline lattice orientation for a Silicon-On-Insulator.In this preferred embodiment, the thickness of tunnel oxide 160 is about 90 to 120 dusts, and (angstrom A), is preferably 95 dusts.The thickness of polysilicon layer 180 is about 1000 dusts.The thickness of sacrifice layer 200 is about 1800 to 1950 dusts, is preferably 1925 dusts.Sacrifice layer 200 is to utilize a chemical vapour deposition (CVD) (chemical vapor deposition, CVD) manufacture process is utilized dichlorosilane (SiH ₂Cl ₂) and ammonia (NH ₃) be reacting gas, form down at 750 ℃.180 of polysilicon layers are to utilize silane (SiH ₄) be reacting gas, form 620 ℃ of deposit, (after-etch-inspect critical dimension, AEICD), promptly the floating grid passage length is about 0.34 micron to the critical dimension of polysilicon layer 180 after etching.

As shown in Figure 6, then carry out an arsenic ion and inject manufacture process 212, with silicon base 120 surfaces beyond grid structure 210, it is bit line zone 115, the arsenic doped ion, to form a doped region 220, be used as flash memory bury drain electrode and source electrode (buried drain and source, BD/BS) or be called bit line.In a preferred embodiment of the invention, it is to utilize energy to be 50KeV that arsenic ion injects manufacture process 212, and dosage is about 1 * 10 ¹⁵Cm ^-2Arsenic ion carry out ion and inject.Subsequently, (rapid thermal processing RTP) is implanted in the arsenic ion on silicon base 120 surfaces with activation to carry out a rapid thermal treatment.

Then, as shown in Figure 7, carry out an oxidation manufacture process that contains oxygen radical and hydroxyl free radical, with simultaneously in silicon nitride sacrifice layer 200 surfaces, polysilicon layer 180 surfaces, and form an ISSG (in-situ steam generation or in-situ steam growth) film 230 at silicon base 120 surface oxidations.The thickness of ISSG film 230 is between 80 to 300 dusts, preferably then between 100 to 150 dusts.Subsequently, carry out a high density plasma chemical vapor deposition (high-density plasma chemicalvapor deposition again, HDPCVD) manufacture process to deposit the HDP oxide layer 240 that a thickness is about 2000 to 3000 dusts, is covered on the ISSG film 230.Wherein HDP oxide layer 240 covers and fills up passage area 113 and bit line zone 115, and HDP oxide layer 240 thickness on the bit line zone 115 need the thickness greater than polysilicon layer 180, but less than the thickness of piled grids 210.

At this moment so-called ISSG film 230 is to utilize one to be called situ steam and to grow up that (in-situ steamgrowth, ISSG) technology forms.Situ steam growth (ISSG) technology is a kind of low pressure wet type rapid thermal oxidation method with high reproducibility.Situ steam growth (ISSG) technology can be carried out in single wafer RTP reactor, the RTP XEplus Centura type of Applied Materials (Applied Materials Co.) for example, its top disposes 15 to 25 tungsten filament halogen heating fluorescent tube tungstenhalogen lamp that are arranged in parallel), fast wafer is warming up to desired high temperature.

In a preferred embodiment of the invention, ISSG film 230 is to feed total flow in an XEplus Centura type RTP reactor (total gas flow rate TGF) is about under the condition of the hydrogen of 10SLM and oxygen and forms.Hydrogen flowing quantity ratio (%H wherein ₂Of TGF) be 2%, the pressure of RTP reactor should be controlled in and be lower than below the 20Torr, preferably then is 10.5Torr.In the process of reaction, silicon base 120 is quickly heated up to 1000 ℃ to 1200 ℃ by tungsten filament halogen heating fluorescent tube, is preferably 1150 ℃, and maintains this temperature about 20 to 25 seconds.Because reaction pressure is controlled under the following low pressure of 20Torr, therefore the quick oxidation reaction of this ISSG high temperature is to carry out under a mass transport state of a control (mass transportcontrolled regime), and the change of pressure can directly have influence on quality transmission rate in the oxidizing process (mass transport rate).Because the heating time of ISSG technology is short, therefore can not influence the concentration profiles of doped region 220.

As shown in Figure 8, then carry out a wet etching manufacture process, utilize a dilute hydrofluoric acid (diluted HF, DHF) or buffer oxide etch liquid (buffered oxide etcher, BOE) the ISSG layer 230 of the HDP oxide layer 240 of etching part and part is to expose the sacrifice layer 200 of part.In a preferred embodiment of the invention, be about 650 to 900 dusts, be preferably the 700 Izod right sides by HDP oxide layer 240 thickness of eating away.At this moment, be divided into two parts that are not connected through the HDP oxide layer 240 after the acid etching, wherein first part 240a be positioned at sacrifice layer 200 directly over, second part 240b then is positioned at grid 210 sides.Because ISSG layer 230 has been strengthened the interface between HDP oxide layer 240 and the polysilicon layer 180, therefore the infiltration of employed acid solution (DHF) in the time of can effectively blocking etching HDP oxide layer 240, and then avoid producing acid attack slit (acid-corroded seam) phenomenon.

Then, as shown in Figure 9, utilize one to be heated to the sacrifice layer 200 that about 160 ℃ hot phosphoric acid solution is removed polysilicon layer 180 tops fully.When removing sacrifice layer 200, be positioned at sacrifice layer 200 directly over the HDP oxide layer 240a of first also be accompanied by and be removed.After removing sacrifice layer 200, the second portion 240b of original HDP oxide layer 240 is promptly forming projection structure 252 near polysilicon layer 180 places.This special projection structure 252 can increase grid coupling efficiency (GCR) about about 60 to 75%.As shown in figure 10, on polysilicon layer 180, form a polysilicon layer 260 subsequently, and make polysilicon layer 260 be in electrical contact with polysilicon layer 180, to be used as a floating grid 280.

At last, as shown in figure 11, on floating grid 280 surfaces, form a dielectric layer 290 in regular turn.Dielectric layer 290 is the ONO structures that are made of oxide layer (not shown) on a bottom oxide (not shown), the nitration case (showing demonstration) and.Go up in semiconductor wafer 100 surfaces again and form a polysilicon layer 300, be used as a control grid.Wherein the dielectric layer of floating grid, ONO structure and control grid just form the stack type grid of a non-volatility memorizer.Because the those skilled in the art that is made as of ONO dielectric layer 290 and control grid knows, therefore repeat no more its detailed step.

The present invention makes the method for flash memory, in the manufacture process that can be applied to non-volatility memorizer (non-volatile memory), also can be used to make embedded flash memory (embedded flash) and dynamic random access memory (dynamic random access memory, the storage bottom electrode of capacity cell DRAM) (storage node).

Than the method that prior art is made flash memory, the marked improvement technical characterictic of the inventive method is: the HDP oxide layer 240b that (1) utilization is deposited on around the polysilicon layer 180 is used as the BD/BS oxide layer, so need not utilize the thermal oxidation manufacture process.Therefore utilize the thickness of the made BD/BS of method of the present invention, can be by the method for HDP CVD obtaining an effectively control, and then make be made in each stack type grid flash memory cells on the semiconductor wafer 100 electrically about equally; (2) the present invention utilizes wet etching mode etching HDP oxide layer 240, removes sacrifice layer 200 again.So can obtain projection structure 252, can significantly increase GCR; (3) the present invention utilizes the ISSG technology to form ISSG film 230, therefore direct wet etching HDP oxide layer 240, this is because ISSG layer 230 has been strengthened the interface between HDP oxide layer 240 and the polysilicon layer 180, therefore the infiltration of employed acid solution (DHF) in the time of can effectively blocking etching DHP oxide layer 240, and then avoid producing acid attack slit (acid-corroded seam) phenomenon.

The above only is the preferred embodiments of the present invention, and all equivalences of doing according to claim of the present invention change and modify, and all should belong to the covering scope of patent of the present invention.

Claims

1. A method for reducing flash memory random bit faults, the method may further comprise the steps:

A semiconductor substrate is provided, the surface of the substrate includes a channel region and a bit line region;

forming a stacked layer on the channel region of the substrate, wherein the stacked layer includes a gate oxide layer, a polysilicon layer, and a sacrificial layer formed directly above the polysilicon layer;

Oxidizing the stacked layer and the base in the bit line area to simultaneously form an in-situ vapor growth film on the surface of the polysilicon layer and the sacrificial layer;

Depositing a dielectric layer on the in-situ vapor growth film, covering the channel area and the bit line area, wherein the thickness of the dielectric layer on the bit line area is greater than the thickness of the polysilicon layer, but less than the thickness of the stack layer;

removing a portion of the dielectric layer and a portion of the in situ vapor grown film over channel regions and bit line regions to expose a portion of the sacrificial layer; and

complete removal of the sacrificial layer;

Wherein the in-situ vapor growth film can strengthen and protect the interface between the dielectric layer and the polysilicon layer, avoiding an acid erosion crevice phenomenon in the interface between the dielectric layer and the polysilicon layer during the acid solution immersion cleaning manufacturing process.

2. The method of claim 1, wherein the in-situ vapor growth film is formed by an in-situ vapor growth technique.

3. The method of claim 1, wherein the dielectric layer is a high density plasma oxide layer.

4. The method of claim 1, wherein the surface of the substrate further comprises a doped region disposed in the substrate in the bit line region for serving as a buried source/drain.

5. The method of claim 1, wherein the sacrificial layer is formed of silicon nitride.

6. The method of claim 1, wherein the method of partially removing the dielectric layer and the in-situ vapor growth film is using a dilute hydrofluoric acid or a buffered oxide etchant.

7. The method of claim 1, wherein the method of removing the sacrificial layer utilizes a hot phosphoric acid solution.

8. The method of claim 1, wherein the acid soak cleaning process comprises a dilute hydrofluoric acid solution.

9. The method of claim 1, wherein the substrate is a silicon substrate.

10. The method of claim 1, wherein the thickness of the in-situ vapor grown film is between 50 and 250 angstroms.