KR102900856B1 - Printed circuit board and mehod of manufacturing thereof - Google Patents

Abstract

A printed circuit board according to an embodiment includes a first insulating layer; and a first circuit pattern layer disposed on an upper surface of the first insulating layer, wherein the first insulating layer includes a first region corresponding to a dummy region and a second region other than the first region, and the first circuit pattern layer includes a first dummy pattern disposed in the first region of the first insulating layer, and the first dummy pattern includes a plurality of first openings in the form of dots that are spaced apart from each other and expose an upper surface of the first region of the first insulating layer.

Description

Printed circuit board and method of manufacturing the same

The embodiment relates to a printed circuit board and a method for manufacturing the same.

As electronic components become increasingly miniaturized, lightweight, and integrated, circuit line widths are shrinking. In particular, as semiconductor chip design rules are becoming more integrated at the nanometer scale, the circuit line widths of the package substrates or printed circuit boards that mount the semiconductor chips are shrinking to a few micrometers or less.

To increase the circuit density of printed circuit boards (PCBs), i.e., to minimize line widths, various techniques have been proposed. To prevent line width loss during the etching process to form patterns after plating, techniques such as the semi-additive process (SAP) and the modified semi-additive process (MSAP) have been proposed.

Since then, the Embedded Trace Substrate (ETS) method, which buries copper foil within an insulating layer to implement finer circuit patterns, has been used in the industry. The ETS method manufactures copper foil circuits by burying them within the insulating layer instead of forming them on the surface of the insulating layer, thereby eliminating circuit loss due to etching and thus being advantageous for minimizing circuit pitch.

Meanwhile, the printed circuit board described above forms a metal layer through electroless chemical copper plating for miniaturization. The metal layer formed through electroless chemical copper plating can be used to form a circuit pattern layer.

However, conventional printed circuit boards, such as the above, can have reliability issues due to residual alkaline gases remaining at the interface between the insulating layer and the metal layer. For example, conventional printed circuit boards are vulnerable to thermal stress caused by the residual alkaline gases, and poor bonding strength can occur, resulting in the metal layer detaching from the insulating layer.

In an embodiment, a printed circuit board and a method for manufacturing the same are provided, which can remove a basic gas remaining between an insulating layer and a circuit pattern layer.

In addition, the embodiment provides a printed circuit board and a method for manufacturing the same that can improve bonding strength between an insulating layer and a circuit pattern layer.

In addition, the embodiment provides a printed circuit board and a manufacturing method thereof capable of improving plating deviation of a circuit pattern layer.

The technical tasks to be achieved in the proposed embodiment are not limited to the technical tasks mentioned above, and other technical tasks not mentioned can be clearly understood by a person having ordinary skill in the technical field to which the proposed embodiment belongs from the description below.

A printed circuit board according to an embodiment includes a first insulating layer; and a first circuit pattern layer disposed on an upper surface of the first insulating layer, wherein the first insulating layer includes a first region corresponding to a dummy region and a second region other than the first region, and the first circuit pattern layer includes a first dummy pattern disposed in the first region of the first insulating layer, and the first dummy pattern includes a plurality of first openings in the form of dots that are spaced apart from each other and expose an upper surface of the first region of the first insulating layer.

In addition, the printed circuit board includes a second insulating layer disposed on an upper surface of the first insulating layer; and a second circuit pattern layer disposed on an upper surface of the second insulating layer, wherein the second insulating layer is formed on the first insulating layer to fill the plurality of first openings.

Additionally, the second circuit pattern layer includes a second dummy pattern arranged in a dummy area of the second insulating layer, and the second dummy pattern includes a plurality of second openings in the form of dots that are spaced apart from each other and expose an upper surface of the dummy area of the second insulating layer.

Additionally, the diameter of each of the plurality of first openings is greater than 100 μm.

Additionally, the spacing between adjacent first openings among the plurality of first openings is greater than 25 μm.

Meanwhile, a printed circuit board according to another embodiment includes a first insulating layer; a first circuit pattern layer disposed on an upper surface of the first insulating layer; and a first degassing portion formed on the first insulating layer and the first circuit pattern layer, wherein the first insulating layer includes a first region corresponding to a dummy region and a second region other than the first region, the first circuit pattern layer includes a first dummy pattern disposed in the first region of the first insulating layer, and the first degassing portion includes a plurality of 1-1 portions in the form of dots that are formed by opening the first dummy pattern and are spaced apart from each other, and a 1-2 portion that is formed by opening the first insulating layer and is connected to the 1-1 portions.

In addition, the printed circuit board includes a second insulating layer disposed on an upper surface of the first insulating layer; and a second circuit pattern layer disposed on an upper surface of the second insulating layer, wherein the second insulating layer is formed on the first insulating layer to fill the first-1 portion and the first-2 portion of the first degassing portion.

In addition, the first-second portion of the first degassing section is formed by penetrating the first insulating layer.

In addition, the first-second portion of the first degassing section is formed without penetrating the first insulating layer.

In addition, the printed circuit board includes a second degassing portion formed on the second insulating layer and the second circuit pattern layer, the second circuit pattern layer includes a second dummy pattern arranged in a dummy area of the second insulating layer, and the second degassing portion includes a plurality of 2-1 portions in the form of dots that are formed by opening the second dummy pattern and are spaced apart from each other, and a 2-2 portion that is formed by opening the second insulating layer and is connected to the 2-1 portion.

In addition, the diameter of the first-1 portion of the first degassing section is greater than 100 μm.

Additionally, the gap between adjacent 1-1 parts among the plurality of 1-1 parts of the first degassing section is greater than 25 μm.

Meanwhile, a method for manufacturing a printed circuit board according to an embodiment includes preparing a first insulating layer, forming a first circuit pattern layer on an upper surface of the first insulating layer, and forming a first degassing portion that opens the first insulating layer and the first circuit pattern layer, wherein the first insulating layer includes a first region corresponding to a dummy region and a second region other than the first region, the first circuit pattern layer includes a first dummy pattern arranged in the first region of the first insulating layer, and the first degassing portion includes a plurality of 1-1 portions in the form of dots that are formed by opening the first dummy pattern and are spaced apart from each other, and a 1-2 portion that is formed by opening the first insulating layer and is connected to the 1-1 portions.

In addition, it includes forming a second insulating layer on the upper surface of the first insulating layer and forming a second circuit pattern layer disposed on the upper surface of the second insulating layer, wherein the second insulating layer fills the first-1 portion and the first-2 portion of the first degassing section.

In addition, the first-second portion of the first degassing section is formed by penetrating the first insulating layer.

In addition, the first-second portion of the first degassing section is formed without penetrating the first insulating layer.

In addition, it includes forming a second degassing portion on the second insulating layer and the second circuit pattern layer, wherein the second circuit pattern layer includes a second dummy pattern arranged in a dummy area of the second insulating layer, and the second degassing portion includes a plurality of 2-1 portions in the form of dots that are formed by opening the second dummy pattern and are spaced apart from each other, and a 2-2 portion that is formed by opening the second insulating layer and is connected to the 2-1 portion.
A circuit board according to an embodiment includes a first insulating layer; a first circuit pattern layer disposed on the first insulating layer; and a second insulating layer disposed on the first circuit pattern layer, wherein the first circuit pattern layer includes a first dummy through-hole penetrating an upper surface and a lower surface of the first circuit pattern layer, the first insulating layer includes a second dummy through-hole penetrating at least a portion of the first insulating layer and overlapping the first dummy through-hole penetrating along a vertical direction, and the second insulating layer includes a protrusion disposed within the first dummy through-hole penetrating and the second dummy through-hole penetrating.
Additionally, the first dummy through-hole includes a plurality of first dummy openings spaced apart from each other in a horizontal direction in the first circuit pattern layer, and the second dummy through-hole includes a plurality of second dummy openings overlapping the plurality of first dummy openings in the vertical direction.
Additionally, it further includes a first conductive via penetrating at least a portion of the first insulating layer along the vertical direction and spaced apart from the protrusion along the horizontal direction.
Additionally, the first conductive via and the protrusion overlap along the horizontal direction.
Additionally, at least a portion of the side surface of the protrusion has an inclination angle that is the same as an inclination angle of at least a portion of the side surface of the first conductive via.
Additionally, the horizontal width of the plurality of first dummy openings is greater than the horizontal spacing between the plurality of first dummy openings.
In addition, the second circuit pattern layer is disposed on the second insulating layer; and a third insulating layer is disposed on the second circuit pattern layer, wherein the second circuit pattern layer includes a third dummy through-hole that penetrates the upper and lower surfaces of the second circuit pattern layer, the second insulating layer includes a fourth dummy through-hole that overlaps the third dummy through-hole along the vertical direction and penetrates at least a portion of the second insulating layer, and the third insulating layer includes a protrusion disposed within the third dummy through-hole and the fourth dummy through-hole.
Additionally, the first to fourth dummy penetration portions overlap along the vertical direction.
Additionally, the protrusions of the first insulating layer and the protrusions of the second insulating layer overlap each other along the vertical direction.
In addition, it further includes a second conductive via penetrating the upper and lower surfaces of the second insulating layer, wherein the second conductive via is spaced apart from the protrusion of the second insulating layer along the horizontal direction.
Additionally, the slope of the side surface of the second conductive via is the same as the slope of the side surface of the protrusion of the second insulating layer.
Additionally, the slope of the inner wall of the first dummy penetration portion is different from the slope of the inner wall of the second dummy penetration portion.
Additionally, the slope of the inner wall of the first dummy penetration portion with respect to the lower surface of the first insulating layer is closer to vertical than the slope of the inner wall of the second dummy penetration portion with respect to the lower surface of the first insulating layer.

In an embodiment, a dummy pattern is formed in a first region (R1) corresponding to a dummy region of an insulating layer, and a plurality of openings having a dot shape are formed in the dummy pattern. In addition, the plurality of openings enable degassing of gas remaining in the insulating layer. Accordingly, in an embodiment, the reliability of a printed circuit board can be improved by removing gas between the insulating layer and the circuit pattern layer. For example, in an embodiment, by removing the gas remaining in the insulating layer, the thermal stress of the insulating layer can be minimized. For example, in an embodiment, by removing the gas remaining in the insulating layer, the reliability problem of the circuit pattern layer being detached from the insulating layer can be solved. In addition, in an embodiment, by including a plurality of openings in the dummy pattern as described above, the plating deviation of the circuit pattern layer can be improved by controlling the area of the dummy pattern.

In addition, in the embodiment, gas that has penetrated into the insulating layer can be completely removed, thereby further improving reliability. For example, in the embodiment, an opening for degassing can be formed not only in the dummy pattern but also in the insulating layer. For example, the opening for degassing includes a first portion formed in the dummy pattern and a second portion formed in the insulating layer and connected to the first portion. Accordingly, in the embodiment, even gas that has penetrated into the insulating layer can be completely removed, thereby further improving reliability.

Figure 1 is a drawing showing a printed circuit board according to the first embodiment.
Figure 2 is a plan view of some layers of a printed circuit board according to a comparative example.
Figure 3 is a plan view of some layers of a printed circuit board according to an embodiment.
Fig. 4 is a variation example of the shape of an opening formed in a dummy pattern according to an embodiment.
Figures 5 to 9 are drawings showing the manufacturing method of the printed circuit board illustrated in Figure 1 in process order.
Figure 10 is a drawing showing a printed circuit board according to the second embodiment.
Figures 11 to 14 are drawings showing the manufacturing method of the printed circuit board illustrated in Figure 10 in process order.

Hereinafter, embodiments disclosed in this specification will be described in detail with reference to the attached drawings. Regardless of the drawing numbers, identical or similar components will be given the same reference numbers, and redundant descriptions thereof will be omitted. The suffixes "module" and "part" used for components in the following description are assigned or used interchangeably only for the convenience of writing the specification, and do not in themselves have distinct meanings or roles. In addition, when describing the embodiments disclosed in this specification, if it is determined that a specific description of a related known technology may obscure the gist of the embodiments disclosed in this specification, a detailed description thereof will be omitted. In addition, the attached drawings are only intended to facilitate easy understanding of the embodiments disclosed in this specification, and the technical ideas disclosed in this specification are not limited by the attached drawings, and should be understood to include all modifications, equivalents, and substitutes included in the spirit and technical scope of the present invention.

Terms that include ordinal numbers, such as first, second, etc., may be used to describe various components, but the components are not limited by these terms. These terms are used solely to distinguish one component from another.

When a component is referred to as being "connected" or "connected" to another component, it should be understood that it may be directly connected or connected to that other component, but that there may be other components intervening. Conversely, when a component is referred to as being "directly connected" or "connected" to another component, it should be understood that there are no other components intervening.

Singular expressions include plural expressions unless the context clearly indicates otherwise.

In this application, terms such as “include” or “have” are intended to specify the presence of a feature, number, step, operation, component, part or combination thereof described in the specification, but should be understood not to exclude in advance the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts or combinations thereof.

FIG. 1 is a drawing showing a printed circuit board according to a first embodiment, FIG. 2 is a plan view of some layers of a printed circuit board according to a comparative example, and FIG. 3 is a plan view of some layers of a printed circuit board according to an embodiment.

Referring to FIGS. 1 to 3, the printed circuit board includes a first insulating layer (110), a second insulating layer (120), a third insulating layer (130), circuit pattern layers (140a, 140b, 150a, 150b, 160a, 160b, 170a, 170b), and vias (V1, V2, V3).

The above printed circuit board expresses electrical wiring connecting circuit components as wiring diagrams based on the circuit design, and can reproduce electrical conductors on an insulating layer. Furthermore, such a printed circuit board can mount electrical components and form wiring that connects them retrospectively, and can mechanically secure components other than those that electrically connect the components.

These printed circuit boards include an insulating layer (110, 120, 130). The insulating layer (110, 120, 130) may be a supporting substrate of a printed circuit board on which a single circuit pattern is formed, but may also mean an insulating region on which one circuit pattern is formed among printed circuit boards having a plurality of laminated structures.

The insulating layer (110, 120, 130) may have a multiple layered structure.

For example, the printed circuit board may include a first insulating layer (110). In addition, the printed circuit board may include a second insulating layer (120) disposed on the first insulating layer (110). In addition, the printed circuit board may include a third insulating layer (130) disposed under the first insulating layer (110). Here, although the printed circuit board is illustrated in the drawing as having a structure including three insulating layers, it is not limited thereto. For example, the printed circuit board may have a structure including less than three insulating layers, or alternatively, may have a structure including more than three insulating layers. Hereinafter, for convenience of explanation, it will be described as if the printed circuit board has a structure including three insulating layers.

The first insulating layer (110), the second insulating layer (120), and the third insulating layer (130) are substrates on which electric circuits capable of changing wiring are formed, and may include all of a print, a wiring board, and an insulating substrate made of an insulating material capable of forming circuit patterns on a surface.

For example, at least one of the first insulating layer (110), the second insulating layer (120), and the third insulating layer (130) may be rigid or flexible. For example, at least one of the first insulating layer (110), the second insulating layer (120), and the third insulating layer (130) may include glass or plastic. In detail, at least one of the first insulating layer (110), the second insulating layer (120), and the third insulating layer (130) may include chemically strengthened/semi-strengthened glass such as soda lime glass or aluminosilicate glass, or may include a strengthened or flexible plastic such as polyimide (PI), polyethylene terephthalate (PET), propylene glycol (PPG), polycarbonate (PC), or may include sapphire.

In addition, at least one of the first insulating layer (110), the second insulating layer (120), and the third insulating layer (130) may include an optically isotropic film. For example, at least one of the first insulating layer (110), the second insulating layer (120), and the third insulating layer (130) may include a cyclic olefin copolymer (COC), a cyclic olefin polymer (COP), an optically isotropic polycarbonate (PC), or an optically isotropic polymethyl methacrylate (PMMA).

In addition, at least one of the first insulating layer (110), the second insulating layer (120), and the third insulating layer (130) can be bent while having a partially curved surface. That is, at least one of the first insulating layer (110), the second insulating layer (120), and the third insulating layer (130) can be bent while having a partially flat surface and a partially curved surface. In detail, at least one of the first insulating layer (110), the second insulating layer (120), and the third insulating layer (130) can be bent while having a curved end or can be bent or curved while having a surface including a random curvature.

In addition, at least one of the first insulating layer (110), the second insulating layer (120), and the third insulating layer (130) may be a flexible substrate having flexible characteristics. In addition, at least one of the first insulating layer (110), the second insulating layer (120), and the third insulating layer (130) may be a curved or bent substrate. In this case, at least one of the first insulating layer (110), the second insulating layer (120), and the third insulating layer (130) may express an electric wiring that connects a circuit component based on a circuit design as a wiring diagram, and may reproduce an electric conductor on the insulating material. In addition, at least one of the first insulating layer (110), the second insulating layer (120), and the third insulating layer (130) may form a wiring that mounts an electric component and connects them circuit-wise, and may mechanically fix components other than the electrical connection function of the component.

Meanwhile, the first insulating layer (110), the second insulating layer (120), and the third insulating layer (130) may each include a first region (R1) and a second region (R2).

The first region (R1) may be a dummy region in which dummy patterns are formed. The second region (R2) may be a region excluding the first region (R1). Generally, a printed circuit board includes a dummy region corresponding to the first region (R1), and a dummy pattern is formed in the dummy region to improve the reliability of the board. At this time, in the printed circuit board of the first embodiment, the dummy pattern does not entirely cover the dummy region corresponding to the first region (R1), but has a plurality of openings in the shape of dots, so that gas remaining in the first insulating layer (110), the second insulating layer (120), and the third insulating layer (130) can be degassed.

A circuit pattern layer may be formed on the surfaces of the first insulating layer (110), the second insulating layer (120), and the third insulating layer (130).

For example, a first circuit pattern layer may be formed on the upper surface of the first insulating layer (110). In addition, a second circuit pattern layer may be formed on the lower surface of the first insulating layer (110). In addition, a third circuit pattern layer may be formed on the upper surface of the second insulating layer (120). In addition, a fourth circuit pattern layer may be formed on the lower surface of the third insulating layer (130). These circuit pattern layers may include dummy patterns and effective patterns. For example, the circuit pattern layers may include dummy patterns formed in the first region (R1) of each insulating layer and effective patterns formed in the second region (R2). Meanwhile, in general, the dummy pattern is formed to entirely cover the dummy region of the insulating layer. For example, the upper surface of the dummy region of the insulating layer is entirely covered by the dummy pattern. In this case, in the embodiment, an opening is formed in the dummy pattern and used as a degassing hole.

Specifically, the first circuit pattern layer may include a first dummy pattern (140a) arranged in a first region (R1) of the upper surface of the first insulating layer (110) and a first effective pattern (140b) arranged in a second region (R2).

Additionally, the second circuit pattern layer may include a second dummy pattern (150a) arranged in a first region (R1) on the lower surface of the first insulating layer (110) and a second effective pattern (150b) arranged in a second region (R2).

Additionally, the third circuit pattern layer may include a third dummy pattern (160a) arranged in a first region (R1) of the upper surface of the second insulating layer (120) and a third effective pattern (160b) arranged in a second region (R2).

Additionally, the fourth circuit pattern layer may include a fourth dummy pattern (170a) arranged in the first region (R1) of the lower surface of the third insulating layer (130) and a fourth effective pattern (170b) arranged in the second region (R2).

These first to fourth circuit pattern layers may be formed of a metal material having high electrical conductivity. For example, the first to fourth circuit pattern layers may be formed of at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn). For example, the first to fourth circuit pattern layers may be formed of a paste or solder paste including at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn) having excellent bonding strength. Preferably, the first to fourth circuit pattern layers may be formed of copper (Cu) which has high electrical conductivity and is relatively inexpensive.

The above first to fourth circuit pattern layers can be manufactured using conventional printed circuit board manufacturing processes such as additive process, subtractive process, modified semi-additive process (MSAP), and semi-additive process (SAP), and a detailed description thereof is omitted here.

Meanwhile, the printed circuit board includes vias (V1, V2, V3). The vias (V1, V2, V3) may be formed to penetrate at least one of the first insulating layer (110), the second insulating layer (120), and the third insulating layer (130). The vias (V1, V2, V3) may electrically connect circuit pattern layers arranged on different layers.

For example, a first via (V1) may be formed in the first insulating layer (110). The first via (V1) may electrically connect a first circuit pattern layer disposed on an upper surface of the first insulating layer (110) and a second circuit pattern layer disposed on a lower surface of the first insulating layer (110).

For example, a second via (V2) may be formed in the second insulating layer (120). The second via (V2) may electrically connect the first circuit pattern layer disposed on the upper surface of the first insulating layer (110) and the third circuit pattern layer disposed on the upper surface of the second insulating layer (120).

For example, a third via (V3) may be formed in the third insulating layer (130). The third via (V3) may electrically connect the second circuit pattern layer disposed on the lower surface of the first insulating layer (110) and the fourth circuit pattern layer disposed on the lower surface of the third insulating layer (130).

Meanwhile, the via (V1, V2, V3) can be formed by filling the inside of a through hole (not shown) penetrating at least one of the plurality of insulating layers with a conductive material.

The above through hole can be formed by any one of mechanical, laser, and chemical processing methods. When the through hole is formed by mechanical processing, methods such as milling, drilling, and routing can be used. When the through hole is formed by laser processing, a UV or Co ₂ laser method can be used. When the through hole is formed by chemical processing, a chemical agent including aminosilane, ketones, etc. can be used to open at least one of the plurality of insulating layers.

Meanwhile, the processing using the laser is a cutting method that focuses optical energy on a surface to melt and vaporize part of the material, thereby taking on a desired shape, and can easily process complex shapes using a computer program, and can also process composite materials that are difficult to cut using other methods.

In addition, the processing by the above laser has the advantage of a cutting diameter of at least 0.005 mm and a wide range of processable thicknesses.

For the above laser processing drill, it is preferable to use a YAG (Yttrium Aluminum Garnet) laser, a _CO2 laser, or an ultraviolet (UV) laser. The YAG laser is a laser that can process both the copper layer and the insulating layer, and the _CO2 laser is a laser that can process only the insulating layer.

When the above through hole is formed, the inside of the through hole can be filled with a conductive material to form the via (V1, V2, V3). The metal material forming the via (V1, V2, V3) can be any one material selected from copper (Cu), silver (Ag), tin (Sn), gold (Au), nickel (Ni), and palladium (Pd), and the filling of the conductive material can use any one of electroless plating, electrolytic plating, screen printing, sputtering, evaporation, inkjetting, and dispensing, or a combination thereof.

Meanwhile, the first to fourth circuit pattern layers as described above may each have a multiple layer structure. For example, each of the first to fourth circuit pattern layers may include, but is not limited to, a chemical copper plating layer formed through electroless plating and an electrolytic plating layer formed through electrolytic plating.

Meanwhile, the dummy patterns formed in the first region (R1) of each circuit pattern layer in the embodiment may include an opening. The opening may be a hole exposing the surface of the insulating layer.

Specifically, the first dummy pattern (140a) may include a plurality of first openings (140h) that are spaced apart from each other. The plurality of first openings (140h) may expose the upper surface of the first insulating layer (110). That is, the plurality of first openings (140h) may be formed to penetrate the upper and lower surfaces of the first dummy pattern (140a). The plurality of first openings (140h) may have a dot shape. That is, the first dummy pattern (140a) may include a plurality of first openings (140h) having a dot shape. Accordingly, in a state in which the first dummy pattern (140a) is formed, the upper surface of the first insulating layer (110) may be exposed through the plurality of first openings (140h). In addition, the gas remaining in the first insulating layer (110) can be degassed through the first opening (140h). Accordingly, in the embodiment, by degassing the gas remaining in the first insulating layer (110), thermal stress can be relieved, thereby improving reliability.

That is, referring to Fig. 2, the dummy pattern (140a') of the comparative example is formed to entirely cover the first region (R1) of the first insulating layer (110'). At this time, when the dummy pattern (140a') is formed to entirely cover the first region (R1) of the first insulating layer (110'), gas may remain within the first insulating layer (110'), which may result in a decrease in reliability.

In contrast, in the embodiment, the first dummy pattern (140a) has a plurality of first openings (140h) in the form of dots that expose the upper surface of the first region (R1) of the first insulating layer (110), as described above. Accordingly, in the embodiment, the gas remaining in the first insulating layer (110) can be degassed through the plurality of first openings (140h) formed in the first dummy pattern (140a), thereby resolving the reliability problem caused by this.

Meanwhile, referring to FIG. 3, the first opening (140h) may be configured in multiple numbers. That is, the first dummy pattern (140a) may include a plurality of first openings (140h) spaced apart from each other by a certain interval. That is, the plurality of first openings (140h) may be formed in the form of dots on the first dummy pattern (140a).

Each of the plurality of first openings (140h) may have a first diameter (D1). For example, the first diameter (D1) may be greater than 100 μm. Here, if the first diameter (D1) of the first opening (140h) is less than 100 μm, a problem may arise in which gas remaining within the first insulating layer (110) is not normally degassed.

Meanwhile, the plurality of first openings (140h) may be spaced apart from each other by a first interval (D2). For example, the first interval (D2) may be greater than 25 μm. When the first interval (D2) is less than 25 μm, a problem may occur in which at least two adjacent first openings among the plurality of first openings (140h) come into contact with each other. For example, when the first interval (D2) is less than 25 μm, the opening ratio of the first dummy pattern (140a) due to the first openings (140h) may be too large, and thus, the normal function of the first dummy pattern (140a) may not be performed.

The plurality of first openings (140h) formed in the first dummy pattern (140a) may be filled by an additionally laminated insulating layer. For example, a second insulating layer (120) is disposed on the upper surface of the first insulating layer (110). Accordingly, the plurality of first openings (140h) formed in the first dummy pattern (140a) may be filled by the second insulating layer (120) disposed on the first insulating layer (110).

Meanwhile, a second dummy pattern (150a) may be formed on the lower surface of the first insulating layer (110). In addition, the second dummy pattern (150a) may include a plurality of second openings (150h) that are spaced apart from each other. The plurality of second openings (150h) may expose the lower surface of the first insulating layer (110). That is, the plurality of second openings (150h) may be formed to penetrate the upper and lower surfaces of the second dummy pattern (150a). The plurality of second openings (150h) may have a dot shape. That is, the second dummy pattern (150a) may include a plurality of second openings (150h) having a dot shape. Accordingly, in a state in which the second dummy pattern (150a) is formed, the lower surface of the first insulating layer (110) may be exposed through the plurality of second openings (150h). In addition, the gas remaining in the first insulating layer (110) can be degassed through the second opening (150h). Accordingly, in the embodiment, by degassing the gas remaining in the first insulating layer (110), thermal stress can be relieved, thereby improving reliability.

Meanwhile, a third dummy pattern (160a) may be formed on the upper surface of the second insulating layer (120). In addition, the third dummy pattern (160a) may include a plurality of third openings (160h) that are spaced apart from each other. The plurality of third openings (160h) may expose the upper surface of the second insulating layer (120). That is, the plurality of third openings (160h) may be formed to penetrate the upper and lower surfaces of the third dummy pattern (160a). The plurality of third openings (160h) may have a dot shape. That is, the third dummy pattern (160a) may include a plurality of third openings (160h) having a dot shape. Accordingly, in a state in which the third dummy pattern (160a) is formed, the upper surface of the second insulating layer (120) may be exposed through the plurality of third openings (160h). In addition, the gas remaining in the second insulating layer (120) can be degassed through the third opening (160h). Accordingly, in the embodiment, by degassing the gas remaining in the second insulating layer (120), thermal stress can be relieved, thereby improving reliability.

Meanwhile, a fourth dummy pattern (170a) may be formed on the lower surface of the third insulating layer (130). In addition, the fourth dummy pattern (170a) may include a plurality of fourth openings (170h) that are spaced apart from each other. The plurality of fourth openings (170h) may expose the lower surface of the third insulating layer (130). That is, the plurality of fourth openings (170h) may be formed to penetrate the upper and lower surfaces of the fourth dummy pattern (170a). The plurality of fourth openings (170h) may have a dot shape. That is, the fourth dummy pattern (170a) may include a plurality of fourth openings (170h) having a dot shape. Accordingly, in a state in which the fourth dummy pattern (170a) is formed, the lower surface of the third insulating layer (130) may be exposed through the plurality of fourth openings (170h). In addition, the gas remaining in the third insulating layer (130) can be degassed through the fourth opening (170h). Accordingly, in the embodiment, by degassing the gas remaining in the third insulating layer (130), thermal stress can be relieved, thereby improving reliability.

Meanwhile, the plurality of third openings (160h) formed in the third dummy pattern (160a) may be filled by an insulating layer additionally laminated on the second insulating layer (120), but is not limited thereto. For example, when the second insulating layer (120) is the outermost insulating layer disposed on the uppermost side of the printed circuit board, the third openings (160h) may be maintained in an open state. For example, when the second insulating layer (120) is the outermost insulating layer disposed on the uppermost side of the printed circuit board, the third openings (160h) may be filled by a solder resist layer (not shown) disposed on the second insulating layer (120).

Likewise, the plurality of fourth openings (170h) formed in the fourth dummy pattern (170a) may be filled by an insulating layer additionally laminated under the third insulating layer (130), but is not limited thereto. For example, when the third insulating layer (130) is the outermost insulating layer disposed at the lowest side of the printed circuit board, the fourth openings (170h) may be maintained in an open state. For example, when the third insulating layer (130) is the outermost insulating layer disposed at the lowest side of the printed circuit board, the fourth openings (170h) may be filled by a solder resist layer (not shown) disposed under the third insulating layer (130).

As described above, in the embodiment, a dummy pattern is formed in the first region (R1) corresponding to the dummy region of the insulating layer, and a plurality of openings having a dot shape are formed in the dummy pattern. In addition, the plurality of openings enable degassing of gas remaining in the insulating layer. Accordingly, in the embodiment, the reliability of the printed circuit board can be improved by removing gas between the insulating layer and the circuit pattern layer. For example, in the embodiment, by removing the gas remaining in the insulating layer, the thermal stress of the insulating layer can be minimized. For example, in the embodiment, the reliability problem of the circuit pattern layer being detached from the insulating layer can be solved by removing the gas remaining in the insulating layer. In addition, in the embodiment, by including a plurality of openings in the dummy pattern as described above, the plating deviation of the circuit pattern layer can be improved by controlling the area of the dummy pattern.

Fig. 4 is a variation example of the shape of an opening formed in a dummy pattern according to an embodiment.

First, referring to FIG. 3, a plurality of first openings (140h) having a circular plane can be formed in the first dummy pattern (140a).

Meanwhile, the shape of the first opening (140h) formed in the first dummy pattern (140a) may have a shape other than a circle.

For example, as in (a) of FIG. 4, the first opening (140h-1) formed in the first dummy pattern (140a) may have a rectangular plane.

For example, as in (b) of FIG. 4, the first opening (140h-2) formed in the first dummy pattern (140a) may have a rhombus-shaped plane.

However, the embodiment is not limited thereto, and the opening formed in the dummy pattern may be changed into various shapes such as a triangle, an ellipse, a heart, a star, a fan shape, etc.

Hereinafter, a method for manufacturing a printed circuit board according to the first embodiment illustrated in FIG. 1 will be described.

Figures 5 to 9 are drawings showing the manufacturing method of the printed circuit board illustrated in Figure 1 in process order.

Referring to FIG. 5, in the embodiment, a first insulating layer (110) that serves as the basis for manufacturing a printed circuit board is prepared.

The first insulating layer (110) may be rigid or flexible. For example, the first insulating layer (110) may include glass or plastic. Specifically, the first insulating layer (110) may include chemically strengthened/semi-strengthened glass such as soda lime glass or aluminosilicate glass, or may include a strengthened or flexible plastic such as polyimide (PI), polyethylene terephthalate (PET), propylene glycol (PPG), polycarbonate (PC), or may include sapphire.

In addition, the first insulating layer (110) may include an optically isotropic film. For example, the first insulating layer (110) may include a cyclic olefin copolymer (COC), a cyclic olefin polymer (COP), an optically isotropic polycarbonate (PC), or an optically isotropic polymethyl methacrylate (PMMA).

In addition, the first insulating layer (110) may be bent while having a partially curved surface. That is, the first insulating layer (110) may be bent while having a partially flat surface and a partially curved surface. In detail, the first insulating layer (110) may be bent while having a curved surface at the end, or may be bent or curved while having a surface including a random curvature.

Next, referring to FIG. 6, in the embodiment, a process of forming a first circuit pattern layer on the upper surface of the first insulating layer (110), forming a second circuit pattern layer on the lower surface of the first insulating layer (110), and forming a first via (V1) within the first insulating layer (110) may be performed.

Each of the first circuit pattern layer and the second circuit pattern layer may include a chemical copper plating layer formed through electroless plating, and an electrolytic plating layer formed by plating the chemical copper plating layer as a seed layer.

At this time, the first circuit pattern layer and the second circuit pattern layer may be formed in the first region (R1) and the second region (R2) of the first insulating layer (110), respectively. For example, the first circuit pattern layer may include a first dummy pattern (140a) formed in the first region (R1) of the first insulating layer (110) and a first effective pattern (140b) formed in the second region (R2). For example, the second circuit pattern layer may include a second dummy pattern (150a) formed in the first region (R1) of the first insulating layer (110) and a second effective pattern (150b) formed in the second region (R2).

Meanwhile, the first dummy pattern (140a) formed above may be formed to entirely cover the upper surface of the first region (R1) of the first insulating layer (110). In addition, the second dummy pattern (150a) may be formed to entirely cover the lower surface of the first region (R1) of the first insulating layer (110).

Next, referring to FIG. 7, in the embodiment, a process of forming a plurality of first openings (140h) that are spaced apart from each other in the first dummy pattern (140a) may be performed. In addition, in the embodiment, a process of forming a plurality of second openings (150h) that are spaced apart from each other in the second dummy pattern (150a) may be performed. The first openings (140h) and the second openings (150h) may each have a first diameter (D1) and may be spaced apart from each other by a first gap (D2). The plurality of first openings (140h) and the second openings (150h) may each have a dot shape.

Next, referring to FIG. 8, in the embodiment, a process of forming a second insulating layer (120) on the upper surface of the first insulating layer (110) and forming a third insulating layer (130) on the lower surface of the first insulating layer (110) may be performed.

At this time, the plurality of first openings (140h) formed in the first dummy pattern (140a) can be filled by the second insulating layer (120) that is laminated.

Additionally, a plurality of second openings (150h) formed in the second dummy pattern (150a) can be filled by the third insulating layer (130) that is laminated.

And, in the embodiment, a process of forming a third circuit pattern layer on the upper surface of the second insulating layer (120) and forming a fourth circuit pattern layer on the lower surface of the third insulating layer (130) may be performed. In addition, in the embodiment, a process of forming a second via (V2) in the second insulating layer (120) and forming a third via (V3) in the third insulating layer (130) may be performed.

Each of the third circuit pattern layer and the fourth circuit pattern layer may include a chemical copper plating layer formed through electroless plating, and an electrolytic plating layer formed by plating the chemical copper plating layer as a seed layer.

At this time, the third circuit pattern layer and the fourth circuit pattern layer may be formed in the first region (R1) and the second region (R2) of the second insulating layer (120) and the third insulating layer (130), respectively. For example, the third circuit pattern layer may include a third dummy pattern (160a) formed in the first region (R1) of the second insulating layer (120) and a third effective pattern (160b) formed in the second region (R2). For example, the fourth circuit pattern layer may include a fourth dummy pattern (170a) formed in the first region (R1) of the third insulating layer (130) and a fourth effective pattern (170b) formed in the second region (R2).

Meanwhile, the third dummy pattern (160a) formed above may be formed to entirely cover the upper surface of the first region (R1) of the second insulating layer (120). In addition, the fourth dummy pattern (170a) may be formed to entirely cover the lower surface of the first region (R1) of the third insulating layer (130).

Next, referring to FIG. 9, in the embodiment, a process of forming a plurality of third openings (160h) that are spaced apart from each other in the third dummy pattern (160a) may be performed. In addition, in the embodiment, a process of forming a plurality of fourth openings (170h) that are spaced apart from each other in the fourth dummy pattern (170a) may be performed. The third openings (160h) and the fourth openings (170h) may each have a first diameter (D1) and may be spaced apart from each other by a first gap (D2). The plurality of third openings (160h) and the fourth openings (170h) may each have a dot shape.

As described above, in the first embodiment, the gas remaining in the insulating layer was degassed by forming an opening in a dummy pattern arranged on the surface of the insulating layer. However, in such a case, a situation may arise where the gas remaining in the insulating layer is not completely degassed. This is because, in the chemical copper plating process for forming the dummy pattern, a situation may arise where the gas penetrates into the insulating layer, and thus, it is difficult to completely degas the gas that has penetrated into the insulating layer simply by forming an opening in the dummy pattern. Accordingly, in the embodiment, the opening for degassing is formed in a via shape rather than a pattern shape, so that the gas remaining in the insulating layer can be completely removed.

Figure 10 is a drawing showing a printed circuit board according to the second embodiment.

Referring to FIG. 10, a printed circuit board according to the second embodiment includes a first insulating layer (210), a second insulating layer (220), a third insulating layer (230), circuit pattern layers (240a, 240b, 250a, 250b, 260a, 260b, 270a, 270b) and vias (V1, V2, V3).

Here, prior to the description of Fig. 10, the description of the configuration that is substantially the same as the printed circuit board of the first embodiment illustrated in Fig. 1 will be omitted.

In Fig. 1, the opening for degassing was formed only in the dummy pattern. In contrast, as in Fig. 10, the opening for degassing may be formed not only in the dummy pattern but also in the insulating layer. Accordingly, the opening for degassing according to the second embodiment, as in Fig. 10, may be divided into a first portion formed in the dummy pattern and a second portion formed in the insulating layer.

Specifically, the first circuit pattern layer may include a first dummy pattern (240a) arranged in a first region (R1) of the upper surface of the first insulating layer (210) and a first effective pattern (240b) arranged in a second region (R2).

Additionally, the second circuit pattern layer may include a second dummy pattern (250a) arranged in a first region (R1) on the lower surface of the first insulating layer (210) and a second effective pattern (250b) arranged in a second region (R2).

Additionally, the third circuit pattern layer may include a third dummy pattern (260a) arranged in a first region (R1) on the upper surface of the second insulating layer (220) and a third effective pattern (260b) arranged in a second region (R2).

Additionally, the fourth circuit pattern layer may include a fourth dummy pattern (270a) arranged in the first region (R1) of the lower surface of the third insulating layer (230) and a fourth effective pattern (270b) arranged in the second region (R2).

Meanwhile, in the second embodiment, openings for degassing are formed in the first region (R1) of the insulating layer and the dummy pattern arranged in the first region (R1). Meanwhile, the first to fourth openings for degassing described below may each be referred to as degassing sections.

Specifically, a first opening (240h) may be formed in the first insulating layer (210) and the first dummy pattern (240a). For example, the first opening (240h) may include a 1-1 portion (240h-1) formed to penetrate the upper and lower surfaces of the first dummy pattern (240a). The 1-1 portion (240h-1) of the first opening (240h) may be substantially the same as the first opening (140h) described with reference to FIGS. 1 and 3. In addition, the first opening (240h) may be connected to the 1-1 portion (240h-1) and include a 1-2 portion (240h-2) formed in the first insulating layer (210). The first-second portion (240h-2) formed on the first insulating layer (210) may have a structure that penetrates the first insulating layer (210), or alternatively, may have a non-penetrating structure. As described above, in the embodiment, the first opening (240h) for degassing has a structure including the first-first portion (240h-1) formed on the first dummy pattern (240a) and the first-second portion (240h-2) formed on the first insulating layer (210). Accordingly, in the embodiment, even the gas that has penetrated into the first insulating layer (210) can be completely removed, thereby improving reliability.

In addition, a second opening (250h) may be formed in the first insulating layer (210) and the second dummy pattern (250a). For example, the second opening (250h) may include a 2-1 portion (250h-1) formed to penetrate the upper and lower surfaces of the second dummy pattern (250a). The 2-1 portion (250h-1) of the second opening (250h) may be substantially the same as the second opening (150h) described with reference to FIGS. 1 and 3. In addition, the second opening (250h) may be connected to the 2-1 portion (250h-1) and include a 2-2 portion (250h-2) formed in the first insulating layer (210). The second-second portion (250h-2) formed on the first insulating layer (210) may have a structure that penetrates the first insulating layer (210), or alternatively, may have a non-penetrating structure. As described above, in the embodiment, the second opening (250h) for degassing has a structure including the second-first portion (250h-1) formed on the second dummy pattern (250a), and the second-second portion (250h-2) formed on the first insulating layer (210). Accordingly, in the embodiment, even the gas that has penetrated into the first insulating layer (210) can be completely removed, thereby improving reliability.

In addition, a third opening (260h) may be formed in the second insulating layer (220) and the third dummy pattern (260a). For example, the third opening (260h) may include a 3-1 portion (260h-1) formed to penetrate the upper and lower surfaces of the third dummy pattern (260a). The 3-1 portion (260h-1) of the third opening (260h) may be substantially the same as the third opening (160h) described with reference to FIGS. 1 and 3. In addition, the third opening (260h) may be connected to the 3-1 portion (260h-1) and include a 3-2 portion (260h-2) formed in the second insulating layer (220). The 3-2 portion (260h-2) formed on the second insulating layer (220) may have a structure that penetrates the second insulating layer (220), or alternatively, may have a non-penetrating structure. As described above, in the embodiment, the third opening (260h) for degassing has a structure including the 3-1 portion (260h-1) formed on the third dummy pattern (260a), and the 3-2 portion (260h-2) formed on the second insulating layer (220). Accordingly, in the embodiment, even the gas that has penetrated into the second insulating layer (220) can be completely removed, thereby improving reliability.

In addition, a fourth opening (270h) may be formed in the third insulating layer (230) and the fourth dummy pattern (270a). For example, the fourth opening (270h) may include a 4-1 portion (270h-1) formed to penetrate the upper and lower surfaces of the fourth dummy pattern (270a). The 4-1 portion (270h-1) of the fourth opening (270h) may be substantially the same as the fourth opening (170h) described with reference to FIGS. 1 and 3. In addition, the fourth opening (270h) may be connected to the 4-1 portion (270h-1) and include a 4-2 portion (270h-2) formed in the third insulating layer (230). The 4-2 portion (270h-2) formed on the third insulating layer (230) may have a structure that penetrates the third insulating layer (230), or alternatively, may have a non-penetrating structure. As described above, in the embodiment, the fourth opening (270h) for degassing has a structure including the 4-1 portion (270h-1) formed on the fourth dummy pattern (270a) and the 4-2 portion (270h-2) formed on the third insulating layer (230). Accordingly, in the embodiment, even the gas that has penetrated into the third insulating layer (230) can be completely removed, thereby improving reliability.

Meanwhile, the above-described openings may be filled with a build-up insulating layer during the lamination process of the insulating layer. For example, the first-first portion (240h-1) and the first-second portion (240h-2) of the first opening (240h) may be filled with the second insulating layer (220). For example, the second-first portion (250h-1) and the second-second portion (250h-2) of the second opening (250h) may be filled with the third insulating layer (230).

Meanwhile, the 3-1 portion (260h-1) and the 3-2 portion (260h-2) of the third opening (260h) may be filled with an additional build-up insulating layer, or alternatively, may be filled with a solder resist layer. Similarly, the 4-1 portion (270h-1) and the 4-2 portion (270-2) of the fourth opening (270h) may be filled with an additional build-up insulating layer, or alternatively, may be filled with a solder resist layer.

Hereinafter, a manufacturing process of a printed circuit board according to the second embodiment illustrated in FIG. 10 will be described.

Figures 11 to 14 are drawings showing the manufacturing method of the printed circuit board illustrated in Figure 10 in process order.

Referring to FIG. 11, in the embodiment, a first insulating layer (210) that serves as the basis for manufacturing a printed circuit board is prepared.

And, in the embodiment, a process of forming a first circuit pattern layer on the upper surface of the first insulating layer (210), forming a second circuit pattern layer on the lower surface of the first insulating layer (210), and forming a first via (V1) within the first insulating layer (210) can be performed.

Each of the first circuit pattern layer and the second circuit pattern layer may include a chemical copper plating layer formed through electroless plating, and an electrolytic plating layer formed by plating the chemical copper plating layer as a seed layer.

At this time, the first circuit pattern layer and the second circuit pattern layer may be formed in the first region (R1) and the second region (R2) of the first insulating layer (210), respectively. For example, the first circuit pattern layer may include a first dummy pattern (240a) formed in the first region (R1) of the first insulating layer (210) and a first effective pattern (240b) formed in the second region (R2). For example, the second circuit pattern layer may include a second dummy pattern (250a) formed in the first region (R1) of the first insulating layer (210) and a second effective pattern (250b) formed in the second region (R2).

Meanwhile, the first dummy pattern (240a) formed above may be formed to entirely cover the upper surface of the first region (R1) of the first insulating layer (210). In addition, the second dummy pattern (250a) may be formed to entirely cover the lower surface of the first region (R1) of the first insulating layer (210).

Next, referring to FIG. 12, in the embodiment, a process of forming a first opening (240h) and a second opening (250h) can be performed.

For example, in the embodiment, a first-first portion (240h-1) of a first opening (240h) may be formed in the first dummy pattern (240a), and a first-second portion (240h-2) of a first opening (240h) may be formed in the first insulating layer (210) so as to be connected to the first-first portion (240h-1).

In addition, in the embodiment, a second-first portion (250h-1) of a second opening (250h) may be formed in the second dummy pattern (250a), and a second-second portion (250h-2) of a second opening (250h) may be formed in the first insulating layer (210) so as to be connected to the second-first portion (250h-1).

Meanwhile, in the above, the portion formed in the first insulating layer (210) among the first opening (240h) and the second opening (250h) is divided into multiple portions, but is not limited thereto. For example, the first-second portion (240h-2) of the first opening (240h) may include the second-second portion (250h-2) of the second opening (250h) illustrated in the drawing. In other words, the first-second portion (240h-2) and the second-second portion (250h-2) may be formed as one integral portion.

Next, referring to FIG. 13, in the embodiment, a process of forming a second insulating layer (220) on the upper surface of the first insulating layer (210) and forming a third insulating layer (230) on the lower surface of the first insulating layer (210) may be performed.

At this time, the first dummy pattern (240a) and the first opening (240h) formed in the first insulating layer (210) can be filled by the second insulating layer (220) that is laminated.

Additionally, the second dummy pattern (250a) and the plurality of second openings (250h) formed in the first insulating layer (210) can be filled by the third insulating layer (230) that is laminated.

And, in the embodiment, a process of forming a third circuit pattern layer on the upper surface of the second insulating layer (220) and forming a fourth circuit pattern layer on the lower surface of the third insulating layer (230) may be performed. In addition, in the embodiment, a process of forming a second via (V2) in the second insulating layer (220) and forming a third via (V3) in the third insulating layer (230) may be performed.

Each of the third circuit pattern layer and the fourth circuit pattern layer may include a chemical copper plating layer formed through electroless plating, and an electrolytic plating layer formed by plating the chemical copper plating layer as a seed layer.

At this time, the third circuit pattern layer and the fourth circuit pattern layer may be formed in the first region (R1) and the second region (R2) of the second insulating layer (220) and the third insulating layer (230), respectively. For example, the third circuit pattern layer may include a third dummy pattern (260a) formed in the first region (R1) of the second insulating layer (220) and a third effective pattern (260b) formed in the second region (R2). For example, the fourth circuit pattern layer may include a fourth dummy pattern (270a) formed in the first region (R1) of the third insulating layer (230) and a fourth effective pattern (270b) formed in the second region (R2).

Meanwhile, the third dummy pattern (260a) formed above may be formed to entirely cover the upper surface of the first region (R1) of the second insulating layer (220). In addition, the fourth dummy pattern (270a) may be formed to entirely cover the lower surface of the first region (R1) of the third insulating layer (230).

Next, referring to FIG. 14, in the embodiment, a process of forming a plurality of third openings (260h) spaced apart from each other in the third dummy pattern (260a) and the second insulating layer (220) may be performed. In addition, in the embodiment, a process of forming a plurality of fourth openings (270h) spaced apart from each other in the fourth dummy pattern (270a) and the third insulating layer (230) may be performed.

That is, the third opening (260h) may include a third-1 portion (260h-1) formed by penetrating the upper and lower surfaces of the third dummy pattern (260a) and a third-2 portion (260h-2) formed on the second insulating layer (220) and connected to the third-1 portion (260h-1).

In addition, the fourth opening (270h) may include a 4-1 portion (270h-1) formed by penetrating the upper and lower surfaces of the fourth dummy pattern (270a), and a 4-2 portion (270h-2) formed on the third insulating layer (230) and connected to the 4-1 portion (270h-1).

In an embodiment, a dummy pattern is formed in a first region (R1) corresponding to a dummy region of an insulating layer, and a plurality of openings having a dot shape are formed in the dummy pattern. In addition, the plurality of openings enable degassing of gas remaining in the insulating layer. Accordingly, in an embodiment, the reliability of a printed circuit board can be improved by removing gas between the insulating layer and the circuit pattern layer. For example, in an embodiment, by removing the gas remaining in the insulating layer, the thermal stress of the insulating layer can be minimized. For example, in an embodiment, by removing the gas remaining in the insulating layer, the reliability problem of the circuit pattern layer being detached from the insulating layer can be solved. In addition, in an embodiment, by including a plurality of openings in the dummy pattern as described above, the plating deviation of the circuit pattern layer can be improved by controlling the area of the dummy pattern.

In addition, in the embodiment, gas that has penetrated into the insulating layer can be completely removed, thereby further improving reliability. For example, in the embodiment, an opening for degassing can be formed not only in the dummy pattern but also in the insulating layer. For example, the opening for degassing includes a first portion formed in the dummy pattern and a second portion formed in the insulating layer and connected to the first portion. Accordingly, in the embodiment, even gas that has penetrated into the insulating layer can be completely removed, thereby further improving reliability.

The features, structures, effects, etc. described in the embodiments above are included in at least one embodiment, and are not necessarily limited to just one embodiment. Furthermore, the features, structures, effects, etc. exemplified in each embodiment can be combined or modified in other embodiments by those skilled in the art to which the embodiments pertain. Therefore, the contents related to such combinations and modifications should be construed as being included within the scope of the embodiments.

Although the above description focuses on examples, these are merely examples and are not intended to limit the examples. Those skilled in the art will appreciate that various modifications and applications not exemplified above are possible without departing from the essential characteristics of the present examples. For example, each component specifically shown in the examples can be modified and implemented. In addition, differences related to such modifications and applications should be interpreted as being included within the scope of the embodiments set forth in the appended claims.

Claims (17)

First insulating layer;
A first circuit pattern layer disposed on the first insulating layer; and
A second insulating layer is disposed on the first circuit pattern layer,
The first circuit pattern layer includes a first dummy through-hole that penetrates the upper and lower surfaces of the first circuit pattern layer,
The first insulating layer includes a second dummy penetration portion that overlaps the first dummy penetration portion along the vertical direction and penetrates at least a portion of the first insulating layer,
The second insulating layer includes a protrusion disposed within the first dummy penetration portion and the second dummy penetration portion.
Circuit board. In the first paragraph,
The first dummy penetration portion includes a plurality of first dummy openings spaced apart from each other in a horizontal direction in the first circuit pattern layer,
The second dummy penetration portion includes a plurality of first dummy openings and a plurality of second dummy openings overlapping along the vertical direction.
Circuit board. In the first paragraph,
Further comprising a first conductive via penetrating at least a portion of the first insulating layer along the vertical direction and spaced apart from the protrusion along the horizontal direction,
Circuit board. In the third paragraph,
The first conductive via and the protrusion overlap along the horizontal direction,
Circuit board. In paragraph 4,
At least a portion of the side surface of the protrusion has an inclination angle that is the same as an inclination angle of at least a portion of the side surface of the first conductive via;
Circuit board. In the second paragraph,
The horizontal width of the plurality of first dummy openings is greater than the horizontal spacing between the plurality of first dummy openings.
Circuit board. In the first paragraph,
A second circuit pattern layer disposed on the second insulating layer; and
Further comprising a third insulating layer disposed on the second circuit pattern layer, wherein the second circuit pattern layer includes a third dummy through-hole penetrating the upper and lower surfaces of the second circuit pattern layer,
The second insulating layer overlaps the third dummy penetration portion along the vertical direction and includes a fourth dummy penetration portion penetrating at least a portion of the second insulating layer,
The third insulating layer includes a protrusion disposed within the third dummy penetration portion and the fourth dummy penetration portion.
Circuit board. In paragraph 7,
The first to fourth dummy penetration portions are overlapped along the vertical direction,
Circuit board. In paragraph 8,
The protrusions of the first insulating layer and the protrusions of the second insulating layer overlap each other along the vertical direction.
Circuit board. In paragraph 8,
Further comprising a second conductive via penetrating the upper and lower surfaces of the second insulating layer,
The second conductive via is spaced apart from the protrusion of the second insulating layer in a horizontal direction,
Circuit board. In Article 10,
The slope of the side surface of the second conductive via is the same as the slope of the side surface of the protrusion of the second insulating layer.
Circuit board. In the first paragraph,
The slope of the inner wall of the first dummy penetration portion is different from the slope of the inner wall of the second dummy penetration portion.
Circuit board. In paragraph 12,
The slope of the inner wall of the first dummy penetration portion with respect to the lower surface of the first insulating layer is closer to vertical than the slope of the inner wall of the second dummy penetration portion with respect to the lower surface of the first insulating layer.
Circuit board. delete delete delete delete