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JPS6421665A - Local memory control system - Google Patents

Local memory control system

Info

Publication number
JPS6421665A
JPS6421665A JP17831987A JP17831987A JPS6421665A JP S6421665 A JPS6421665 A JP S6421665A JP 17831987 A JP17831987 A JP 17831987A JP 17831987 A JP17831987 A JP 17831987A JP S6421665 A JPS6421665 A JP S6421665A
Authority
JP
Japan
Prior art keywords
load
main
memory space
executed
access
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17831987A
Other languages
Japanese (ja)
Inventor
Hiroyuki Abiko
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
PFU Ltd
Original Assignee
PFU Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by PFU Ltd filed Critical PFU Ltd
Priority to JP17831987A priority Critical patent/JPS6421665A/en
Publication of JPS6421665A publication Critical patent/JPS6421665A/en
Pending legal-status Critical Current

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  • Multi Processors (AREA)

Abstract

PURPOSE:To effectively utilize a main memory space by making a main processor accessable only to the contents of the access of a local memory when the main processor is in a operational condition. CONSTITUTION:When a firmware is executed a load-down on respective local memories 6-i (i=1, 2,...) at a system rising time, on a main memory space 8, the firmwares, to which initial program load is executed, are executed the load-down on the local memories 6-0, 6-1 and 6-2. At such a time, respective local memory control parts 7-i execute controls so that a main processor 1 can access all blocks on the memory 6-i. After the load-down is ended, the control parts 7-i execute the controls so that only the block, to which a slanting line in the memory 6-i is added, can be investigated on the main memory space 8. Thus, in the main memory space 8, only one to relay need the access by the processor 1 in the operational condition is remained.
JP17831987A 1987-07-17 1987-07-17 Local memory control system Pending JPS6421665A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17831987A JPS6421665A (en) 1987-07-17 1987-07-17 Local memory control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17831987A JPS6421665A (en) 1987-07-17 1987-07-17 Local memory control system

Publications (1)

Publication Number Publication Date
JPS6421665A true JPS6421665A (en) 1989-01-25

Family

ID=16046402

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17831987A Pending JPS6421665A (en) 1987-07-17 1987-07-17 Local memory control system

Country Status (1)

Country Link
JP (1) JPS6421665A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007513390A (en) * 2003-09-02 2007-05-24 サーフ テクノロジー インコーポレイテッド Memory reallocation and sharing in electronic systems

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58139261A (en) * 1982-02-15 1983-08-18 Hitachi Ltd Memory sharing method
JPS62125444A (en) * 1985-11-27 1987-06-06 Hitachi Ltd Memory shared area control method

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58139261A (en) * 1982-02-15 1983-08-18 Hitachi Ltd Memory sharing method
JPS62125444A (en) * 1985-11-27 1987-06-06 Hitachi Ltd Memory shared area control method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007513390A (en) * 2003-09-02 2007-05-24 サーフ テクノロジー インコーポレイテッド Memory reallocation and sharing in electronic systems

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