JPS5950559A - Semiconductor device protection circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a semiconductor device for protecting a semiconductor device from static electricity, which is formed by connecting a plurality of pin junction diodes or thin film transistors formed of amorphous 3i in series and further connecting a plurality of them in parallel. It relates to a device protection circuit, and can be used, for example, to protect the electric circuit of an IJ drive contact reading line/sensor from static electricity.

Fig. 1 shows the circuit diagram of the conventional matrix drive IaIJl contact line sensor (Utility Application No. 55-129258
(see issue). In Figure 1, 1 is Ma) IJ Kusj, Q
l) Isolation diode used for switching #j, 2
This is a photodiode used for photoelectric conversion. Also 3゜4
are column and row drive terminals, respectively. Here, both the isolation diode 1 and the photodiode 2 are made of amorphous Si.
A pin junction diode formed using a common process is used, and its current-voltage characteristics are as shown in FIG. That is, the current rises at about 0.6V in the forward direction, and breaks down at about -50V in the reverse direction.

Breakdown voltage v! on this diode! It has been experimentally confirmed that when static electricity with a voltage of 1 or more is applied in the opposite direction, the i-layer is destroyed and the pin junction diode becomes short-circuited. When handling the sensor shown in Figure 1,
When a charged hand 7 is applied to the terminal 6 while the terminal 5 is connected, a current flows in the path shown by the arrow, and the separation diode 8 and photodiode 9 are biased in the opposite direction.
and is destroyed. In contrast, the forward biased photodiode 10 and isolation diode 11 are unaffected.

The electric potential of a human body charged with chemical fibers, etc. reaches nearly 10,000 V, and when a worker's hand charged to such a high C level comes into contact with terminal 6, etc. in Figure 1, many pixels (consisting of a combination of a separation diode and a photodiode) were destroyed, significantly reducing yields in device inspection and installation work.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device protection circuit that can prevent the above-mentioned electrostatic and air-induced destruction of a semiconductor device configured with an element made of amorphous Si.

The feature of the present invention is that in order to achieve the above object, amorphous S
A clamp circuit having a clamp voltage value smaller than the breakdown voltage but larger than the circuit driving voltage is provided for each series circuit including a semiconductor element formed by s,
There is a configuration in which this clamp circuit discharges static electricity.

The present invention will be explained in detail below with reference to the drawings.

FIG. 3 is an embodiment circuit diagram in which the clamp circuit is constructed from an anti-parallel circuit of diode arrays, 12 indicates an input/output terminal for any one pixel in FIG. 1, and 13
14 is a protection resistor, 14 is N diodes connected in series in the forward direction, 15 is N diodes connected in series in the reverse direction, and 16 is connected to the pixel. This is the signal line.

The current (I) and voltage M characteristics of the circuit of the embodiment shown in FIG. 3 are as shown in FIG. Here, Vd is the forward voltage drop per diode, and since N diodes connected in series are connected in antiparallel, the output voltage V is -N-Vd and N-V
It will be clamped during d. The pixel can be protected by preventing this clamp voltage value N-Vd from exceeding the breakdown voltage of the series circuit forming the pixel. Further, the pixel driving voltage needs to fall within the above-mentioned range N-Vd, and thereby the number N of series connections can be determined. The positive and negative clamp values do not need to be the same value at all times, and may be different clamp values depending on the connection status of the elements that make up the pixel. In this case, the value of the number N of series connections is You can decide by selecting each direction separately. Although diodes made of crystalline Si may be used as the diodes constituting the above-mentioned clamp circuit, amorphous Si can be used since they can be formed in the same process as the amorphous Si elements constituting the pixels.
It is more convenient to use a t pin junction diode.

In the embodiment shown in FIG. 5, an n-channel amorphous S+ thin film field effect transistor 17 with its gate and drain shorted is used as a clamp circuit in place of the diode array 13 in FIG.

By using the ramp circuit as described above, when the transistor 17 becomes conductive when a voltage higher than the threshold voltage vth is present on the signal line 16, the current-voltage characteristics of the clamp circuit become as shown in FIG.

As the clamp circuit, it is possible to use a thin film field effect transistor in place of the diode string 15 in FIG. .beta., or to replace both the diode strings 14 and 15 with thin film field effect transistors.

Furthermore, in FIG. 5, a p-channel transistor can be used by reversing the connections.

Figures 7 and 8 show the pixels in Figure 1 and Figure 3 and Figure 5, respectively.
FIG. 3 is an example circuit diagram in which the clamp circuit shown in the figure is provided. Here, the terminal 18 is used to fix the voltage to a constant voltage when the pixel is moving, and to prevent mutual interference of signals through the clamp circuit. The path through which static electricity is discharged is shown by a solid line with an arrow.
In this way, the signal passes through two clamp circuits in series.

FIG. 12 shows the planar structure of the embodiment circuit shown in FIG.
The figure shows the equivalent circuit. For simplicity, two diode arrays were connected in series in the clamp circuit. Also, Figures 9, 10, and 11 correspond to A-A' and B-B in Figure 12, respectively.
' , is a cross-sectional view taken along line C-C'.

In FIGS. 9 to 13, reference numeral 19 denotes a common ground wiring of the clamp circuit, which is formed by slatting or vapor-depositing a metal such as At or Or.

At the same time, the first layer wiring 20 of the terminal 12 is made of amorphous Si.
Lower electrode 21 of pin junction diode, signal line 16
etc. are formed. Next, the clamp circuit diode 22
and glow discharge CVD of amorphous Si as the protective resistor 13.
Formed by law. Here, from the bottom, they are formed in the order of n conductivity type, n conductivity type (intrinsic conductivity type), and n conductivity type.
Although this corresponds to the equivalent circuit shown in the figure, formation in the reverse order is also possible.

After forming amorphous Si, an insulating film 23 such as SIO is sputtered on the entire surface, and CVD1. It is formed by V-bonding, etc., and a hole 24 is drilled only in the part where the connection is to be made. Finally Cr
, At, or the like is formed by vapor deposition or the like to complete the circuit. The above circuit is formed on an insulating substrate 26 made of glass or the like.

FIG. 17 shows the planar structure of the embodiment circuit shown in FIG.
The figure shows the equivalent circuit. Diode string 14 for simplicity
Two pieces were connected in series. Also, Fig. 14.

15 and 16 are A-A' in FIG. 17, respectively.

It is a BB', CC' cross-sectional view. As in the case of FIGS. 9 to 13, the first layer wiring 20 of the terminal 12, the lower electrode 21 of the amorphous Si pin junction diode, and the signal line 16 are formed on the insulating substrate 26.

Next, amorphous Si is formed as the clamp circuit diode 22 and the protective resistor 13 by glow discharge CVD. In addition, in addition to this, a thin film field effect transistor 1
As the gate insulating film 27 of No. 7, a film such as 5i02 is formed by a CVD method or the like. Further, amorphous 5i2B of n-conductivity type is formed thereon by a glow discharge method. Next, as in the case of FIGS. 9 to 13, an insulating film 23 is formed on the entire surface, a hole 24 for a connection portion is made, and a second layer metal wiring 25 is connected thereto to complete the circuit. Note that 29, 30, and 31 represent the drain sheath and gate of the amorphous Si thin film transistor 17, respectively. Furthermore, since the thin film transistor of this embodiment has n-type conductivity and is of an enhancement type, its threshold voltage vth exhibits a positive value.

19 to 22 show, as another embodiment of the present invention, a case in which a clamp circuit is applied to a device constituted by an amorphous Si thin film transistor.

The protected thin film transistor is shown as a single transistor 32 for ease of explanation.

FIG. 19 shows a clamp circuit consisting of a forward and reverse parallel circuit of amorphous Si pin junction diode arrays, with gate electrode 33 and drain polarization 3 of transistor 32 to be protected.
4 and between the gate electrode 33 and the source electrode 35, the transistor 32 is protected from static electricity applied to these electrodes. The operating range of the circuit shown in FIG. 19 is designed according to the above-mentioned FIG. 4, taking into consideration the operating voltage of the element and the gate breakdown voltage. The structure of Oniko conforms to Figures 9 to 12.

In FIG. 20, deep crushing is performed by providing a clamp circuit configured by connecting a series diode array 14 and a thin film transistor 17 whose gate and source are shorted in parallel.
The operating range and structure are based on FIGS. 6 and 14 to 17, respectively.

Figure 21 Beam 271 The circuit is composed entirely of 7 transistors submerged in oil, and 3 thin film transistors to be protected.
Since it is formed by the same process as 2, it is the easiest to introduce. The operating voltage range is -Vth to vth, where Vth is the threshold value of the thin film transistor. If this limits the operating range too much, you can use thin film transistors in the clamp circuit connected in series. For example, in the case of the one connected to the second row of stones as shown in FIG. 22, the operating pressure range is -2 Vth to 2 Vth. When the thin film transistors in the clamp circuit are configured in the same process as the thin film transistor 32 in the main body, it is desirable to drive the main body element at a voltage higher than the threshold voltage, and two or more thin film transistors connected in series as in the embodiment in FIG. Recommended for use in clamp circuits.

According to the present invention, the withstand voltage against static electricity of a semiconductor device including a pin junction diode made of amorphous Si or a thin film transistor also made of amorphous Si can be significantly improved. To give a specific numerical example, when an amorphous Si pin junction diode is used in the 2271 circuit, the withstand voltage can be improved to about 250 V, compared to about 50 VK when no clamp circuit is provided. Further, even when the clamp circuit is configured with non-quality Si thin film transistors, a breakdown voltage comparable to that described above is obtained. Note that the number of series-connected diodes at this time is 10, and the threshold value of the thin film transistor is 1 (N
'Met.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram of a conventional Max IJ drive drive close reading line sensor, Fig. 2 is a current-voltage characteristic of an amorphous Si pin junction diode, and Figs. 3 to 22 are explanatory diagrams of embodiments of the present invention. Fig. 3 is a circuit diagram with a clamp circuit using a diode string, Fig. 4 is a current-voltage characteristic diagram of the clamp circuit in Fig. 3, and Fig. 5 is a circuit diagram with a clamp circuit using a diode string and a thin film transistor. The circuit diagram shown in Figure 6 is
The current-voltage characteristic diagram of the clamp circuit shown in the figure, Figure 7 is a circuit diagram in which Figure 3 is applied to a line sensor, Figure 8 is a circuit diagram in which Figure 5 is applied to a line sensor, and Figures 9 to 13 are a circuit diagram in which Figure 5 is applied to a line sensor. Figure 3 Structural sectional view, plan view, and equivalent circuit diagram for the circuit, No. 14
18 are structural cross-sectional views, plan views, and equivalent circuit diagrams for the circuit shown in FIG. 5, and FIGS. 19 to 22 are diagrams showing examples of clamp circuits when thin film transistors are targeted for film preservation. 1... Separation diode, 2... Photodiode, 5
...grounded terminal, 7...electrified human hand,
13 Punishment 7 閤χ 21 z Circulation 19 Figure 21 B Continuation of page 1 0 Author: Hiroshi Seki - 1-280 Higashi Koigakubo, Kokubunji City, Hitachi, Ltd. Central Research Laboratory 0 Author: Toshihisa Tsukada 1-chome, Higashi Koigakubo, Kokubunji City 280 Hitachi, Ltd. Central Research Laboratory

Claims (1)

[Claims] 1. A semiconductor device protection circuit for protecting a semiconductor device from static electricity, which is formed by further connecting in parallel pin junction diodes or thin film transistors formed of amorphous Si, each of the series circuits described above. The breakdown voltage value of each series circuit is small between the common wiring, which is commonly placed between the input terminal and output terminal of the circuit and is fixed at a constant potential, and each input/output terminal of each series circuit. A semiconductor device IF protection circuit, characterized in that clamp circuits each having a clamp voltage value p larger than the driving voltage value thereof are provided. 2. The clamp circuit has one or even number of diode strings connected in series in the same direction, and one or a plurality of diode strings whose conduction direction is opposite to the above, connected in parallel. 2. The semiconductor device protection circuit according to claim 1, wherein the semiconductor device protection circuit is a clamp circuit configured as follows. 3. The clamp circuit includes one or a plurality of diode arrays connected in series in the same direction, and an amorphous diode array whose gate electrode is connected to a source or drain pole and whose conduction direction is opposite to that of the diode array. 2. The semiconductor device protection circuit according to claim 1, wherein the circuit is a clap circuit constructed by connecting in parallel a thin film anti-boost effect transistor made of silicon.