JP2001339044A - Electrostatic protection circuit for semiconductor device - Google Patents

Abstract

(57) Abstract: An object of the present invention is to provide an electrostatic protection circuit for a semiconductor device that can ensure a withstand voltage and suppress an increase in the area of a circuit. SOLUTION: Since a drain and a source are connected between an external terminal (52) and a power supply terminal (56) and a plurality of MOS transistors (54, 55) are stacked and connected, an external terminal (52) is provided. ) Is divided by a plurality of MOS transistors (54, 55), so that the reverse breakdown voltage of the PN junction of each MOS transistor can be made lower than that of the conventional MOS transistor. Thus, the area of the electrostatic protection circuit can be made smaller than before.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrostatic protection circuit for a semiconductor device, and more particularly to an electrostatic protection circuit for a MOS transistor which protects the semiconductor device from static electricity.

[0002]

2. Description of the Related Art Depending on the use of a semiconductor device, some external terminals may be required to have a higher breakdown voltage than other external terminals. In such a case, conventionally, an electrostatic protection circuit as shown in FIG. 5 is provided for an external terminal that requires a high withstand voltage.

FIG. 5 is an equivalent circuit diagram of an example of a conventional electrostatic protection circuit of a semiconductor device, and FIGS. 6 and 7 are a sectional view and a plan view, respectively. In FIG. 5, the semiconductor device 1
The 0 external terminal 12 is provided with a high-breakdown-voltage N-channel MOS transistor 14 as an electrostatic protection circuit. MO
The drain of the S transistor 14 is connected to the external terminal 12 of the semiconductor device 10, and the gate, source and back gate of the MOS transistor 14 are commonly connected to the ground level power supply terminal 16 of the semiconductor device 10. The external terminal 12 is connected to the internal circuit 18 via a current limiting resistor R1.
And a ground-level power supply terminal 1 of the semiconductor device 10.
6 and the power supply terminal 20 of the voltage VDD are connected to the internal circuit 1
8 is connected.

In FIG. 6 and FIG. 7, an N ^- type semiconductor substrate 2 is shown.
In order to obtain a high breakdown voltage, N-type regions 25 and 26 having a bar shape are formed in the P-type well 24 formed in the N-type region 2, and a N-type region having a bar shape serving as a source of the MOS transistor 14 is formed in the N-type region 25. A type region 27 (having a higher impurity concentration than the N-type regions 25 and 26) is formed, and an N-type region 28 (having a higher impurity concentration than the N-type regions 25 and 26) serving as a drain is formed in the N-type region 26. A P-type region 30 serving as a back gate is formed adjacent to the N-type region 27. A gate oxide film 32 is formed on the P-type well 24 between the N-type regions 25 and 26, a gate electrode 34 is provided on the gate oxide film 32, and the N-type region 27 and the P-type The source and back gate electrodes 3 are formed above the region 30.
6 is provided, and a drain electrode 38 is provided above the N-type region 28.
Is provided. The gate electrode 34, the source / back gate electrode 36, and the drain electrode 38 are each provided with a plurality of contacts shown in FIG.

Here, the N-type region 2 is provided in the P-type well 24.
A parasitic npn transistor having a collector 8, a P-type well 24 as a base, a diffusion resistance of the P-type well 24 as a base resistance, a connection to a P-type region 30 of a back gate, and an N-type region 27 as an emitter is formed. become. For this reason, when positive static electricity is applied to the external terminal 12, the parasitic npn transistor breaks down and a surge current flows from the external terminal 12 to the power supply terminal 16 at the ground level through the collector and the emitter of the parasitic npn transistor. The internal circuit 18 formed in the device is protected from static electricity. Here, the P-type well 24 and the N-type region 2
By providing the N-type regions 25 and 26 between the PN junctions 7 and 28, the breakdown voltage in the reverse direction of the PN junction is increased.

FIG. 8 is an equivalent circuit diagram of another example of a conventional electrostatic protection circuit of a semiconductor device, and FIGS. 9 and 10 are a sectional view and a plan view, respectively. 8, a diode 15 is provided at an external terminal 12 of the semiconductor device 10 as an electrostatic protection circuit. The cathode of the diode 15 is connected to the external terminal 12 of the semiconductor device 10, and the anode of the diode 15 is connected to the ground-level power supply terminal 16 of the semiconductor device 10. The external terminal 12 is connected to an internal circuit 18 via a current limiting resistor R1.
Each of the power supply terminals 16 and 20 at the ground level of the semiconductor device 10 is connected to the internal circuit 18.

In FIG. 9 and FIG. 10, a N ^- type semiconductor substrate 22 has a P-type region 40 serving as an anode of the diode 15.
Is formed, and N serves as a cathode of the diode 15.
A mold region 42 is formed. An anode 41 is formed above the P-type region 40, and a cathode 43 is formed above the N-type region 42. The anode electrode 41 and the cathode electrode 43 are provided with a plurality of contacts shown in a square or a rectangle in FIG.

Here, when positive static electricity is applied to the external terminal 12, a surge current in the reverse direction flows through the PN junction between the P-type region 40 and the N-type region 42, and an internal surge formed in the semiconductor device is formed. Protect circuit 18 from static electricity. Where P
Since the N ⁻ type semiconductor substrate 22 exists between the mold region 40 and the N type region 42, the breakdown voltage against the reverse voltage of the PN junction is increased.

[0009]

In the conventional electrostatic protection circuit shown in FIG. 5, since the MOS transistor 14 itself has a high withstand voltage, the MOS transistor 14 itself has a high withstand voltage, so that the PN junction between the P-type well 24 and the N-type regions 25 and 26 is formed. Since heat generation increases, the size of the MOS transistor 14 must be increased in order to increase the breakdown voltage, and there is a problem that the area of the electrostatic protection circuit increases.

In the conventional electrostatic protection circuit shown in FIG.
Similarly to the above, since the withstand voltage of the diode 15 itself is high, the heat generation at the PN junction between the P-type region 40 and the N ⁻ -type semiconductor substrate 22 increases, so that the size of the diode 15 is increased in order to increase the withstand voltage. Must be bigger,
There is a problem that the area constituting the electrostatic protection circuit becomes large.

SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and has as its object to provide an electrostatic protection circuit for a semiconductor device which can ensure a withstand voltage and suppress an increase in the area of a circuit. .

[0012]

According to the first aspect of the present invention, an internal circuit of the semiconductor device is not destroyed by static electricity which is provided between an external terminal and a power supply terminal of the semiconductor device and which enters the external terminal. In the electrostatic protection circuit of a semiconductor device to be protected, a plurality of the electrostatic protection circuits are stacked and connected between the external terminal (52) and the power supply terminal (56) by connecting their drains and sources to each other. MOS transistors (54, 55).

As described above, a plurality of MOS transistors (54, 5) connected in a stack between the external terminal (52) and the power supply terminal (56) by connecting their drains and sources to each other.
5), the voltage of the static electricity applied to the external terminal (52) is reduced by a plurality of MOS transistors (54, 55).
, The breakdown voltage in the reverse direction of the PN junction of each MOS transistor can be made lower than before, the configuration area of each MOS transistor can be made smaller, and the area of the electrostatic protection circuit as a whole can be made smaller than before. it can. Claim 2
The invention according to claim 1, wherein in the electrostatic protection circuit of the semiconductor device according to claim 1, the electrostatic protection circuit has a drain connected to an external terminal and a gate connected to a source commonly.
A channel MOS transistor and a second N-channel MOS transistor having a drain commonly connected to a gate and a source of the first N-channel MOS transistor, and a gate and a source commonly connected to the power supply terminal.

As described above, since the electrostatic protection circuit includes the first N-channel MOS transistor (54) and the second N-channel MOS transistor (55), the electrostatic protection circuit is applied to the external terminal (52). Is divided by the MOS transistors (54, 55), the breakdown voltage in the reverse direction of the PN junction of each MOS transistor (54, 55) can be made lower than before, and the configuration area of each MOS transistor can be reduced. As a whole, the area of the electrostatic protection circuit can be made smaller than before.

According to a third aspect of the present invention, in the electrostatic protection circuit of the semiconductor device according to the first aspect, the first electrostatic protection circuit has a drain connected to an external terminal and a gate and a source commonly connected. N channel MOS transistor (5
4), a second N-channel MOS transistor (55) having a drain commonly connected to the gate and source of the first N-channel MOS transistor, and a gate and source commonly connected, and a drain connected to the second N-channel MOS transistor. Channel MOS
A third N-channel MOS transistor (57) commonly connected to the gate and source of the transistor, and having the gate and source commonly connected to the power supply terminal.

As described above, the electrostatic protection circuit includes the first N-channel MOS transistor (54), the second N-channel MOS transistor (55), and the third N-channel M transistor.
With the OS transistor (57), the withstand voltage of the electrostatic protection circuit can be further increased.

Note that the reference numerals in the parentheses are provided for easy understanding, are merely examples, and are not limited to the illustrated embodiment.

[0018]

FIG. 1 is an equivalent circuit diagram of a first embodiment of an electrostatic protection circuit for a semiconductor device according to the present invention, and FIGS. 2 and 3 are a sectional view and a plan view, respectively. In FIG. 1, N-channel MOS transistors 54 and 55 are provided at an external terminal 52 of a semiconductor device 50 as an electrostatic protection circuit. The drain of the MOS transistor 54 is connected to the external terminal 52 of the semiconductor device 50 which requires a high withstand voltage. The gate, source and back gate of the MOS transistor 54 are commonly connected to the drain of the MOS transistor 55. The gate, the source, and the back gate are commonly connected to a ground-level power supply terminal 56 of the semiconductor device 50, and the MOS transistor 54,
Numerals 55 are stacked and connected by connecting their drains and sources. The external terminal 52 is connected to a current limiting resistor R.
5 and a power supply terminal 56 of the ground level of the semiconductor device 50 and a power supply terminal 6 of the voltage VDD.
0 are connected to the internal circuit 58.

[0019] In FIGS. 2 and 3, N ^- -type semiconductor substrate 6
2, P-type wells 64 and 84 are formed, and a P-type well 6 is formed.
An N-type region 66 having a rod-like planar shape as a source of the MOS transistor 54 and an N-type region 68 as a drain are formed in the MOS transistor 54, and a P-type region 70 as a back gate is formed adjacent to the N-type region 66. Have been. N-type regions 66, 68
A gate oxide film 72 having a U-shape in plan view is formed above the P-type well 64 therebetween, and a gate electrode 74 is provided above the gate oxide film 72.
The source and back gate electrodes 76 are provided above the P-type region 6 and the P-type region 70, and the drain electrode 78 is provided above the N-type region 68.

In the N ^- type semiconductor substrate 62, an N-type region 86 having a rod-like planar shape as a source of the MOS transistor 55 and an N-type region 88 as a drain are formed in a P-type well 84 formed in the N ^- type semiconductor substrate 62. A P-type region 90 serving as a back gate is formed adjacent to the N-type region 86. A U-shaped gate oxide film 92 is formed on the P-type well 84 between the N-type regions 86 and 88, and a gate electrode 94 is provided on the gate oxide film 92. A source and back gate electrode 96 is provided above the N-type region 86 and the P-type region 90, and a drain electrode 98 is provided above the N-type region 88.

The gate electrodes 74 and 94, the source and back gate electrodes 76 and 96, and the drain electrodes 78 and 98
Each is provided with a plurality of contacts, shown as squares or rectangles in FIG. Each electrode 74, 76, 78,
Any of the contacts provided on each of the electrodes 94, 96, 98 may be selected according to the wiring or the like for each electrode.

Each of the MOS transistors 54 and 55 is of a normal type (not high withstand voltage) having no N-type region between the P-type wells 64 and 84 and the N-type regions 66 and 88. The drain electrode 78 of the transistor 54 is connected to the external terminal 52 by a wiring 100,
The gate electrode 74 of the OS transistor 54 and the source and back gate electrodes 76 are commonly connected by a wiring 102, and connected to the drain electrode 98 of the MOS transistor 55 by a wiring 104, and the gate electrode 9 of the MOS transistor 55
4 and the source and back gate electrodes 96 are commonly connected to the power supply terminal 56 at the ground level by the wiring 106.

Here, the N-type region 6 is provided in the P-type well 64.
A parasitic npn transistor having a collector 8, a P-type well 64 as a base, a diffusion resistance of the P-type well 64 as a base resistance, a connection to a P-type region 70 of a back gate, and an N-type region 66 as an emitter is formed. In the P-type well 84, the N-type region 88 is used as a collector, the P-type well 84 is used as a base, the diffusion resistance of the P-type well 84 is used as a base resistance, and the N-type region 86 is connected to the back gate. A parasitic npn transistor serving as an emitter is formed.

When positive static electricity is applied to the external terminal 52, the voltage of this static electricity is applied to the MOS transistors 54, 5
5, the parasitic npn transistors of the MOS transistors 54 and 55 are turned on, and a surge current flows from the external terminal 52 to the power supply terminal 56 at the ground level through the collector and the emitter of the parasitic npn transistor. The internal circuit 58 is protected from static electricity.

Here, since the voltage of the static electricity is divided by the MOS transistors 54 and 55, the MOS transistor 5
4 between the P-type well 64 and the N-type regions 66 and 68
The reverse breakdown voltage of the junction and the P of the MOS transistor 55
The withstand voltage in the reverse direction of the PN junction between the mold well 84 and the N-type regions 86 and 88 can be reduced to half of that in the related art. Therefore, the area per one of the MOS transistors 54 and 55 can be reduced to half or less of the area constituting the conventional circuit shown in FIG. 7, and the area of the electrostatic protection circuit can be reduced as a whole as compared with the conventional circuit. .

FIG. 4 is an equivalent circuit diagram of a second embodiment of the electrostatic protection circuit of the semiconductor device according to the present invention. In FIG. 4, N-channel MOS transistors 54, 55, and 57 are provided at an external terminal 52 of the semiconductor device 50 as an electrostatic protection circuit. The drain of the MOS transistor 54 is connected to the external terminal 52 of the semiconductor device 50 which requires a high withstand voltage. The gate, source and back gate of the MOS transistor 54 are commonly connected to the drain of the MOS transistor 55. The gate, source and back gate are commonly connected to the drain of the MOS transistor 57, and the gate, source and back gate of the MOS transistor 57 are commonly connected to the ground level power supply terminal 56 of the semiconductor device 50, and the MOS transistors 54 and 55 , 57 are connected vertically by connecting their drains and sources. The external terminal 52 is connected to the internal circuit 58 via a current limiting resistor R5, and is connected to the ground level power supply terminal 56 and the power supply terminal 6 of the semiconductor device 50.
0 are connected to the internal circuit 58.

In this embodiment, since the voltage of the static electricity is divided by the MOS transistors 54, 55 and 57, the withstand voltage of the external terminal 52 can be 1.5 times that of the embodiment of FIG. As described above, by increasing the number of stages of MOS transistors connected in series between the external terminal and the power supply terminal at the ground level, the withstand voltage required for the external terminal can be freely selected.

[0028]

As described above, since the drain and the source are connected between the external terminal and the power supply terminal and the MOS transistors are stacked and connected, the voltage of the static electricity applied to the external terminal is reduced. The voltage is divided by a plurality of MOS transistors, the breakdown voltage in the reverse direction of the PN junction of each MOS transistor can be made lower than before, the configuration area of each MOS transistor can be made smaller, and the area of the electrostatic protection circuit as a whole becomes larger than before Can be smaller.

According to a second aspect of the present invention, the electrostatic protection circuit comprises a first N-channel MOS transistor and a second N-channel MOS transistor.
Since it is composed of a channel MOS transistor, the voltage of the static electricity applied to the external terminal is divided by each MOS transistor, so that the reverse breakdown voltage of the PN junction of each MOS transistor can be made lower than that of the conventional MOS transistor. The configuration area can be reduced, and the area of the electrostatic protection circuit can be reduced as a whole as compared with the related art.

According to a third aspect of the present invention, the electrostatic protection circuit comprises a first N-channel MOS transistor and a second N-channel MOS transistor.
Channel MOS transistor and third N-channel MO
With the S transistor, the withstand voltage of the electrostatic protection circuit can be further increased.

[Brief description of the drawings]

FIG. 1 is an equivalent circuit diagram of a first embodiment of an electrostatic protection circuit of a semiconductor device according to the present invention.

FIG. 2 is a sectional configuration diagram of a first embodiment of the electrostatic protection circuit of the semiconductor device of the present invention.

FIG. 3 is a plan view of a first embodiment of the electrostatic protection circuit of the semiconductor device of the present invention.

FIG. 4 is an equivalent circuit diagram of a second embodiment of the electrostatic protection circuit of the semiconductor device according to the present invention.

FIG. 5 is an equivalent circuit diagram of an example of a conventional electrostatic protection circuit of a semiconductor device.

FIG. 6 is a sectional structural view of an example of a conventional electrostatic protection circuit of a semiconductor device.

FIG. 7 is a plan view showing an example of a conventional electrostatic protection circuit of a semiconductor device.

FIG. 8 is an equivalent circuit diagram of another example of the electrostatic protection circuit of the conventional semiconductor device.

FIG. 9 is a sectional structural view of another example of the electrostatic protection circuit of the conventional semiconductor device.

FIG. 10 is a plan view showing another example of a conventional electrostatic protection circuit of a semiconductor device.

[Explanation of symbols]

 Reference Signs List 50 semiconductor device 52 external terminal 54, 55 N-channel MOS transistor 58 internal circuit 64, 84 P-type well 66, 68, 86, 88 N-type region 70, 90 P-type region 72, 92 Gate oxide film 74, 94 Gate electrode 76 , 96 Source and back gate electrodes 78, 98 Drain electrodes

Claims (3)

[Claims] 1. An electrostatic protection circuit for a semiconductor device, which is provided between an external terminal and a power supply terminal of the semiconductor device and protects an internal circuit of the semiconductor device from being damaged by static electricity entering the external terminal. An electrostatic protection circuit for a semiconductor device, comprising: a plurality of MOS transistors stacked and connected by connecting a drain and a source between the external terminal and a power supply terminal. 2. The electrostatic protection circuit of a semiconductor device according to claim 1, wherein said electrostatic protection circuit has a first N-channel MOS having a drain connected to an external terminal and a gate and a source commonly connected.
A semiconductor comprising: a transistor; and a second N-channel MOS transistor having a drain commonly connected to a gate and a source of the first N-channel MOS transistor, and a gate and a source commonly connected to the power supply terminal. Equipment electrostatic protection circuit. 3. The static electricity protection circuit according to claim 1, wherein said static electricity protection circuit has a drain connected to an external terminal and a gate and a source connected in common.
A transistor, a drain commonly connected to the gate and the source of the first N-channel MOS transistor, and a gate and a source commonly connected to each other; a drain connected to the second N-channel MOS transistor; An electrostatic protection circuit for a semiconductor device, comprising: a third N-channel MOS transistor commonly connected to a gate and a source; and a gate and a source commonly connected to the power supply terminal.