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JPH1187401A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH1187401A
JPH1187401A JP9281038A JP28103897A JPH1187401A JP H1187401 A JPH1187401 A JP H1187401A JP 9281038 A JP9281038 A JP 9281038A JP 28103897 A JP28103897 A JP 28103897A JP H1187401 A JPH1187401 A JP H1187401A
Authority
JP
Japan
Prior art keywords
copper foil
layer
copper
terminals
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9281038A
Other languages
Japanese (ja)
Inventor
Haruki Yokono
春樹 横野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Priority to JP9281038A priority Critical patent/JPH1187401A/en
Publication of JPH1187401A publication Critical patent/JPH1187401A/en
Pending legal-status Critical Current

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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
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    • H01L2224/481—Disposition
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

(57)【要約】 【目的】半導体集積回路素子の多ピン化、小型化、高機
能化などの進歩に対応できる半導体集積回路素子および
半導体集積回路素子パッケージの電極端子と電子回路の
端子との接続構造を、信頼性の高い方法で実現するこ
と。 【構成】半導体集積回路素子および半導体集積回路素子
パッケージの各電極端子と、少なくとも銅、銅合金およ
びそれらの酸化物からなる銅はくを用いて製造された電
子回路上の端子を半田などを介して接続した半導体装置
で、その銅はくは、接着基材との接着面に金属、合金、
酸化物、水酸化物、および水和物から選ばれる一層以上
の被覆層を有し、その上にシラザン系化合物の加熱加湿
分解により生成したシリカ層がある。接着基材は高強
度、高伸び性もつ合成樹脂層で、銅はくと積層基材を接
着する。半導体側の端子から数えて半田などの接続層、
銅はく層、金属被覆層、シリカ層、接着基材層および積
層基材層からなる少なくとも六乃至七層の接続層構成を
持つ半導体装置。 (57) [Abstract] [Purpose] A combination of electrode terminals of a semiconductor integrated circuit device and a semiconductor integrated circuit device package and terminals of an electronic circuit which can cope with the progress of multi-pin, miniaturization, and enhancement of functions of the semiconductor integrated circuit device. Realize the connection structure in a reliable way. A semiconductor integrated circuit device and each electrode terminal of the semiconductor integrated circuit device package, and terminals on an electronic circuit manufactured using at least a copper foil made of copper, a copper alloy, and an oxide thereof are soldered. The semiconductor device is connected by a metal, alloy,
It has one or more coating layers selected from oxides, hydroxides, and hydrates, and a silica layer formed by heating and humidifying decomposition of a silazane-based compound thereon. The adhesive substrate is a synthetic resin layer having high strength and high elongation, and adheres the copper foil and the laminated substrate. Connection layer such as solder, counting from the terminal on the semiconductor side,
A semiconductor device having at least six to seven connection layer structures including a copper foil layer, a metal coating layer, a silica layer, an adhesive substrate layer, and a laminated substrate layer.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【産業上の利用分野】本発明は、半導体集積回路素子お
よび半導体集積回路素子パッケージと電子回路の接続構
造に関する。The present invention relates to a semiconductor integrated circuit device and a connection structure between a semiconductor integrated circuit device package and an electronic circuit.

【０００２】[0002]

【従来の技術】半導体集積回路素子および半導体集積回
路素子パッケージの各電極端子は、所望の目的および用
途に適合するように設計された電子回路の端子にボンデ
ングワイア、半田あるいは異方導電性接着フイルムなど
によって接続された半導体装置として使用される。2. Description of the Related Art Each electrode terminal of a semiconductor integrated circuit device and a package of a semiconductor integrated circuit device is bonded to a terminal of an electronic circuit designed to meet a desired purpose and use by bonding wire, solder or anisotropic conductive adhesive. It is used as a semiconductor device connected by a film or the like.

【０００３】現在までの半導体集積回路素子は、パッケ
ージと称して素子をプラスチックで封止したり、セラミ
ック配線板に実装されたモジュールのかたちで使われて
きた。この代表的なものがＱＦＰである。ＱＦＰの場合
は、素子の各電極はリードフレームを介して電子回路に
接続される。現在でも、電子機器に使用される半導体集
積回路素子は、このＱＦＰが主流となっているが、ＱＦ
Ｐに対する素子の面積比率は１５〜５０％にすぎず、電
子機器の小型化や高機能化のながれの中で、この面積比
率を大幅に改善し実装密度の向上を図るとともに、さら
に高集積化の実現をはかる技術開発が活発に行われてい
る。これにともなって端子の数も飛躍的に増加し、多ピ
ン化、狭ピッチ化が図られてきたが、電子回路として主
流となっているプリント配線板の細線化、高密度化技術
に限界があることから、半導体集積回路素子パッケージ
と素子の面積比率の向上と実装密度の向上を目的として
ＴＡＢ、ＭＣＭ、ＢＧＡ、ＣＳＰあるいはＩＣベアチッ
プ実装と称される新しい実装法による半導体装置が生ま
れてきている。（日経エレクトロニクス１９９５．１．
１６号ｐ７９ 参照）Until now, semiconductor integrated circuit devices have been used in the form of a module called a package in which the device is sealed with plastic or mounted on a ceramic wiring board. A typical example is a QFP. In the case of QFP, each electrode of the element is connected to an electronic circuit via a lead frame. At present, the QFP is the mainstream in semiconductor integrated circuit devices used in electronic devices.
The area ratio of the element to P is only 15% to 50%, and in the course of miniaturization and high functionality of electronic devices, this area ratio is largely improved to improve the mounting density and further increase the integration. Technology development for realizing is being actively carried out. Along with this, the number of terminals has increased dramatically, and the number of pins has been increased and the pitch has been reduced.However, there is a limit to the thinning and high-density technology of printed wiring boards, which are the mainstream in electronic circuits. Therefore, a semiconductor device using a new mounting method called TAB, MCM, BGA, CSP or IC bare chip mounting has been born for the purpose of improving the area ratio between the semiconductor integrated circuit device package and the device and improving the mounting density. . (Nikkei Electronics 1995.1.
No.16 p79)

【０００４】ここに云う電子回路は、銅はくと積層基材
が積層接着された銅張り積層体の銅はくを、所望の回路
にプリント回路技術によって加工したプリント配線板
（“プリント回路技術便覧”１９９３年２月２４日 日
刊工業新聞社刊 参照）で、回路機能を満たしているも
のをいう。ここに使用される銅はくは、製造方法により
電解銅はくと圧延銅はくに分けられる。その厚さは、３
５および１８μｍのものが主である。このほか厚さの大
きいものでは７０および１０５μｍ、薄いものでは１２
および９μｍのものが実用されている。[0004] The electronic circuit referred to here is a printed wiring board ("printed circuit technology") in which copper foil and a copper-clad laminate having a laminated base material laminated and adhered are processed into a desired circuit by a printed circuit technology. Handbook, "February 24, 1993, published by Nikkan Kogyo Shimbun"), which satisfies the circuit function. The copper foil used here is classified into electrolytic copper foil and rolled copper foil according to the manufacturing method. Its thickness is 3
Mainly 5 and 18 μm. In addition, 70 and 105 μm for a thick one, and 12 for a thin one.
And 9 μm are in practical use.

【０００５】この銅張り積層体に使用される銅はくは、
電子回路に加工後も端子が安定的に固定されるよう積層
基材との接着を強固なものとするため、粗化と称して銅
はく表面に銅、銅合金およびそれらの酸化物からなる粗
化微粒子が付着して凹凸状となっている。その凹凸の度
合い、すなわち粗さは、ＪＩＳ−Ｂ−０６０１に規定さ
れた中心線平均粗さで０．５から３．０μｍ程度であ
る。この粗化微粒子による凹凸は、銅はくが積層基材に
加熱圧着され積層体を造るとき、投錨効果による物理的
な接着力を発現させるためのもので、プリント配線板が
初めて実用されるようになった時から、この方法によっ
て全てのプリント配線板が造られて今日に至った。この
ように従来のプリント配線板は、物理的な接着を主原理
として銅はくと積層基材が積層された銅張り積層体から
造られている。従って、半導体集積回路素子およびその
パッケージの各電極端子が、ボンデングワイア、半田ま
たは異方導電性接着フイルムなどを介して電子回路の端
子と接続した構造の半導体装置は、この銅、銅合金およ
びそれらの酸化物からなる粗化微粒子が付着して凹凸状
となった面を積層基材との接着面とし、その反対面は電
解銅はくにあっては電解用の電極面、圧延銅はくにあっ
ては圧延ロール面が転写されて出来た銅はく面が半導体
集積回路素子およびそのパッケージの各電極端子と接続
された構造となっている。その接続面の粗さは、通常
０．３５μｍ以下である。銅はくの表面は電子回路の上
下の導通回路であるスルーホールやバイヤホールの電導
性付与のために銅めっきを行う時、同時に銅めっきされ
ることが多く、このような場合には半導体集積回路素子
およびそのパッケージの各電極端子は、この銅めっきさ
れた電子回路の端子上に接続されることになる。また電
子回路の端子は、接続信頼性を高めるために半田めっき
や金めっきなどがなされ、その上に半導体集積回路を接
続することもある。[0005] The copper foil used in the copper-clad laminate is
It is made of copper, copper alloy and their oxides on the copper foil surface called roughening to strengthen the adhesion with the laminated substrate so that the terminals are stably fixed even after processing into the electronic circuit The roughened fine particles are attached to form irregularities. The degree of the unevenness, that is, the roughness is about 0.5 to 3.0 μm as a center line average roughness specified in JIS-B-0601. The irregularities due to the roughened fine particles are for expressing the physical adhesive force due to the anchoring effect when the copper foil is heat-pressed to the laminated base material to form a laminate, so that the printed wiring board is practically used for the first time. Since then, all printed wiring boards have been manufactured by this method to this day. As described above, the conventional printed wiring board is made of a copper-clad laminate in which a copper foil and a laminated base material are laminated on the basis of physical bonding as a main principle. Therefore, a semiconductor device having a structure in which each electrode terminal of a semiconductor integrated circuit element and its package is connected to a terminal of an electronic circuit via a bonding wire, solder, anisotropic conductive adhesive film, or the like, has a copper, copper alloy and The roughened fine particles composed of these oxides adhered and the surface that became uneven was used as the bonding surface with the laminated base material, and the opposite surface was the electrode surface for electrolysis for electrolytic copper foil, rolled copper foil In this case, the copper foil formed by transferring the roll surface is connected to each electrode terminal of the semiconductor integrated circuit device and its package. The roughness of the connection surface is usually 0.35 μm or less. The surface of copper foil is often plated at the same time as copper plating is performed to provide conductivity for through-holes and via-holes, which are conductive circuits above and below electronic circuits. Each electrode terminal of the circuit element and its package will be connected to the terminal of this copper-plated electronic circuit. Also, terminals of the electronic circuit are plated with solder or gold in order to improve connection reliability, and a semiconductor integrated circuit may be connected thereon.

【０００６】半導体集積回路素子およびそのパッケージ
の各電極端子とボンデングワイア、半田または異方導電
性接着フイルムなどを介して接続された電子回路上の端
子は接着基材層を介して積層基材と積層体を構成してい
る。銅はくと積層基材との接着基材は、エポキシ樹脂な
どの合成樹脂積層基材自体が接着基材の役割をはたすも
のと、フエノール樹脂、ポリイミド樹脂フイルムやポリ
エステル樹脂フイルムなどそれぞれに適した接着剤を用
いるものがある。フエノール樹脂は、ポリビニルブチラ
ールとフエノール樹脂、メラミン樹脂、エポキシ樹脂な
どの熱硬化性樹脂との複合物を主成分とする接着剤（例
えば日本特許第７１３．７８０号）、ポリイミド樹脂フ
イルムおよびポリエステル樹脂フイルムでは、例えばア
クリル系やイソシヤネート系の接着剤などが通常用いら
れる。接着基材層の厚さは、通常２０〜５０μｍであ
る。この接着基材層と銅はくの界面には、シランカップ
リング剤を使用することも常識的に行われている。The terminals on the electronic circuit connected to the respective electrode terminals of the semiconductor integrated circuit element and its package via bonding wires, solder or anisotropic conductive adhesive films, etc. are laminated base materials via an adhesive base material layer. And a laminate. Adhesive base material with copper foil and laminated base material is suitable for synthetic resin laminated base material such as epoxy resin itself which plays the role of adhesive base, phenolic resin, polyimide resin film and polyester resin film etc. Some use an adhesive. The phenol resin is an adhesive mainly composed of a composite of polyvinyl butyral and a thermosetting resin such as a phenol resin, a melamine resin, and an epoxy resin (for example, Japanese Patent No. 713.780), a polyimide resin film and a polyester resin film. For example, an acrylic or isocyanate-based adhesive is usually used. The thickness of the adhesive base material layer is usually 20 to 50 μm. It is common practice to use a silane coupling agent at the interface between the adhesive base layer and the copper foil.

【０００７】銅はくと積層体を構成する積層基材には、
フエノール樹脂、エポキシ樹脂、ポリイミド樹脂、ポリ
エステル樹脂、ＢＴレジン、ＰＰＯなどが使用されてい
る。フエノール樹脂の場合は紙、エポキシ樹脂の場合は
ガラス繊維布や不織布、ポリイミド樹脂およびＢＴレジ
ンの場合はガラス繊維布を補強基材として銅はくと積層
体を造っている。最近では、アラミド繊維布や不織布も
エポキシ樹脂、ポリイミド樹脂およびＢＴレジンの補強
基材として用いられている。またポリイミド樹脂および
ポリエステル樹脂の場合は、紙やガラス繊維布などの補
強基材を含まないフイルム状の物が用いられることも多
い。これを用いた配線板は、フレキシブルプリント配線
板と称して、立体的な屈曲した状態で使用されたり、Ｔ
ＡＢと称する半導体集積回路素子のテープキャリアとし
て使用されている。合成樹脂積層基材の厚さは、通常
０．０５〜１．６ｍｍとなっている。このほか最近で
は、厚さ２．０ｍｍ以下の鉄板、ステンレス板やアルミ
ニウム板などの金属板も積層基材として使用されてい
る。[0007] The copper foil and the laminated base material constituting the laminated body include:
A phenol resin, an epoxy resin, a polyimide resin, a polyester resin, BT resin, PPO and the like are used. A copper foil laminate is formed using paper as a phenolic resin, glass fiber cloth or non-woven fabric as an epoxy resin, and glass fiber cloth as a base material as a polyimide resin or BT resin. Recently, aramid fiber cloths and nonwoven fabrics have also been used as reinforcing substrates for epoxy resins, polyimide resins and BT resins. In the case of a polyimide resin or a polyester resin, a film-like material that does not include a reinforcing substrate such as paper or glass fiber cloth is often used. A wiring board using this is called a flexible printed wiring board and is used in a three-dimensional bent state,
It is used as a tape carrier for a semiconductor integrated circuit device called AB. The thickness of the synthetic resin laminated base material is usually 0.05 to 1.6 mm. In addition, recently, an iron plate having a thickness of 2.0 mm or less, a metal plate such as a stainless steel plate or an aluminum plate has also been used as a laminated base material.

【０００８】以上に述べたように、半導体集積回路素子
および半導体集積回路素子のパッケージの各電極端子
は、ボンデングワイア、半田や異方導電性接着フイルム
などの接合剤によって電子回路上の銅はくから造られた
端子に接続されて、電子回路上で半導体装置となる。そ
の銅はくから出来た端子は、接着基材層を介し、あるい
は直接積層基材と積層接着された層構成となっている。
このとき銅はくの積層基材との接着面は、銅、銅合金お
よびそれらの酸化物からなる粗化微粒子による凹凸状の
面を持っていることが、半導体集積回路素子およびその
パッケージおよびプリント配線板が開発された時から行
われてきた半導体装置の接続構造となっている。As described above, the electrode terminals of the semiconductor integrated circuit device and the package of the semiconductor integrated circuit device are connected to the copper on the electronic circuit by a bonding agent such as bonding wire, solder or anisotropic conductive adhesive film. The semiconductor device is connected to a terminal manufactured from the electronic circuit and becomes a semiconductor device on an electronic circuit. The terminal made of the copper foil has a layer configuration in which the terminal is laminated and adhered to the laminated substrate via an adhesive substrate layer or directly.
At this time, the bonding surface of the copper foil with the laminated base material has an uneven surface formed by roughened fine particles composed of copper, a copper alloy and their oxides. The connection structure of the semiconductor device has been used since the wiring board was developed.

【０００９】[0009]

【発明が解決しようとする課題】前述のように、従来の
半導体集積回路素子およびそのパッケージの各電極端子
は、銅、銅合金およびそれらの酸化物からなる粗化微粒
子の存在する銅はくを用いた電子回路上の端子と接合さ
れて、半導体装置を構成していた。しかしながら半導体
集積回路素子の実装密度の向上と高集積化、それに伴う
電極端子の多ピン化、狭ピッチ化のながれの中で、電子
回路の微細加工の向上が、この半導体側の進歩に追随出
来ず下記の問題点を生じ、その解決が課題となってい
た。As described above, each electrode terminal of a conventional semiconductor integrated circuit device and its package is made of a copper foil containing coarse particles made of copper, a copper alloy and their oxides. The semiconductor device is constituted by being joined to the terminal on the used electronic circuit. However, as the mounting density and integration of semiconductor integrated circuit elements increase, the number of electrode terminals increases, and the pitch decreases, the fine processing of electronic circuits can keep up with the progress on the semiconductor side. The following problems have arisen, and the solution has been an issue.

【００１０】（１）電子回路形成のために、銅張り積層
体の表面の銅はくは化学薬品によるエッチング加工によ
って不必要な銅はくが除去される。このとき銅はくと接
着基材との接着面にある銅、銅合金およびそれらの酸化
物からなる粗化微粒子を除去する時間は、粒子が接着基
材層に理没しているために粗化微粒子の無い場合のエッ
チングに要する時間の１．５倍以上かかる。このために
図７に示すように銅はくの端面がえぐられて接着面の実
質的な幅は、極端な場合には設計値の約６０％となり、
さらに微粒子状の銅、銅合金およびそれらの酸化物層と
接着基材との接着面に沿ってエッチング液が染み込み、
エッチングされた銅はくの端部周辺の接着力が著しく低
下する現象がある。このために微細加工幅の限界は、厚
さ３５μｍの銅はくで導体幅１００μｍ、配線ピッチは
３００μｍ（ＴＡＢでは、１００μｍ）までとされてい
る。現在、携帯用電子機器はじめ電子計算機などの電子
機器の小型化、高機能化のながれのなかで、前述のとお
り半導体集積回路の高集積化が急速に進展し、半導体集
積回路素子およびそのパッケージの各電極端子の多ピン
化、狭ピッチ化が急速に進んでいる。ところが、プリン
ト配線板の微細加工が前述のとおり導体幅１００μｍ、
配線ピッチ３００μｍが限界となっており、更なる微細
加工が課題とされている。この解決策として最近、粗化
微粒子による凹凸を出来るだけ小さくする試みや、ビル
ドアップ基板と称する回路を無電解めっきにより形成す
る高密度回路板が開発されており、配線ピッチ１００乃
至１５０μｍが可能とされているが、価格および技術的
な点でまだ汎用品に適用されるまでにはいたっていな
い。さらに将来を睨んで、配線ピッチ５０μｍ前後の狭
ピッチ配線回路加工の必要性が叫ばれている。（日経エ
レクトロニクス１９９５．４．１０号ｐ１００参照）(1) For forming an electronic circuit, unnecessary copper foil is removed from the surface of the copper-clad laminate by etching with a chemical or a chemical. At this time, the time required to remove coarse particles made of copper, copper alloy and their oxides on the bonding surface between the copper foil and the adhesive substrate is long because the particles are submerged in the adhesive substrate layer. It takes 1.5 times or more the time required for etching when no fine particles are present. Therefore, as shown in FIG. 7, the end face of the copper foil is cut off, and the substantial width of the bonding surface becomes about 60% of the design value in an extreme case.
Further, the etching solution penetrates along the bonding surface between the particulate copper, the copper alloy and the oxide layer thereof and the bonding substrate,
There is a phenomenon that the adhesive strength around the edge of the etched copper foil is significantly reduced. For this reason, the limit of the fine processing width is set to a copper width of 35 μm, a conductor width of 100 μm, and a wiring pitch of 300 μm (100 μm in TAB). At present, as electronic devices such as portable electronic devices and electronic computers are becoming smaller and more sophisticated, high integration of semiconductor integrated circuits is rapidly progressing as described above, and semiconductor integrated circuit elements and their packages are being developed. Increasing the number of pins and narrowing the pitch of each electrode terminal are rapidly advancing. However, the fine processing of the printed wiring board has a conductor width of 100 μm as described above,
The wiring pitch is limited to 300 μm, and further fine processing has been an issue. As a solution to this, recently, attempts have been made to reduce the irregularities due to the coarse particles as much as possible, and a high-density circuit board in which a circuit called a build-up substrate is formed by electroless plating has been developed, and a wiring pitch of 100 to 150 μm is possible. However, it has not yet been applied to general-purpose products in terms of price and technology. In view of the future, the necessity of processing a narrow-pitch wiring circuit with a wiring pitch of about 50 μm has been raised. (See Nikkei Electronics 1995.4.10 p100)

【００１１】（２）電子回路の端子の周囲は、接着基材
に理没した銅、銅合金およびそれらの酸化物からなる粗
化微粒子を除去した跡が図７に示すように微少な穴とな
って存在している。この穴が禍して、隣あう端子の半田
どうしがブリッジを起こす原因となったり、塵が着きや
すく取り除きにくいという問題がある。またエッチング
液やフラックスなどの薬液も、穴の中に残りやすく洗滌
を難しくしている。(2) Around the terminals of the electronic circuit, traces of removal of roughened fine particles made of copper, copper alloy, and their oxides, which are submerged in the adhesive base, have fine holes as shown in FIG. It exists. This hole causes a problem that solder between adjacent terminals may cause a bridge, and that dust easily adheres and is difficult to remove. In addition, chemicals such as an etching solution and a flux easily remain in the holes, making cleaning difficult.

【００１２】（３）半導体集積回路に入出力される電気
信号は、高周波電気信号である。周知のように電気は、
導体の表面を伝わっていく性質がある。導体の表面が粗
であると電気信号の反射、エネルギーの損失やノイズを
生じやすく、特に超高周波電気信号の場合や音楽の録音
再生の場合に伝送信頼性が問題となっている。(3) The electric signal input / output to / from the semiconductor integrated circuit is a high-frequency electric signal. As is well known, electricity is
It has the property of transmitting along the surface of a conductor. If the surface of the conductor is rough, reflection of an electric signal, energy loss and noise are likely to occur, and transmission reliability is a problem particularly in the case of an ultra-high frequency electric signal and in the case of recording and reproducing music.

【００１３】（４）高度な電子機器の発達、普及が進む
なかで、製造コストの低減が必須の事項である。半導体
装置は、いままで半導体集積回路本体のコストパーホー
マンスの向上や半田付けなどの実装工程の合理化を行っ
てコストを低減してきたが、電子回路のコストは、微細
加工の限界が壁となって、高多層化の方向や無電解めっ
きによる方法などを模索しており、逆にコスト上昇をき
たしているのが実状である。このような背景のもとに半
導体装置全体としてのコストミニマム化という観点か
ら、半導体集積回路が実用されて以来、基本的に変わっ
ていない電子回路の構成にメスをいれる必要性が要望さ
れるようになってきた。このような事から、粗化銅はく
を使用した銅張り積層体の材料費を分析すると、銅はく
のコストが約５０％を占めており、この大幅な低減が課
題となっている。(4) With the development and spread of advanced electronic devices, it is essential to reduce manufacturing costs. The cost of semiconductor devices has been reduced by improving the cost performance of the semiconductor integrated circuit body and rationalizing the mounting process such as soldering, but the cost of electronic circuits has been limited by the limitations of microfabrication. However, they are exploring the direction of increasing the number of layers and a method using electroless plating, and conversely, the cost is actually increasing. Against this background, from the viewpoint of minimizing the cost of the semiconductor device as a whole, it has been demanded that the necessity of using a scalpel for an electronic circuit configuration which has not changed basically since the semiconductor integrated circuit was put into practical use. It has become Therefore, when analyzing the material cost of the copper-clad laminate using the roughened copper foil, the cost of the copper foil occupies about 50%, and a significant reduction has been a problem.

【００１４】[0014]

【課題を解決するための手段】本発明者は、前記課題を
解決するために鋭意研究を進めた結果、接着基材との接
着面に銅、銅合金およびそれらの酸化物からなる粗化微
粒子の存在しない銅はくを銅張り積層体に使用し、これ
を回路加工して電子回路の端子とし、半導体集積回路側
の端子と接続すると、これらの課題が解決されることを
確認し、これを実現するために銅張り積層体の銅はくと
積層基材の接着に、新しい接着原理を導入して本発明の
実現に成功した。Means for Solving the Problems The inventors of the present invention have made intensive studies to solve the above-mentioned problems, and as a result, roughened fine particles made of copper, a copper alloy and their oxides were formed on the surface to be bonded to the bonding substrate. It is confirmed that these problems can be solved by using copper foil that does not exist in a copper-clad laminate, processing it as a terminal of an electronic circuit, and connecting it to a terminal on the semiconductor integrated circuit side. In order to realize the above, the present invention was successfully realized by introducing a new bonding principle into the bonding between the copper foil and the laminated base material of the copper-clad laminate.

【００１５】即ち、（１）半導体集積回路素子の複数の
信号系端子、接地端子および電源端子または半導体集積
回路素子パッケージの複数の信号系端子、接地端子およ
び電源端子が、ボンデングワイア、半田または異方導電
性接着フイルムなどを介して、電子回路上の端子と接続
してなる半導体装置において、電子回路の端子が少なく
とも銅、銅合金およびそれらの酸化物からなる粗化微粒
子の存在しない銅はくから形成された半導体装置。 （２）、（１）記載の銅はくの半導体集積回路との接続
面の反対面にＢ，Ａｌ，Ｐ，Ｚｎ，Ｔｉ，Ｖ，Ｃｒ，Ｍ
ｎ，Ｆｅ，Ｃｏ，Ｎｉ，Ａｇ，Ｉｎ，Ｚｒ，Ｓｎ，Ｎ
ｂ，Ｍｏ，Ｒｕ，Ｒｈ，Ｐｄ，Ｐｂ，Ｔａ，Ｗ，Ｉｒ，
Ｐｔから選ばれる一種以上の元素を含む金属、合金、酸
化物、水酸化物および水和物から選ばれる一層以上から
なる被覆層を有する（１）記載の半導体装置。 （３）、（２）記載の被覆層の上に、シラザン系化合物
を分解して生成するシリカ層を有する（１）記載の半導
体装置。 （４）、（３）記載のシリカ層を有する銅はくが、引っ
張り強さ５０ｋｇ／ｃｍ２以上、伸び１％以上の高強度
高伸び性を有する合成樹脂を主成分とする接着基材層を
介して、積層基材と積層体を構成する（１）記載の半導
体装置。以上（１）から（４）までの、半導体集積回路
素子またはそのパッケージの各電極端子から数えて、半
田などによる接続層、銅はく端子、金属を含む被覆層、
シリカ層、接着基材層および積層基材層の少なくとも六
乃至七層構造からなる半導体装置を発明した。このうち
（１）記載の銅はく、（２）記載の被覆層、（３）記載
のシリカ層が従来の半導体装置の層構成と異なるところ
である。この層構成は、本発明の基本層構成で、従来の
半導体装置の層構成を置き換えていく事により、前記課
題が解決可能となるものである。That is, (1) a plurality of signal terminals, a ground terminal and a power supply terminal of the semiconductor integrated circuit device or a plurality of signal system terminals, the ground terminal and the power supply terminal of the semiconductor integrated circuit device package are bonded wire, solder or In a semiconductor device connected to a terminal on an electronic circuit via an anisotropic conductive adhesive film or the like, the terminal of the electronic circuit is at least copper, copper free of coarse particles made of a copper alloy and their oxides. Semiconductor device (2), B, Al, P, Zn, Ti, V, Cr, M on the surface opposite to the connection surface of the copper foil with the semiconductor integrated circuit described in (1).
n, Fe, Co, Ni, Ag, In, Zr, Sn, N
b, Mo, Ru, Rh, Pd, Pb, Ta, W, Ir,
The semiconductor device according to (1), further comprising a coating layer composed of at least one selected from metals, alloys, oxides, hydroxides, and hydrates containing one or more elements selected from Pt. (3) The semiconductor device according to (1), further comprising a silica layer formed by decomposing a silazane-based compound on the coating layer according to (2). (4) The adhesive base layer mainly composed of a synthetic resin having high strength and high elongation with a tensile strength of 50 kg / cm 2 or more and an elongation of 1% or more. (1) The semiconductor device according to (1), wherein the stacked body and the stacked body are configured through the above. From the above (1) to (4), counting from each electrode terminal of the semiconductor integrated circuit device or its package, a connection layer made of solder or the like, a copper foil terminal, a coating layer containing metal,
Invented a semiconductor device having at least six to seven layers of a silica layer, an adhesive substrate layer and a laminated substrate layer. Among them, the copper foil described in (1), the coating layer described in (2), and the silica layer described in (3) are different from the layer configuration of the conventional semiconductor device. This layer configuration can solve the above problem by replacing the layer configuration of the conventional semiconductor device with the basic layer configuration of the present invention.

【００１６】在来の粗化銅はくの場合は物理的な投錨効
果による接着を主体とするものである。本発明は、半導
体集積回路素子またはそのパッケージの各電極端子と電
子回路の端子の接続層構成に関するものであるが、その
実現には、銅はくと接着基材が良好な接着を形成し、電
子回路の導体系を絶縁系が高度な信頼性を持って支持し
ていることが前提となるので、本発明者は以上に述べる
投錨効果によらない新しい接着原理に基づく方法を発見
し、これによって本発明の半導体装置を完成した。もち
ろん、在来の粗化銅はくの場合でも本発明による方法を
適用できる。銅はくは、電解法あるいは圧延法で造られ
る。電解法では、電極面側の銅はく面は電極の面が転写
され、その面の粗さは電極面によって人為的に造ること
が出来る。通常その値は０．１０〜０．３５μｍで、そ
の反対面である電解液側の面に比べて光沢があるのでシ
ヤイニー面と呼ばれている。電解液側の面はマット面と
呼ばれている。この面は、全体に小さなうねりを有して
光沢はない。その粗さは通常０．３〜１．５μｍであ
る。圧延法による銅はくは、圧延ロールの表面の状態が
転写される。その表面は、電解法による銅はくに比べ平
坦性で光沢があり粗さは０．１０〜０．１５μｍであ
る。使用する銅はくは、接着基材との接着面にＢ，Ａ
ｌ，Ｐ，Ｚｎ，Ｔｉ，Ｖ，Ｃｒ，Ｍｎ，Ｆｅ，Ｃｏ，Ｎ
ｉ，Ａｇ，Ｉｎ，Ｚｒ，Ｓｎ，Ｎｂ，Ｍｏ，Ｒｕ，Ｒ
ｈ，Ｐｄ，Ｐｂ，Ｔａ，Ｗ，Ｉｒ，Ｐｔから選ばれる一
種以上の元素を含む被覆層を造る。この被覆層は、金属
または合金のほか酸化物、水酸化物、および水和物を含
んでもよい。また複数の被覆層であってもよい。合金の
場合は、銅を含むものでもよい。厚さは、０．０１〜５
μｍの範囲がよい。これらの被覆層は、電気めっき、化
学めっき、蒸着、スパッタリング、浸せき処理などによ
り形成できる。とくにＰｄ，Ｎｉ，Ｚｎ，Ｃｒ，Ｍｏ，
Ｃｏなどの金属、合金、酸化物、水酸化物および水和物
が、接着には効果的である。この被覆層は、銅はくの表
面を粗化するものではないので、被覆層の粗さは銅はく
の元の粗さと同程度でよい。また電解銅はくの場合は、
シヤイニー面およびマット面のどちらでも接着基材との
接着面に採用可能である。つぎに、この被覆層の上にシ
ラザン系化合物の分解生成物であるシリカ層を形成す
る。シラザンは、Ｓｉ−Ｎ結合をもつ化合物で、低分子
量のヘキサメチルジシラザンなどのような有機基を含む
ものや、無機ポリシラザンなどがある。シラザンは、大
気中で水分や酸素と反応しアンモニアを放出してシリカ
膜（ＳｉＯ２）を形成する。このシラザンは、前記各種
金属類の被覆層を有する銅はくの表面に塗布される。塗
布方法はシラザンの水溶液に銅はくを浸せきさせたり、
スプレー法やグラビヤコート法が採用される。塗布後は
大気中または蒸気中で加熱してアンモニアを放出させシ
リカ膜とする。アンモニアの放出が不完全でも、接着基
材のほうのエポキシ樹脂などがアンモニアを吸収するの
で問題は殆ど生じない。シラザンの膜厚は、２μｍ以下
でよい。膜厚の下限は、単分子膜、すなはち１０Å程度
で充分な効果が得られる。加熱温度および加熱時間はシ
ラザンの種類や添加される触媒によって異なり実験によ
って決定されるが、通常４５０℃以下常温以上の温度範
囲で行われる。また銅はく被覆層の上にシランカップリ
ング剤を塗布したり、シラザンに予めシランカップリン
グ剤やエポキシ樹脂などの物質を混合しておいても銅は
く被覆層の上にシリカ膜は形成され、良好な接着力が得
られる。In the case of conventional roughened copper foil, adhesion is mainly performed by a physical anchoring effect. The present invention relates to a connection layer configuration of each electrode terminal of the semiconductor integrated circuit element or its package and the terminal of the electronic circuit, for realization, copper foil and an adhesive substrate to form a good adhesion, Since it is premised that the insulating system supports the conductor system of the electronic circuit with high reliability, the present inventor has found a method based on the above-described new bonding principle that does not rely on the anchoring effect, and Thus, the semiconductor device of the present invention was completed. Of course, the method according to the invention can also be applied to the case of conventional roughened copper foil. Copper foil is produced by an electrolytic method or a rolling method. In the electrolysis method, the copper surface on the electrode surface side is transferred to the surface of the electrode, and the roughness of the surface can be artificially made by the electrode surface. Usually, the value is 0.10 to 0.35 μm, which is called a shiny surface because it is glossier than the surface on the electrolyte side which is the opposite surface. The surface on the electrolyte side is called a mat surface. This surface is dull with small undulations throughout. Its roughness is usually 0.3-1.5 μm. The state of the surface of the rolling roll is transferred to the copper foil by the rolling method. Its surface is flat and glossy and has a roughness of 0.10 to 0.15 μm, as compared with copper foil produced by the electrolytic method. Copper foil to be used, B, A on the bonding surface with the bonding substrate
1, P, Zn, Ti, V, Cr, Mn, Fe, Co, N
i, Ag, In, Zr, Sn, Nb, Mo, Ru, R
A coating layer containing one or more elements selected from h, Pd, Pb, Ta, W, Ir, and Pt is produced. The coating may include oxides, hydroxides, and hydrates as well as metals or alloys. Also, a plurality of coating layers may be used. In the case of an alloy, it may contain copper. The thickness is 0.01-5
The range of μm is good. These coating layers can be formed by electroplating, chemical plating, vapor deposition, sputtering, immersion treatment, or the like. In particular, Pd, Ni, Zn, Cr, Mo,
Metals such as Co, alloys, oxides, hydroxides and hydrates are effective for adhesion. Since this coating layer does not roughen the surface of the copper foil, the roughness of the coating layer may be about the same as the original roughness of the copper foil. In the case of electrolytic copper foil,
Either the shiny surface or the mat surface can be used as the bonding surface with the bonding substrate. Next, a silica layer, which is a decomposition product of a silazane compound, is formed on the coating layer. Silazane is a compound having a Si—N bond, and includes a compound containing an organic group such as low-molecular-weight hexamethyldisilazane, and inorganic polysilazane. Silazane reacts with moisture and oxygen in the atmosphere to release ammonia to form a silica film (SiO 2 ). This silazane is applied to the surface of a copper foil having a coating layer of the various metals. The application method is to soak the copper foil in the aqueous solution of silazane,
Spray method and gravure coat method are adopted. After the application, it is heated in the air or in steam to release ammonia to form a silica film. Even if the release of ammonia is incomplete, there is almost no problem because the epoxy resin or the like on the adhesive substrate absorbs the ammonia. The thickness of the silazane may be 2 μm or less. When the lower limit of the film thickness is a monomolecular film, that is, about 10 °, a sufficient effect can be obtained. The heating temperature and heating time vary depending on the type of silazane and the catalyst to be added, and are determined by experiments. Usually, the heating is performed in a temperature range of 450 ° C. or lower and room temperature or higher. Even if a silane coupling agent is applied on the copper foil coating layer, or a material such as a silane coupling agent or epoxy resin is mixed in advance with silazane, a silica film is formed on the copper foil coating layer. And a good adhesive strength is obtained.

【００１７】接着基材は、引っ張り強さ５０ｋｇ／ｃｍ
２以上、好ましくは１００ｋｇ／ｃｍ２以上、さらに好
ましくは２００ｋｇ／ｃｍ２、伸びは１％以上、好まし
くは５％以上、さらに好ましくは１０％以上の高強度高
伸び性の合成樹脂で、例えば、ポリコニチレン、エチレ
ン−α−オレフインコポリマー、ポリビニルアルコール
と脂肪族アルデヒドの誘導体、エチレン−α−オレフイ
ンジエンターポリマー、ＰＰＯなどのエンジニヤリング
プラスチック、ポリブタジエン、ポリイソプレン、各種
ゴム、ＤＣＰＤ、スチレン−ブタジエン共重合体など多
くのジエン系合成樹脂やジアリルフタレート、トリアリ
ルイソシヤネートなどのアリル基を含む化合物、アクリ
レートおよびその誘導体、メタクリレートおよびその誘
導体、ポリエステルあるいはエポキシアクリレート、ウ
レタンアクリレート、ポリエステルアクリレートなどの
各種アクリレートやグリシジルメタクリレート−オレフ
イン共重合体あるいはエポキシ樹脂やフェノール樹脂な
どの熱硬化性樹脂が使用できる。難燃化のためにハロゲ
ン化や難燃剤を添加することも従来の半導体装置の銅張
り積層板と同じように行われる。また、これらの合成樹
脂は、単体で用いることはなく、カップリング剤、硬化
剤、加硫剤、加硫促進剤、安定剤、相溶化剤、変性剤、
塗膜形成剤などと複合して用い、モノマーやプレポリマ
ー、オリゴマー、あるいはポリマーの状態で、目的とす
る半導体装置の要求性能や製造プロセスに合わせて併用
または共重合させて用いることができる。接着基材層の
厚さは５〜１５０μｍで、液状のものを銅はく面に塗布
乾燥して塗膜とするか、フイルム状にして銅はくと積層
基材とを積層接着する際に銅はくの下に挿入したり、あ
るいは銅はくに貼るなどの方法がある。積層基材は従来
から使われている物を使用できる。接着基材と積層基材
が同じ材料であってもよい。この場合も層数は、接着基
材層と積層基材層が合体して一層と数えるものとする。
積層接着の方法は従来から行われている定法により、平
板プレス、ロールあるいはオートクレーブなどを用いて
加熱加圧し積層体を造る。The adhesive substrate has a tensile strength of 50 kg / cm.
2 or more, preferably 100 kg / cm 2 or more, more preferably 200 kg / cm 2 , and an elongation of 1% or more, preferably 5% or more, and more preferably 10% or more of a high-strength high-elongation synthetic resin. Polyethylene, ethylene-α-olefin copolymer, derivatives of polyvinyl alcohol and aliphatic aldehyde, ethylene-α-olefin diene terpolymer, engineering plastics such as PPO, polybutadiene, polyisoprene, various rubbers, DCPD, styrene-butadiene copolymer Many diene-based synthetic resins, compounds containing an allyl group such as diallyl phthalate and triallyl isocyanate, acrylates and derivatives thereof, methacrylates and derivatives thereof, polyesters or epoxy acrylates, urethane acrylates And various acrylates such as polyester acrylate, glycidyl methacrylate-olefin copolymer, and thermosetting resins such as epoxy resin and phenol resin. Halogenation and addition of a flame retardant for flame retardation are performed in the same manner as in the conventional copper-clad laminate of a semiconductor device. In addition, these synthetic resins are not used alone, but include a coupling agent, a curing agent, a vulcanizing agent, a vulcanization accelerator, a stabilizer, a compatibilizer, a denaturant,
It can be used in combination with a film-forming agent or the like, and used in the form of a monomer, prepolymer, oligomer or polymer in combination or copolymerized in accordance with the required performance and manufacturing process of the intended semiconductor device. The thickness of the adhesive base layer is 5 to 150 μm, and when a liquid is applied to the copper foil and dried to form a coating film, or when the copper foil and the laminate substrate are laminated and bonded in a film shape, There is a method of inserting it under the copper foil or attaching it to the copper foil. As the laminated base material, those conventionally used can be used. The adhesive base material and the laminated base material may be the same material. Also in this case, the number of layers is such that the adhesive base material layer and the laminated base material layer are united and counted as one.
The method of laminating and bonding is performed by heating and pressurizing using a flat plate press, a roll, an autoclave, or the like by a conventional method, to produce a laminate.

【００１８】以上に述べた方法を要約すると、半導体集
積回路素子および半導体集積回路素子パッケージの各電
極端子は、ボンデングワイア、半田あるいは異方導電性
接着フイルムなどによって、電子回路側の端子と接続さ
れ半導体装置となる。電子回路側の端子は、銅張り積層
体上の銅はくをエッチング加工して形成されたものであ
る。この銅はくは、電解法または圧延法によって造ら
れ、前記の各種元素を含む層で接着基材との接着面を被
覆してある。また、その被覆面はシランカップリング剤
を塗布してあってもよい。その被覆面の上にシラザン系
化合物の分解生成物であるシリカ層を形成する。シリカ
層はシランカップリング剤やエポキシ樹脂などの合成樹
脂と共存させてもよい。このシリカ層を有する銅はく
を、接着基材層を介するか、または直接、積層基材と積
層接着するものである。To summarize the above-mentioned method, each electrode terminal of the semiconductor integrated circuit device and the semiconductor integrated circuit device package is connected to the terminal on the electronic circuit side by bonding wire, solder or anisotropic conductive adhesive film. Thus, a semiconductor device is obtained. The terminal on the electronic circuit side is formed by etching a copper foil on the copper-clad laminate. This copper foil is produced by an electrolytic method or a rolling method, and has a layer containing the above-mentioned various elements covering a bonding surface with a bonding substrate. Further, the coated surface may be coated with a silane coupling agent. A silica layer, which is a decomposition product of a silazane compound, is formed on the coated surface. The silica layer may be made to coexist with a silane coupling agent or a synthetic resin such as an epoxy resin. The copper foil having the silica layer is laminated and adhered to the laminated substrate through an adhesive substrate layer or directly.

【００１９】[0019]

【作用】本発明の銅、銅合金およびそれらの酸化物から
なる粗化微粒子の存在しない銅はくを用いた電子回路上
の端子は、投錨効果による接着は不可能であるので、本
発明では、銅はくの表面にシラザン系化合物の分解によ
り得られる緻密なシリカ層を設ける新しい接着原理、接
着方法を銅張り積層体に適用して半導体装置を造りだし
た。本発明の接着に係る基本部分は、請求項２の被覆
層、請求項３のシリカ層それに請求項４の接着基材層で
ある。緻密なシリカ層が形成される過程において、銅は
くの表面の吸着水分による水酸基がシリカ層と強固に結
合して接着するものと考えられる。このシリカ層は接着
基材層またはエポキシ樹脂などの場合は積層基材層と直
接、積層接着によって容易に接着される。これらの事に
よって、粗化微粒子の存在しない銅はくでも十分な接着
が得られることになる。銅はくと接着基材層との接着力
は、例えば特公昭−６０−１５６５４に記載されている
ようにシラン系カップリング剤によって増大することが
知られているが、本発明者の追試ではエポキシ樹脂のよ
うな接着剤として優れているとされているものでも、粗
化微粒子の存在しない銅はくでは殆ど効果はなかった。
また接着基材はある程度以上の強度と伸びをもつこと
が、引き剥がしなどの外力による変形に抗するために必
要不可欠であった。従来の接着基剤では、特に伸びが１
％以下と小さく、外力にたいし抵抗する力が小さかっ
た。この銅はくの被覆層、シリカ層、高強度高伸び性接
着基材の三者が、本半導体装置の電子回路側の導体系を
絶縁系が信頼性をもって支持する層構成を成立させてい
る接着システムの一つの役割を担っている。そしてこの
システムの場合、引き剥がし強さは、常態、加熱処理
後、塩酸浸せき処理後ともに、実施例で述べるとおり極
めて高い値が得られる。これは従来の半導体装置に用い
られた銅はり積層体では考えられなかったことである。
本発明の銅はくは、粗化微粒子がないのでエッチング
された後の断面は、図６に示すように矩形となる。従来
の粗化銅はくの場合は、図７に示すようにエッチング加
工によって端面がえぐられた状態になる。これは粗化の
ための銅、銅合金およびそれらの酸化物からなる粗化微
粒子が、接着基材の中に埋没しており、これをエッチン
グ加工によって完全に除去するのに長時間（銅はくのエ
ッチング時間の１．５倍以上）を要するため銅はくが過
剰にエッチングされて起こる現象である。この時、銅は
く表面は保護膜（エッチングレジスト）を有するので変
化はなく、端面だけがエッチングされてえぐられた状態
となる。この結果、従来の粗化銅はくの場合は実質的な
接着面積は、極端な場合には回路幅の約６０％程度とな
り回路幅全体の接着力は、その接着面積に比例して低下
してしまう。粗化微粒子のない銅はくでは、このような
事はない。また合成樹脂基体に埋没している粒子状の物
もないためエッチング時間は約６０％減少できる。さら
に銅はくと基材層の接着面は、銅はくの接着面の被覆層
とシリカ層および基剤層が強固な結合をしているので、
エッチング液が接着面に染み込むことも少なく、従来の
粗化銅はくを使用した時のようにエッチングによる接着
力の低下も殆どない。また塩酸処理あるいは熱処理を受
けても接着力の低下も少ない。それらの結果として厚さ
３５μｍの銅はくで導体幅が５０μｍ、配線間隔５０μ
ｍ、配線ピッチ１００μｍ（ＴＡＢでは７０μｍまで可
能）、厚さ１８μｍの銅はくで導体幅が２０μｍ、配線
間隔２０μｍ、配線ピッチ４０μｍまでの回路加工が可
能となった。このために、半導体集積回路素子および半
導体集積回路素子パッケージの多ピン化、狭ピッチ化の
要求に対し十分応えることが可能となった。特に、電子
回路上の端子からの引出線の微細化が可能になり、端子
周辺に密集した回路の占める面積が縮小し、実装密度の
向上に寄与することとなった。また銅はくがエッチング
加工によって取り除かれた跡の基材層の表面は、従来は
粗化微粒子の埋没した状態が、そのまま微小な穴となっ
て残っていたが、本発明の半導体装置では、このような
微粒子が無いのでエッチング加工によって銅はくが取り
除かれた跡も平坦である。そのために端子の周辺は半田
が着き難く、隣どうしの端子間で半田がブリッジする事
も少なくなる。汚れも着き難くエッチング液やフラッグ
ス残渣の洗浄もしやすい。本発明は、粗化のない銅はく
に特に有効な方法を提供するものであるが、従来の粗化
銅はくについても適用可能なものである。According to the present invention, terminals on an electronic circuit using a copper foil having no roughened fine particles composed of copper, a copper alloy and their oxides cannot be bonded by an anchoring effect. A new bonding principle in which a dense silica layer obtained by decomposing a silazane-based compound is provided on the surface of a copper foil, and a new bonding method were applied to a copper-clad laminate to produce a semiconductor device. The basic parts relating to the adhesion of the present invention are the coating layer of claim 2, the silica layer of claim 3, and the adhesive base layer of claim 4. It is considered that, in the process of forming a dense silica layer, the hydroxyl groups due to the adsorbed moisture on the surface of the copper foil are firmly bonded to the silica layer and adhere. This silica layer is easily adhered directly to the adhesive substrate layer or the laminated substrate layer in the case of an epoxy resin or the like by laminating adhesion. As a result, sufficient adhesion can be obtained even with copper without roughened fine particles. It is known that the adhesive force between the copper foil and the adhesive base material layer is increased by a silane coupling agent as described in, for example, Japanese Patent Publication No. 60-15654. Even an adhesive such as an epoxy resin which is considered to be excellent as an adhesive has little effect on copper foil without roughened fine particles.
In addition, it is indispensable for the adhesive base material to have strength and elongation of a certain degree or more in order to resist deformation due to external force such as peeling. In the case of a conventional adhesive base, the elongation is particularly 1
% Or less, and the force resisting external force was small. The copper foil coating layer, the silica layer, and the high-strength, high-elongation adhesive base material establish a layer configuration in which the insulating system reliably supports the conductor system on the electronic circuit side of the semiconductor device. Has one role in the bonding system. In the case of this system, an extremely high peel strength can be obtained as described in the examples, in the normal state, after the heat treatment, and after the hydrochloric acid immersion treatment. This is not possible with the copper beam laminate used in the conventional semiconductor device.
Since the copper foil of the present invention has no roughened fine particles, the cross section after being etched has a rectangular shape as shown in FIG. In the case of the conventional roughened copper foil, as shown in FIG. 7, the end face is cut off by etching. This is because roughening fine particles composed of copper, copper alloy and their oxides for roughening are buried in the adhesive base material, and it takes a long time to completely remove this by etching (copper is This is a phenomenon that occurs when copper foil is excessively etched because it requires 1.5 times or more the etching time. At this time, there is no change because the copper foil surface has a protective film (etching resist), and only the end face is etched to be extruded. As a result, in the case of the conventional roughened copper foil, the substantial bonding area becomes about 60% of the circuit width in an extreme case, and the bonding strength of the entire circuit width decreases in proportion to the bonding area. Would. This is not the case with copper foil without roughened fine particles. Further, since there is no particulate matter buried in the synthetic resin substrate, the etching time can be reduced by about 60%. Furthermore, since the adhesive surface of the copper foil and the base layer has a strong bond between the coating layer and the silica layer and the base layer of the adhesive surface of the copper foil,
The etchant is less likely to permeate the adhesive surface, and there is almost no decrease in adhesive strength due to etching as in the case of using conventional roughened copper foil. Further, even if it is subjected to a hydrochloric acid treatment or a heat treatment, a decrease in adhesive strength is small. As a result, a copper foil having a thickness of 35 μm, a conductor width of 50 μm, and a wiring interval of 50 μm were used.
m, a wiring pitch of 100 μm (TAB can be up to 70 μm), a copper foil of 18 μm thickness, a conductor width of 20 μm, a wiring interval of 20 μm, and a circuit processing up to a wiring pitch of 40 μm are possible. For this reason, it has become possible to sufficiently meet the demands for increasing the number of pins and reducing the pitch of the semiconductor integrated circuit device and the semiconductor integrated circuit device package. In particular, it is possible to miniaturize the lead wires from the terminals on the electronic circuit, and the area occupied by the circuits densely arranged around the terminals is reduced, contributing to the improvement of the mounting density. Also, the surface of the base material layer where the copper foil was removed by the etching process, the state where the roughened fine particles were buried was left as a minute hole as it was in the past, but in the semiconductor device of the present invention, Since there are no such fine particles, the trace of the copper foil removed by the etching process is flat. Therefore, it is difficult for the solder to reach the periphery of the terminal, and the solder is less likely to be bridged between adjacent terminals. Dirt is hard to reach, and it is easy to clean the etchant and Flags residue. Although the present invention provides a particularly effective method for copper foil without roughening, it is also applicable to conventional roughened copper foil.

【００２０】[0020]

【実施例】図１は本発明の第一の実施例（実施例１）
で、ＱＦＰと称される最も標準的な半導体集積回路素子
パッケージを用いた半導体装置の例である。半導体集積
回路素子（以下半導体チップという）１はエポキシ樹脂
成型品２によってリードフレーム８とともに封止保護さ
れている。電極端子３はリードとも称され成型品２の外
に出ている。プリント配線板４（厚さ１．６ｍｍ）とこ
れを構成する積層基材であるガラス繊維布基材エポキシ
樹脂５（日立化成工業製、品番Ｅ−６７）および粗化微
粒子の存在しない電解銅はく６、半導体の電極端子３は
半田７によってプリント配線板４の端子６と接続されて
半導体装置を形成している。粗化微粒子の存在しない銅
はくは、厚さ１８μｍの電解銅はくで、接着面は０．５
μｍのＮｉ−Ｍｏ−Ｃｏ合金が電気メッキされ、その上
にシラザン系化合物（東燃株式会社製Ｎ−５１０，０．
１ｇをキシレン１００ｇに溶かしたものを使用）を１０
秒間浸せき塗布し１２０℃で３０分間加熱乾燥した後９
５℃８５％ＲＨで２時間処理してある。プリント配線板
４の配線ピッチは１５０μｍで、端子ピッチ３００μ
ｍ、３８４ピンのＱＦＰが接続出来た。粗化銅はくを使
用した従来のプリント配線板でも、配線ピッチ３００μ
ｍ、端子ピッチ５００μｍ、３０４ピンのＱＦＰが接続
出来た。なお銅はくの引き剥がし強さは常態、２．１ｋ
Ｎ／ｍ，１８０℃４８時間加熱後２．０ｋＮ／ｍであっ
た。濃度１８％の塩酸に室温で１時間浸せき後は１．３
ｋＮ／ｍあった。従来のシラザン処理のない粗化銅はく
を使用した銅張り積層体の場合は、それぞれ２．０ｋＮ
／ｍ、１．９ｋＮ／ｍ、１．３ｋＮ／ｍであった。無粗
化の銅はくを使用した銅張り積層体の場合は、それぞれ
１．２ｋＮ／ｍ、０．７ｋＮ／ｍ、０．８ｋＮ／ｍであ
った。この半導体装置は、積層基材層のエポキシ樹脂が
接着基材層を兼ね、したがって図上の５と１５が同じ一
層で、全体で六層構成となっている。実施例１のシラザ
ン系化合物をヘキサメチルジシラザン（東芝シリコーン
株式会社製 ＴＳＬ８８０２ＥＤ）に置き換えた場合に
ついて記載する。（実施例２）このヘキサメチルジシラ
ザンＴＳＬ８８０２ＥＤのキシレン１％溶液に、粗化微
粒子の存在しない銅はくのＮｉ−Ｍｏ−Ｃｏ合金被覆層
を１０分間浸せき塗布し９０℃８５％ＲＨで二十分間乾
燥した。この銅はくを用いて実施例１と同じプリント配
線板を作り、端子ピッチ３００μｍ、３８４ピンのＱＦ
Ｐを半田で接続した。なお銅はくの引き剥がし強さは常
態２．０ｋＮ／ｍ、１８０℃４８時間加熱後１．９ｋＮ
／ｍ、濃度１８％の塩酸に室温で１時間浸せき後１．３
ｋＮ／ｍであった。FIG. 1 shows a first embodiment (Embodiment 1) of the present invention.
This is an example of a semiconductor device using the most standard semiconductor integrated circuit element package called QFP. A semiconductor integrated circuit element (hereinafter, referred to as a semiconductor chip) 1 is sealed and protected by an epoxy resin molded product 2 together with a lead frame 8. The electrode terminal 3 is also called a lead, and extends out of the molded product 2. The printed wiring board 4 (thickness: 1.6 mm) and the glass fiber cloth base epoxy resin 5 (manufactured by Hitachi Chemical Co., Ltd., part number E-67), which is a laminated base material constituting the printed wiring board 4, and electrolytic copper free of coarse particles are 6, the semiconductor electrode terminals 3 are connected to the terminals 6 of the printed wiring board 4 by solder 7 to form a semiconductor device. Copper foil without roughened fine particles, electrolytic copper foil with a thickness of 18 μm, and an adhesive surface of 0.5 μm
μm Ni-Mo-Co alloy is electroplated, and a silazane-based compound (N-510,0.
1 g dissolved in 100 g xylene)
After dipping and applying for 30 seconds and drying by heating at 120 ° C for 30 minutes, 9
Treated at 5 ° C and 85% RH for 2 hours. The wiring pitch of the printed wiring board 4 is 150 μm, and the terminal pitch is 300 μm.
m, 384-pin QFP could be connected. Even with a conventional printed wiring board using roughened copper foil, a wiring pitch of 300μ
m, a terminal pitch of 500 μm, and a 304-pin QFP could be connected. The peel strength of copper foil is normal, 2.1k
N / m and 2.0 kN / m after heating at 180 ° C. for 48 hours. 1.3 hours after immersion in 18% hydrochloric acid at room temperature for 1 hour
kN / m. In the case of a conventional copper-clad laminate using roughened copper foil without a silazane treatment, 2.0 kN
/ M, 1.9 kN / m and 1.3 kN / m. In the case of the copper-clad laminate using unroughened copper foil, the values were 1.2 kN / m, 0.7 kN / m, and 0.8 kN / m, respectively. In this semiconductor device, the epoxy resin of the laminated base material layer also serves as the adhesive base material layer, and therefore, 5 and 15 in the figure are the same layer, and have a total of six layers. The case where the silazane compound of Example 1 is replaced with hexamethyldisilazane (TSL8802ED manufactured by Toshiba Silicone Co., Ltd.) will be described. (Example 2) A 1% xylene solution of hexamethyldisilazane TSL8802ED was coated with a Ni-Mo-Co alloy coating layer of copper foil without roughened fine particles for 10 minutes, applied at 90 ° C and 85% RH for 20 minutes. Dried for minutes. Using this copper foil, the same printed wiring board as in Example 1 was made, and a QF having a terminal pitch of 300 μm and 384 pins was used.
P was connected by solder. The peel strength of the copper foil was 2.0 kN / m in a normal state, and 1.9 kN after heating at 180 ° C. for 48 hours.
/ M, 18% hydrochloric acid at room temperature for 1 hour and then 1.3
kN / m.

【００２１】図１のＱＦＰを用いた半導体装置におい
て、積層基材として紙基材フエノール樹脂を用いた本発
明第三の実施例（実施例３）を記載する。半導体チップ
１はエポキシ樹脂成型品２によってリードフレーム８と
ともに封止保護されているＱＦＰ（電極端子ピッチ６５
０μｍ、２３２ピン）である。電極端子３はリードとも
称され成型品２の外に出ている。プリント配線板４（厚
さ１．６ｍｍ）とこれを構成する積層基材である紙基材
フエノール樹脂５（日立化成工業製、品番４３７Ｆ）お
よび粗化微粒子の存在しない電解銅はく６、その中間に
厚さ５０μｍの接着基材層１５。（日立化成製 ＶＰ−
６３Ｎ…ポリビニルブチラール、フェノール樹脂、メラ
ミン樹脂、エポキシ樹脂系接着剤）半導体の電極端子３
は半田７によってプリント配線板４の端子６と接続され
て半導体装置を形造っている。粗化微粒子の存在しない
銅はくは、厚さ３５μｍの電解銅はくで、接着面は、厚
さ０．３μｍのクロメート処理を行った。（重クロム酸
ナトリウム水和物２．２ｇを純水１リットルに溶解して
調整した処理液中で銅はくの接着面を陽極に向けて電流
密度０．１５Ａ／ｄｍ２で４秒間室温で電気分解し
た。）その上にシラザン系化合物（東燃株式会社製Ｌ１
１０）を１０秒間浸せき塗布し１２０℃で一時間加熱し
た後９５℃、８５％ＲＨで３時間処理した。プリント配
線板４は、配線ピッチ１００μｍの電子回路が加工出来
た。粗化銅はくを使用した従来のプリント配線板では、
配線ピッチ３００μｍの電子回路が実用出来る限界水準
であった。このために、約２０％電子回路の面積を縮減
出来た。なお銅はくの引き剥がし強さは常態２．１ｋＮ
／ｍ、１８０℃４８時間加熱後１．８ｋＮ／ｍであっ
た。濃度１８％の塩酸に室温で１時間浸せき後は１．８
ｋＮ／ｍあった。従来の銅張り積層体の場合は、それぞ
れ２．１ｋＮ／ｍ、１．６ｋＮ／ｍ、１．９ｋＮ／ｍで
あった。この場合は、七層構成の半導体装置となる。実
施例４の接着基材層をビニルエステル樹脂に置き換えた
場合を第五の実施例（実施例５）として記載する。用い
た接着基材は、ポリビニルブチラール（デンカ製、品番
６０００Ｃ）７０重量部、エポキシアクリレート（三菱
レーヨン製、品番ＵＫ６１０５）３０重量部、過酸化物
硬化触媒（日本油脂製、パーブチルＰ）０．５重量部を
溶剤（ＭＥＫ５００重量部とトルエン５００重量部の混
合物）に溶解し、これを実施例４で用いたシラザン系化
合物で処理しシリカ膜を形成させた銅はくの上に、乾燥
後の厚さが３０μｍになるようにロールコーターを用い
て塗布乾燥した。乾燥は、９０℃で十分間行った。この
接着基材付き銅はくと紙基材フエノール樹脂（日立化成
工業製、品番４３７Ｆ）積層基材を積層接着して、厚さ
１．６ｍｍの銅張り積層体を製造した。この銅張り積層
体を用いて実施例４と同様に配線ピッチ１００μｍのプ
リント配線板を得て、これに実施例４で用いたＱＦＰを
半田で接続した。銅はくの引き剥がし強さは、常態１．
９ｋＮ／ｍ、１８０℃４８時間加熱後１．７ｋＮ／ｍ、
濃度１８％の塩酸に常温で１時間浸せき後１．５ｋＮ／
ｍであった。この場合の層構成は、七層の半導体装置で
ある。実施例５のエポキシアクリレートを（実施例６）
ウレタンアクリレート（東亜合成製、品番Ｍ−１１０
０）（実施例７）ポリエステルアクリレート（東亜合成
製、品番Ｍ−６４００）に置き換えて配線ピッチ１００
μｍの電子回路に接続された半導体装置を製作すること
が出来た。銅はくの引き剥がし強さは、常態、１８０℃
４８時間加熱後、濃度１８％の塩酸に常温で１時間浸せ
き後の値が実施例６で２．０ｋＮ／ｍ、１．９ｋＮ／
ｍ、１．４ｋＮ／ｍ 実施例７で２．３ｋＮ／ｍ、１．
５ｋＮ／ｍ、１．１ｋＮ／ｍであった。A third embodiment (Embodiment 3) of the present invention using a paper base phenol resin as a laminated base in a semiconductor device using the QFP of FIG. 1 will be described. The semiconductor chip 1 is sealed and protected together with the lead frame 8 by the epoxy resin molded product 2 (QFP (electrode terminal pitch 65)).
0 μm, 232 pins). The electrode terminal 3 is also called a lead, and extends out of the molded product 2. Printed wiring board 4 (thickness 1.6 mm), paper base phenolic resin 5 (product number 437F, manufactured by Hitachi Chemical Co., Ltd.) and laminating base material constituting the same, and electrolytic copper foil 6 free of coarsened fine particles. An adhesive base layer 15 having a thickness of 50 μm in the middle. (Hitachi Chemical VP-
63N: polyvinyl butyral, phenol resin, melamine resin, epoxy resin adhesive) Semiconductor electrode terminal 3
Are connected to the terminals 6 of the printed wiring board 4 by solder 7 to form a semiconductor device. Copper foil without roughened fine particles or electrolytic copper foil with a thickness of 35 μm was subjected to chromate treatment on the bonding surface with a thickness of 0.3 μm. (In a treatment solution prepared by dissolving 2.2 g of sodium bichromate hydrate in 1 liter of pure water, the copper foil is bonded at the current density of 0.15 A / dm 2 at room temperature for 4 seconds with the bonding surface of the copper foil facing the anode. Then, a silazane compound (L1 manufactured by Tonen Co., Ltd.)
10) was applied by dipping for 10 seconds, heated at 120 ° C. for 1 hour, and then treated at 95 ° C. and 85% RH for 3 hours. The printed wiring board 4 was able to process an electronic circuit having a wiring pitch of 100 μm. In a conventional printed wiring board using roughened copper foil,
The electronic circuit having a wiring pitch of 300 μm was at a practically usable limit. For this reason, the area of the electronic circuit could be reduced by about 20%. The peel strength of copper foil is 2.1kN under normal conditions
/ M, and 1.8 kN / m after heating at 180 ° C for 48 hours. 1.8 hours after immersion in 18% hydrochloric acid at room temperature for 1 hour
kN / m. In the case of the conventional copper-clad laminate, they were 2.1 kN / m, 1.6 kN / m, and 1.9 kN / m, respectively. In this case, the semiconductor device has a seven-layer structure. A case in which the adhesive base material layer in Example 4 is replaced with a vinyl ester resin will be described as a fifth example (Example 5). The adhesive base material used was 70 parts by weight of polyvinyl butyral (manufactured by Denka, part number 6000C), 30 parts by weight of epoxy acrylate (manufactured by Mitsubishi Rayon, part number UK6105), 0.5 part of a peroxide curing catalyst (manufactured by NOF Corporation, Perbutyl P) 0.5 Parts by weight were dissolved in a solvent (a mixture of 500 parts by weight of MEK and 500 parts by weight of toluene), and this was treated with the silazane compound used in Example 4 to form a silica film on a copper foil, and then dried. Coating and drying were performed using a roll coater so that the thickness became 30 μm. Drying was performed at 90 ° C. for a sufficient time. This copper foil with an adhesive substrate and a paper substrate phenol resin (manufactured by Hitachi Chemical Co., Ltd., product number 437F) were laminated and bonded to produce a copper-clad laminate having a thickness of 1.6 mm. Using this copper-clad laminate, a printed wiring board having a wiring pitch of 100 μm was obtained in the same manner as in Example 4, to which the QFP used in Example 4 was connected by soldering. The peeling strength of copper foil is 1.
9 kN / m, after heating at 180 ° C. for 48 hours, 1.7 kN / m,
1.5kN / after immersing in 18% hydrochloric acid at room temperature for 1 hour
m. The layer configuration in this case is a seven-layer semiconductor device. The epoxy acrylate of Example 5 was used (Example 6)
Urethane acrylate (manufactured by Toagosei, part number M-110
0) (Example 7) Wiring pitch 100 instead of polyester acrylate (manufactured by Toagosei Co., Ltd., product number M-6400)
A semiconductor device connected to a μm electronic circuit could be manufactured. Peel strength of copper foil is normal, 180 ℃
After heating for 48 hours and immersing in 18% hydrochloric acid at room temperature for 1 hour, the values in Example 6 were 2.0 kN / m and 1.9 kN / m.
m, 1.4 kN / m In Example 7, 2.3 kN / m, 1.
The values were 5 kN / m and 1.1 kN / m.

【００２２】図２は本発明の第八の実施例（実施例８）
で、ＢＧＡと称される半導体の接続方式における例を示
す。半導体チップ１は、金ボンデングワイア９によりプ
リント配線板４ａ（厚さ０．６ｍｍ）上の端子６と接続
されている。この状態でエポキシ樹脂２によって封止保
護されている。半導体チップ１は、裏面に放熱板１０を
置いて発熱を放散するようになっている。プリント配線
板４ａは、積層基材としてガラス繊維布基材ＢＴレジン
（三菱化学工業製、品番…ＣＣＬ−Ｈ８１０を積層基材
とした）を用い、半導体チップ１に接続する端子６のほ
かに、外部との接続用の端子１１を有し、端子６と１１
は、目的とする用途に適合するように設計された回路で
つながっている。この半導体装置を搭載した電子回路
は、さらにもう一つの電子回路と接続される。その電子
回路は、プリント配線板４ｂの上に形成された端子１１
の上で半田ボール１２によって接続されている。本発明
は、端子６がシラザン系化合物を塗布、加熱吸湿させて
シリカ膜を形成させた粗化微粒子の存在しない銅はくで
あることを要件とするものである。銅はくは厚さ１８μ
ｍで、その接着基材層面は電気メッキにより厚さ０．２
μｍのＰｄで被覆され、その上にシラザン系化合物（東
燃株式会社製Ｎ５１０）を塗布、大気中４５０℃で１時
間加熱し０．０１μｍのシリカ膜を形成させてある。接
着基材はメタクリル酸グリシジルエチレン共重合体（日
本石油化学製、レクスパールＲＡ３０５０）１００重量
部、過酸化物硬化触媒（日本油脂製、バーブチルＰ）２
重量部を１２０℃に加熱したニーダで均一に混合した
後、１２０℃のロールで圧延して厚さ５０μｍのフイル
ムとし、これを用いた。プリント配線板４ａの配線ピッ
チは、１５０μｍ、３層回路で６２５ピンのＢＧＡに対
応可能であった。従来の粗化銅はくを用いたプリント配
線板では、配線ピッチ３００μｍ、６層回路の配線板が
必要であった。ここで用いた銅張り積層体の銅はくの引
き剥がし強さは、常態、塩酸浸せき後および加熱後それ
ぞれ２．０ｋＮ／ｍ、１．７ｋＮ／ｍ、１．５ｋＮ／ｍ
であった。従来の銅張り積層体の場合は、それぞれ０．
５ｋＮ／ｍ、０．２ｋＮ／ｍ、０．２ｋＮ／ｍであっ
た。この場合の半導体装置の層構成は七層となってい
る。図３は、図２の本発明に係る部分を図示したもので
ある。半導体チップ１上の電極端子３は、金ボンデング
ワイア９によってプリント配線板４上の端子６と超音波
接合法により接続されている。１３は半導体チップ１を
固定するダイボンデングである。端子６は、シラザン系
化合物の加熱分解により形成させたシリカ膜を有する粗
化微粒子の存在しない電解銅はくである。この半導体装
置全体をエポキシ樹脂２で保護封止する。図３は、半導
体チップを図２と上下逆に示してある。半導体側の端子
３、ボンデングワイア９、電子回路（プリント配線板）
上の端子６（銅はく、Ｐｄ膜、シリカ膜層）接着基材層
および積層基材層の七層構造となっている。放熱板１０
は省略してある。FIG. 2 shows an eighth embodiment of the present invention (Eighth Embodiment).
Now, an example of a semiconductor connection method called BGA will be described. The semiconductor chip 1 is connected to a terminal 6 on a printed wiring board 4a (thickness 0.6 mm) by a gold bonding wire 9. In this state, it is sealed and protected by the epoxy resin 2. The semiconductor chip 1 is configured to dissipate heat by placing a heat sink 10 on the back surface. The printed wiring board 4a uses a glass fiber cloth base material BT resin (manufactured by Mitsubishi Chemical Corporation, product number: CCL-H810 was used as the base material) as a laminated base material, and in addition to the terminals 6 connected to the semiconductor chip 1, It has a terminal 11 for connection to the outside, and terminals 6 and 11
Are connected by circuits designed to suit the intended use. The electronic circuit on which the semiconductor device is mounted is connected to yet another electronic circuit. The electronic circuit includes terminals 11 formed on the printed wiring board 4b.
Are connected by a solder ball 12. The present invention requires that the terminal 6 be a copper foil which is free of roughened fine particles in which a silazane-based compound is applied and heated and absorbed to form a silica film. Copper foil thickness 18μ
m, the surface of the adhesive base material layer has a thickness of 0.2 by electroplating.
A silazane-based compound (N510 manufactured by Tonen Co., Ltd.) is applied thereon, and heated at 450 ° C. for 1 hour in the air to form a 0.01 μm silica film. Adhesive base material: 100 parts by weight of glycidyl ethylene methacrylate copolymer (manufactured by Nippon Petrochemical Co., Ltd., Lexpearl RA3050), peroxide curing catalyst (manufactured by NOF CORPORATION, Burbutyl P) 2
A part by weight was uniformly mixed with a kneader heated to 120 ° C., and then rolled with a roll at 120 ° C. to obtain a 50 μm thick film, which was used. The wiring pitch of the printed wiring board 4a was 150 μm, and a three-layer circuit could support 625-pin BGA. A conventional printed wiring board using roughened copper foil requires a wiring board with a wiring pitch of 300 μm and a six-layer circuit. The peel strength of the copper foil of the copper-clad laminate used here was 2.0 kN / m, 1.7 kN / m, 1.5 kN / m after normal temperature, after soaking with hydrochloric acid, and after heating.
Met. In the case of a conventional copper-clad laminate, each of them is 0.1.
They were 5 kN / m, 0.2 kN / m and 0.2 kN / m. In this case, the semiconductor device has seven layers. FIG. 3 illustrates a portion according to the present invention of FIG. The electrode terminals 3 on the semiconductor chip 1 are connected to the terminals 6 on the printed wiring board 4 by gold bonding wires 9 by an ultrasonic bonding method. Reference numeral 13 denotes a die bonding for fixing the semiconductor chip 1. The terminal 6 is an electrolytic copper foil having a silica film formed by thermal decomposition of a silazane-based compound and free of roughened fine particles. The entire semiconductor device is protected and sealed with the epoxy resin 2. FIG. 3 shows the semiconductor chip upside down from FIG. Terminal 3 on the semiconductor side, bonding wire 9, electronic circuit (printed wiring board)
The upper terminal 6 (copper foil, Pd film, silica film layer) has a seven-layer structure of an adhesive substrate layer and a laminated substrate layer. Heat sink 10
Is omitted.

【００２３】図４は本発明の第九の実施例（実施例９）
で、ＴＡＢ方式の場合を示す。ＴＡＢは、フレキシブル
プリント配線板によって半導体チップの電極端子と外部
のプリント配線板の端子を接続する機能を有するもので
ある。１４がＴＡＢ、１が半導体チップ、４がプリント
配線板、１１がプリント配線板上の端子である。ＴＡＢ
１４の端子６は半導体チップ１およびプリント配線板の
端子１１と半田バンプ１２によって接続されるもので、
厚さ３５μｍの粗化微粒子の存在しない平坦な圧延銅は
くで、接着面に厚さ０．５μｍのクロメート処理がなさ
れ（重クロム酸ナトリウム水和物２．２ｇを純水１リッ
トルに溶解し、この溶液を用い銅はくのＣｒ被覆をしよ
うとする面を陽極に向けて電流密度０．１５Ａ／ｄｍ２
で５秒間処理）その後、０．２％のシラザン系化合物
（東燃株式会社製 Ｌ１１０）のキシレン溶液に１０秒
間浸せきし１２０℃で一時間加熱後９５℃８５％ＲＨで
三時間処理し厚さ０．０２μｍのシリカ膜を形成したも
のを用いた。用いられた積層基材は、厚さ７５μｍのポ
リイミドフイルム（宇部興産製、商品名ユーピレックス
−Ｓ）を用いた。接着剤は、エチレンブテンジエンター
ポリマ（三井石油化学製：品番Ｋ−９７２０）３２重量
部に含水シリカ（日本シリカ工業製、品番ＶＮ−３）８
重量部、トリアリルイソシアヌレート（日本化成製、Ｔ
ＡＩＣ）０．３２重量部、過酸化物（日本油脂製、パー
ブチルＰ）０．３２重量部を均一に混練したのち１２０
℃でロール圧延して厚さ５０μｍのフイルムとしたもの
を用いた。端子の幅は２０μｍ配線ピッチは５０μｍと
なっている。従来の粗化銅はくを用いたプリント配線板
では１００μｍピッチのものが限界であった。端子１１
も端子６と同じくシリカ膜を有する銅はくを使用でき
る。ここで用いた銅張り積層体の銅はくの引き剥がし強
さは、常態１．７ｋＮ／ｍ、塩酸浸せき後１．６ｋＮ／
ｍ、加熱後１．３ｋＮ／ｍであった。従来の銅張り積層
体では、それぞれ１．２ｋＮ／ｍ、１．１ｋＮ／ｍ、
０．１ｋＮ／ｍであった。FIG. 4 shows a ninth embodiment of the present invention (ninth embodiment).
Shows the case of the TAB method. TAB has a function of connecting an electrode terminal of a semiconductor chip to a terminal of an external printed wiring board by a flexible printed wiring board. 14 is a TAB, 1 is a semiconductor chip, 4 is a printed wiring board, and 11 is a terminal on the printed wiring board. TAB
14 terminals 6 are connected to the semiconductor chip 1 and the terminals 11 of the printed wiring board by the solder bumps 12,
35 μm thick flat rolled copper foil without roughened fine particles, chromate treatment of 0.5 μm thickness on the bonding surface (2.2 g of sodium dichromate hydrate dissolved in 1 liter of pure water With this solution, the surface to be coated with Cr of the copper foil is directed to the anode, and the current density is 0.15 A / dm 2.
Immersion for 10 seconds in a xylene solution of a 0.2% silazane-based compound (L110 manufactured by Tonen Co., Ltd.), heated at 120 ° C. for 1 hour, and then treated at 95 ° C. and 85% RH for 3 hours to obtain a thickness of 0%. One having a 0.02 μm silica film formed thereon was used. As the laminated base material used, a 75 μm-thick polyimide film (trade name: Upilex-S, manufactured by Ube Industries, Ltd.) was used. The adhesive was prepared by mixing 32 parts by weight of ethylene butene diene terpolymer (manufactured by Mitsui Petrochemical: product number K-9720) with hydrous silica (product number VN-3 manufactured by Nippon Silica Kogyo).
Parts by weight, triallyl isocyanurate (Nippon Kasei, T
(AIC) 0.32 parts by weight and 0.32 parts by weight of peroxide (manufactured by NOF CORPORATION, Perbutyl P) are uniformly kneaded, and then 120
A film rolled at 50 ° C. into a film having a thickness of 50 μm was used. The terminal width is 20 μm and the wiring pitch is 50 μm. A conventional printed wiring board using roughened copper foil has a limit of 100 μm pitch. Terminal 11
Copper foil having a silica film, like the terminal 6, can also be used. The peel strength of the copper foil of the copper-clad laminate used here was 1.7 kN / m in a normal state and 1.6 kN / m after immersion in hydrochloric acid.
m and 1.3 kN / m after heating. In a conventional copper-clad laminate, 1.2 kN / m, 1.1 kN / m,
It was 0.1 kN / m.

【００２４】図５は本発明の第十の実施例（実施例１
０）で、フリップチップ方式の場合を示す。半導体チッ
プ１の各電極端子３が半田バンプ１２により電子回路で
あるプリント配線板４の上に形成された電子回路の端子
６（実施例１０と同じ処理によりシリカ膜を有する銅は
くからなる端子）と接続された状態を示したものであ
る。プリント配線板４は、厚さ１８μｍの上記シリカ膜
を有する電解銅はく（端子の幅５０μｍ、配線ピッチ１
００μｍ）厚さ０．６ｍｍのガラス繊維布基材ＢＴレジ
ンを積層基材（接着基材および積層基材は実施例８と同
じ）に用いたものである。従来の粗化銅はくを用いたも
のは配線ピッチ３００μｍが限界であった。FIG. 5 shows a tenth embodiment (Embodiment 1) of the present invention.
0) shows the case of the flip chip method. Each electrode terminal 3 of the semiconductor chip 1 is formed by a solder bump 12 on a printed wiring board 4 which is an electronic circuit. An electronic circuit terminal 6 (a terminal made of a copper foil having a silica film by the same processing as in the tenth embodiment) ) Is shown. The printed wiring board 4 is made of electrolytic copper foil having a silica film having a thickness of 18 μm (terminal width 50 μm, wiring pitch 1).
(00 μm) A glass fiber cloth base material BT resin having a thickness of 0.6 mm was used for a laminated base material (the adhesive base material and the laminated base material were the same as in Example 8). In the case of using conventional roughened copper foil, the wiring pitch was limited to 300 μm.

【００２５】[0025]

【発明の効果】本発明による半導体装置は、電子回路上
の端子が従来より微細加工可能となるので、半導体集積
回路素子の高集積化、狭ピッチ化に対応でき特に端子周
辺の密集した引出線の微細化により、実装密度の向上に
大きく寄与する。多層回路プリント配線板の層数も低減
でき、電子装置全体の小型化、低価格化に貢献できる。
無粗化銅はくの場合は、製造工程が短縮されるため、銅
はくのコストが約３０％安くなるほか、接着基材層に埋
没した銅、銅合金およびそれらの酸化物からなる微粒子
を取り除く必要がないのでエッチング時間も約６０％短
縮される。また銅はくの回路加工後の形状が、ほぼ矩形
状となり超高周波電気信号の反射、エネルギー損失、ノ
イズ発生が少なくなり伝送信頼性が向上する。エッチン
グ後の接着基材の表面も平坦になって、半田による実装
接続において隣あう端子間で起こる半田のブリッジが少
なくなる。また塵などの付着も軽減されるほか、エッチ
ング液、フラックス残渣などの薬液の洗浄も容易にな
る。さらに、従来、銅はく表面に粗化微粒子を着けにく
いため、余り使われなかった圧延銅はくも電解銅はく並
みに使用できるようになり、高強度銅はくが使用しやす
くなる。電子部品には、半導体集積回路の他に抵抗体、
コンデンサー、コイルなどいろいろあるが、半導体集積
回路素子に比べて端子の数が少なく配線ピッチも５００
μｍ以上あればよい。本発明は、半導体集積回路の高集
積化ならびに端子の狭ピッチ化、多ピン化に特に効果が
あり、今後開発される超多ピンの半導体集積回路および
半導体集積回路パッケージに十分対応できる半導体装置
を提供可能とするもので、エッチング加工によって製作
されるサブトラクト法プリント配線板を用いた半導体装
置としては、高い接着性能を持ち、微細な回路加工が可
能となり、そのコストも従来と比べて低減が可能とな
り、かつ従来の製造設備をそのまま活用できる究極の半
導体装置である。In the semiconductor device according to the present invention, the terminals on the electronic circuit can be processed finer than before, so that it is possible to cope with the high integration and narrow pitch of the semiconductor integrated circuit element, and particularly, the dense lead lines around the terminals. The miniaturization greatly contributes to the improvement of the mounting density. The number of layers of the multilayer circuit printed wiring board can be reduced, which contributes to the miniaturization and cost reduction of the entire electronic device.
In the case of non-roughened copper foil, the manufacturing process is shortened, so that the cost of copper foil is reduced by about 30%, and fine particles composed of copper, copper alloy and their oxides buried in the adhesive base material layer. Since there is no need to remove, etching time is also reduced by about 60%. In addition, the shape of the copper foil after the circuit processing is substantially rectangular, so that reflection of ultra-high frequency electric signals, energy loss and noise generation are reduced, and transmission reliability is improved. The surface of the adhesive base material after the etching is also flattened, and solder bridging occurring between adjacent terminals in mounting connection by soldering is reduced. In addition, the adhesion of dust and the like is reduced, and the cleaning of a chemical solution such as an etching solution and a flux residue becomes easy. Further, conventionally, roughened fine particles are hardly attached to the surface of copper foil. Therefore, rolled copper foil, which has not been used much, can be used like electrolytic copper foil, and high-strength copper foil becomes easy to use. Electronic components include resistors,
There are various types such as capacitors and coils, but the number of terminals is smaller and the wiring pitch is 500
It is sufficient if it is at least μm. The present invention is particularly effective in increasing the integration density of semiconductor integrated circuits, narrowing the pitch of terminals, and increasing the number of pins, and provides a semiconductor device that can sufficiently cope with ultra-high pin count semiconductor integrated circuits and semiconductor integrated circuit packages to be developed in the future. As a semiconductor device using a subtractive printed wiring board manufactured by etching, it has high adhesion performance and enables fine circuit processing, and its cost can be reduced compared to conventional It is the ultimate semiconductor device that can utilize conventional manufacturing equipment as it is.

【図面の簡単な説明】[Brief description of the drawings]

【図１】 ＱＦＰのリードフレームとシリカ膜を有す
る銅はくを用いた電子回路上の端子を接続した半導体装
置説明図。FIG. 1 is an explanatory view of a semiconductor device in which terminals on an electronic circuit using a copper foil having a lead frame of a QFP and a silica film are connected.

【図２】 ＢＧＡ方式における半導体装置の接続構造
説明図。FIG. 2 is a diagram illustrating a connection structure of a semiconductor device in a BGA system.

【図３】 図２における接続部分の説明図。FIG. 3 is an explanatory diagram of a connection portion in FIG. 2;

【図４】 ＴＡＢ方式における半導体装置の接続構造
説明図。FIG. 4 is a diagram illustrating a connection structure of a semiconductor device in a TAB method.

【図５】 フリップチップ方式における半導体装置の
接続構造説明図FIG. 5 is an explanatory diagram of a connection structure of a semiconductor device in a flip chip system.

【図６】 本発明の電子回路上の端子の断面形状とそ
の周囲の説明図。FIG. 6 is an explanatory diagram of a cross-sectional shape of a terminal on an electronic circuit according to the present invention and its periphery.

【図７】 従来の電子回路上の端子の断面形状とその
周囲の説明図。FIG. 7 is an explanatory diagram of a cross-sectional shape of a terminal on a conventional electronic circuit and its surroundings.

【符号の説明】[Explanation of symbols]

１…半導体チップ ２…エポキシ樹脂成型品 ３…半導体側の電極端子 ４…プリント配線板、複数の場合は４ａ，４ｂと区別し
た。 ５…積層基材 ６…シラザン系化合物を塗布、加熱分解してシリカ膜を
形成させた銅はくで出来た電子回路上の端子 ７…半田 ８…リードフレーム ９…ボンデングワイア １０…放熱板 １１…プリント配線板上の外部接続用端子 １２…半田ボールまたは半田バンプ １３…ダイボンデング １４…ＴＡＢ １５…接着基材層 １６…保護膜（エッチングレジスト） １７…粗化銅はくで出来た電子回路上の端子DESCRIPTION OF SYMBOLS 1 ... Semiconductor chip 2 ... Epoxy resin molded product 3 ... Semiconductor-side electrode terminal 4 ... Printed wiring board. 5 Laminated base material 6 Terminal on electronic circuit made of copper foil coated with a silazane compound and thermally decomposed to form a silica film 7 Solder 8 Lead frame 9 Bonding wire 10 Heat sink DESCRIPTION OF SYMBOLS 11 ... External connection terminal on printed wiring board 12 ... Solder ball or solder bump 13 ... Die bonding 14 ... TAB 15 ... Adhesive base material layer 16 ... Protective film (etching resist) 17 ... Electronic circuit made of roughened copper foil Upper terminal

Claims (5)

【特許請求の範囲】[Claims] 【請求項１】半導体集積回路素子の複数の信号系端子、
接地端子および電源端子、または半導体集積回路素子パ
ッケージの複数の信号系端子、接地端子および電源端子
が、ボンデングワイア、半田または異方導電性接着フイ
ルムなどを介して、電子回路上の端子と接続してなる半
導体装置において、電子回路の端子が少なくとも銅、銅
合金およびそれらの酸化物からなる銅はくから形成され
る半導体装置。A plurality of signal terminals of a semiconductor integrated circuit device;
Ground terminals and power terminals, or multiple signal terminals, ground terminals, and power terminals of a semiconductor integrated circuit device package are connected to terminals on an electronic circuit via bonding wires, solder, or anisotropic conductive adhesive films. A semiconductor device according to claim 1, wherein the terminals of the electronic circuit are formed of copper foil composed of at least copper, a copper alloy, and an oxide thereof. 【請求項２】請求項１記載の銅はくが、半導体集積回路
との接続面の反対面にＢ，Ａｌ，Ｐ，Ｚｎ，Ｔｉ，Ｖ，
Ｃｒ，Ｍｎ，Ｆｅ，Ｃｏ，Ｎｉ，Ａｇ，Ｉｎ，Ｚｒ，Ｓ
ｎ，Ｎｂ，Ｍｏ，Ｒｕ，Ｒｈ，Ｐｄ，Ｐｂ，Ｔａ，Ｗ，
Ｉｒ，Ｐｔから選ばれる一種以上の元素を含む金属、合
金、酸化物、水酸化物および水和物から選ばれる一層以
上からなる被覆層を有する請求項１記載の半導体装置。2. The copper foil according to claim 1, wherein B, Al, P, Zn, Ti, V,
Cr, Mn, Fe, Co, Ni, Ag, In, Zr, S
n, Nb, Mo, Ru, Rh, Pd, Pb, Ta, W,
2. The semiconductor device according to claim 1, further comprising a coating layer comprising at least one selected from metals, alloys, oxides, hydroxides and hydrates containing one or more elements selected from Ir and Pt. 【請求項３】請求項２記載の銅はくが、被覆層の上に、
シラザン系化合物を分解して生成したシリカ膜の層を有
する請求項１記載の半導体装置。3. The copper foil according to claim 2, further comprising:
2. The semiconductor device according to claim 1, further comprising a silica film layer formed by decomposing a silazane-based compound. 【請求項４】請求項３記載のシリカ層を有する銅はく
が、引っ張り強さ５０ｋｇ／ｃｍ２以上、伸び１％以上
の高強度高伸び性を有する合成樹脂を主成分とする接着
基材層を介して、積層基材と積層体を構成する少なくと
も七層以上の接続層構成を持った請求項１記載の半導体
装置。4. A copper foil having a silica layer according to claim 3, wherein the adhesive base material is a synthetic resin having high strength and high elongation with a tensile strength of 50 kg / cm 2 or more and an elongation of 1% or more. 2. The semiconductor device according to claim 1, wherein the semiconductor device has at least seven or more connection layers constituting a laminate with the laminated base material via the layers. 【請求項５】請求項３記載のシリカ層を有する銅はく
が、積層基材と積層体を構成する少なくとも六層以上の
接続層構成を持った請求項１記載の半導体装置。5. The semiconductor device according to claim 1, wherein the copper foil having a silica layer according to claim 3 has at least six or more connection layer structures constituting a laminate and a laminate.
JP9281038A 1997-09-05 1997-09-05 Semiconductor device Pending JPH1187401A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9281038A JPH1187401A (en) 1997-09-05 1997-09-05 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9281038A JPH1187401A (en) 1997-09-05 1997-09-05 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH1187401A true JPH1187401A (en) 1999-03-30

Family

ID=17633439

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9281038A Pending JPH1187401A (en) 1997-09-05 1997-09-05 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH1187401A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6461745B2 (en) * 2000-04-25 2002-10-08 Nippon Denkai, Ltd. Copper foil for tape carrier and tab carrier tape and tab tape carrier using the copper foil
JP2006316300A (en) * 2005-05-11 2006-11-24 Hitachi Chem Co Ltd Copper surface treatment method and copper surface
CN110709966A (en) * 2017-01-19 2020-01-17 德克萨斯仪器股份有限公司 Etching platinum-containing films using protective caps

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6461745B2 (en) * 2000-04-25 2002-10-08 Nippon Denkai, Ltd. Copper foil for tape carrier and tab carrier tape and tab tape carrier using the copper foil
KR100429439B1 (en) * 2000-04-25 2004-05-03 닛폰 덴카이 가부시키가이샤 Tab carrier tape and tab tape carrier using copper foil
JP2006316300A (en) * 2005-05-11 2006-11-24 Hitachi Chem Co Ltd Copper surface treatment method and copper surface
CN110709966A (en) * 2017-01-19 2020-01-17 德克萨斯仪器股份有限公司 Etching platinum-containing films using protective caps
CN110709966B (en) * 2017-01-19 2023-09-19 德克萨斯仪器股份有限公司 Etching platinum-containing films using a protective cap layer

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