JPH118260A - Method for manufacturing resin-encapsulated semiconductor device - Google Patents
Method for manufacturing resin-encapsulated semiconductor deviceInfo
- Publication number
- JPH118260A JPH118260A JP9176585A JP17658597A JPH118260A JP H118260 A JPH118260 A JP H118260A JP 9176585 A JP9176585 A JP 9176585A JP 17658597 A JP17658597 A JP 17658597A JP H118260 A JPH118260 A JP H118260A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- resin
- conductive substrate
- sealing
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H10W90/756—
Landscapes
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Dicing (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
(57)【要約】
【課題】 導電性基板上にめっき法により回路部を形成
し、半導体素子を搭載、樹脂封止後に、半導体装置を導
電性基板から分離して得る、プラスチックBGA等の作
製において、複数に面付けされた状態(1連の状態)で
工程進行ができる製造方法を提供する。
【解決手段】 一つの半導体装置用の単位回路部を、面
付けされた状態に、複数個、導電性基板の上に作製し、
該導電性基板の各回路部毎に半導体素子を搭載し、必要
な電気接続を行った後、順次、各半導体装置毎の樹脂封
止とともに、半導体装置の封止用樹脂部と少なくとも一
部において一体的に連結する封止用樹脂からなる連結部
を設けて、隣接する半導体装置間を連結させ、処理する
複数個の半導体装置全てを封止用樹脂にて連結させた状
態に樹脂封止する樹脂封止工程と、処理する複数個の半
導体装置全てを封止用樹脂にて連結させた状態で、導電
性基板より剥離する剥離工程と、剥離後に、各半導体装
置を互いに分離させるための、封止用樹脂からなる連結
部を除去するトリミング工程とを有する。
PROBLEM TO BE SOLVED: To produce a plastic BGA or the like by forming a circuit portion on a conductive substrate by a plating method, mounting a semiconductor element, sealing the resin, and separating the semiconductor device from the conductive substrate. In the above, there is provided a manufacturing method capable of performing the process in a state where a plurality of impositions are performed (a series of states). SOLUTION: A plurality of unit circuit portions for one semiconductor device are formed on a conductive substrate in an imposed state,
After mounting a semiconductor element for each circuit portion of the conductive substrate and making necessary electrical connections, sequentially with resin sealing for each semiconductor device, at least a portion with a sealing resin portion of the semiconductor device. A connecting portion made of a sealing resin integrally connected is provided to connect adjacent semiconductor devices, and the plurality of semiconductor devices to be processed are all resin-sealed in a state of being connected by the sealing resin. A resin sealing step, a peeling step of peeling off from the conductive substrate in a state where all of the plurality of semiconductor devices to be processed are connected by the sealing resin, and after peeling, for separating each semiconductor device from each other, And a trimming step of removing a connecting portion made of a sealing resin.
Description
【0001】[0001]
【発明の属する技術分野】本発明は,めっきにより薄く
形成された回路部を有する、面実装型の樹脂封止型半導
体装置用の回路部材を用いた半導体装置の製造方法に関
するもので、特に、PBGA(Plastic Bal
l Grid Array)タイプの半導体装置用の回
路部材を用いた半導体装置の製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device using a circuit member for a surface-mount type resin-encapsulated semiconductor device having a circuit portion formed thin by plating. PBGA (Plastic Bal)
The present invention relates to a method of manufacturing a semiconductor device using a circuit member for a (Grid Array) type semiconductor device.
【0002】[0002]
【従来の技術】近年、半導体装置は、電子機器の高性能
化と軽薄短小化の傾向(時流)からLSIのASICに
代表されるように、ますます高集積化、高機能化が図ら
れており、これに伴い、半導体装置には、ますます多端
子(ピン)化が求められるようになってきた。多端子
(ピン)IC、特にゲートアレイやスタンダードセルに
代表されるASICあるいは、マイコン、DSP(Di
gital Signal Processor)等の
半導体装置化には、リードフレームを用いたQFP(Q
uadFlat Package)等の表面実装型パッ
ケージが用いられており、QFPでは300ピンクラス
のものまでが実用化に至ってきている。QFPは、図4
(b)に示す単層リードフレーム410を用いたもの
で、図4(a)にその断面図を示すように、ダイパッド
411上に半導体素子420を搭載し、銀めっき、金め
っき等の処理がされたインナーリード先端部412Aと
半導体素子420の端子(電極パッド)421とをワイ
ヤ430にて結線した後に、樹脂440で封止し、ダム
バー部をカットし、アウターリード413部をガルウイ
ング状に折り曲げて作製されている。このようなQFP
は、パッケージの4方向へ外部回路と電気的に接続する
ためのアウターリードを設けた構造となり、多端子(ピ
ン)化に対応できるものとして開発されてきた。ここで
用いられる単層リードフレーム410は、通常、コバー
ル、42合金(42%Ni−鉄)、銅系合金等の導電性
に優れ、且つ強度が大きい金属板をフオトリソグラフイ
ー技術を用いたエッチング加工方法やスタンピング法等
により、図4(b)に示すような形状に加工して作製さ
れていた。2. Description of the Related Art In recent years, semiconductor devices have become more and more highly integrated and highly functional as represented by LSI ASICs due to the trend toward higher performance and lighter, thinner and smaller electronic devices (current trend). Accordingly, semiconductor devices are increasingly required to have more terminals (pins). Multi-terminal (pin) ICs, especially ASICs represented by gate arrays and standard cells, microcomputers, DSPs (Di
In order to make a semiconductor device such as a digital signal processor (QFP), a QFP (Q
A surface mount type package such as uadFlat Package) is used, and a QFP of up to 300-pin class has been put to practical use. QFP is shown in FIG.
As shown in FIG. 4A, a semiconductor element 420 is mounted on a die pad 411, and a single-layer lead frame 410 shown in FIG. 4B is used. After connecting the tip 412A of the inner lead and the terminal (electrode pad) 421 of the semiconductor element 420 with a wire 430, sealing is performed with a resin 440, the dam bar portion is cut, and the outer lead 413 is bent into a gull-wing shape. It is manufactured. Such QFP
Has a structure in which outer leads for electrically connecting to an external circuit are provided in four directions of a package, and has been developed as a structure capable of coping with multi-terminals (pins). The single-layer lead frame 410 used here is usually formed by etching a metal plate having high conductivity and high strength, such as Kovar, 42 alloy (42% Ni-iron), or a copper alloy, using photolithography technology. It was fabricated by processing into a shape as shown in FIG. 4B by a processing method, a stamping method, or the like.
【0003】しかしながら、近年の半導体素子の信号処
理の高速化及び高性能(機能)化は、更に多くの端子を
必要としている。これに対し、QFPでは、外部端子ピ
ッチを狭めることにより、更なる多端子化に対応できる
が、外部端子を狭ピッチ化した場合、外部端子自体の幅
も狭める必要があり、外部端子強度を低下させることと
なる。その結果、端子成形(ガルウイング化)の位置精
度あるいは平坦精度等において問題を生じてしまう。ま
た、QFPでは、アウターリードのピッチが、0.4m
m、0.3mmと更にピッチが狭くなるにつれ、これら
狭ピッチの実装工程が難しくなってきて、高度なボード
実装技術を実現せねばならない等の障害(問題)をかか
えている。また、インナーリード先端部を狭いピッチで
作製するにも加工限界がある。結局、加工限界と実装性
の面から、多ピン化を図ると、パッケージの拡大が必要
で、パッケージの小型化には限界が見え始めていた。[0003] However, in recent years, higher speed and higher performance (function) of signal processing of a semiconductor element require more terminals. On the other hand, the QFP can cope with further increase in the number of terminals by reducing the pitch of the external terminals. However, when the pitch of the external terminals is reduced, it is necessary to reduce the width of the external terminals themselves. Will be done. As a result, a problem arises in the positional accuracy or flatness accuracy of the terminal forming (gull-wing). In QFP, the outer lead pitch is 0.4 m
As the pitch is further reduced to m and 0.3 mm, the mounting process at these narrow pitches becomes more difficult, and there are obstacles (problems) such as the need to realize advanced board mounting technology. In addition, there is a processing limit in manufacturing the tip of the inner lead at a narrow pitch. In the end, in view of processing limitations and mountability, increasing the number of pins required an increase in the size of the package, and the size reduction of the package was beginning to reach its limits.
【0004】これら従来のQFPパッケージがかかえる
実装効率、実装性の問題を回避するために、半田ボール
をパッケージの外部端子に置き換えた面実装型パッケー
ジであるBGA(Ball Grid Array)と
呼ばれるプラスチックパッケージ半導体装置が開発され
てきた。BGAは、外部端子としての半田ボールを裏面
にマトリクス状(アレイ状)に配置した表面実装型半導
体装置(プラスチックパッケージ)の総称である。通
常、このBGAは、入出力端子を増やすために、両面配
線基板の片面に半導体素子を搭載し、もう一方の面に球
状の半田を取付けた外部端子用電極を設け、スルーホー
ルを通じて半導体素子と外部端子用電極との導通をとっ
ていた。球状の半田をアレイ状に並べることにより、端
子ピッチの間隔を従来のリードフレームを用いた半導体
装置より広くすることができ、この結果、半導体装置の
実装工程を難しくせず、入出力端子の増加に対応でき
た。しかしながら、このBGAは搭載する半導体素子と
ワイヤの結線を行う回路と、半導体装置化した後にプリ
ント基板に実装するための外部端子用電極とを、基材の
両面に設け、これらをスルーホールを介して電気的に接
続した複雑な構成であり、樹脂の熱膨張の影響によりス
ルーホールに断線を生じることもあり、作製上、信頼性
の点で問題が多かった。In order to avoid the mounting efficiency and mounting problems of these conventional QFP packages, a plastic package semiconductor called a BGA (Ball Grid Array) which is a surface mounting type package in which solder balls are replaced with external terminals of the package. Equipment has been developed. BGA is a generic name of a surface-mounted semiconductor device (plastic package) in which solder balls as external terminals are arranged in a matrix (array) on the back surface. Normally, in order to increase the number of input / output terminals, this BGA has a semiconductor element mounted on one side of a double-sided wiring board and an external terminal electrode provided with a spherical solder on the other side, and is connected to the semiconductor element through a through hole. The connection with the external terminal electrode was established. By arranging spherical solders in an array, the pitch of the terminals can be wider than that of a semiconductor device using a conventional lead frame. As a result, the mounting process of the semiconductor device is not difficult, and the number of input / output terminals is increased. Was able to respond. However, in this BGA, a circuit for connecting a semiconductor element to be mounted and a wire, and electrodes for external terminals for mounting on a printed circuit board after the semiconductor device is formed are provided on both sides of the base material, and these are provided through through holes. It is a complicated configuration in which the through holes are electrically connected to each other, and the through holes may be broken due to the effect of thermal expansion of the resin.
【0005】この為、上記BGAの作製プロセスの簡略
化、信頼性の低下を回避し、多ピン化、パッケージの小
型化に対応する、図2や図3に示すような、半導体装置
の製造方法が提案されている。この方法による半導体装
置は、従来の両面配線基板を用いたBGAと同様に、半
導体装置の一面に外部回路と接続するための外部端子の
一部を封止用樹脂から露出させて、配列させるものであ
り、新しい型のプラスチックBGA、CSP(Chip
size Package)に成り得るものである。
図2に示す半導体装置の製造方法は、導電性基板220
上にめっき法にて導電性金属からなる回路部210を形
成した回路部材200を用意し(図1(a))、該回路
部210上に半導体素子250を搭載し、必要な電気的
接続を行った(図2(b))後に、導電性基板220上
で樹脂封止し(図2(c))、樹脂封止された半導体装
置280Aを該導電性基板220から剥離して得る(図
2(d)、図2(e))、あるいは、更に露出した回路
部210の面に半田ボール290を付けて得る(図2
(f)))ものである。この方法の場合には、導電性基
板220上に形成された導電性金属からなる回路部21
0が、剥離し易いように、あらかじめ、導電性基板22
0の一面に凹凸を付ける表面処理を行い、且つ剥離性を
持たせる剥離処理を行っておく等の処置が採られる。
尚、ここでの表面処理としてはサンドブラストによるブ
ラスト処理、剥離処理としては導電性基板の表面に酸化
膜を生成する処理等が挙げられる。For this reason, a method of manufacturing a semiconductor device as shown in FIGS. 2 and 3 which simplifies the manufacturing process of the above-mentioned BGA, avoids a decrease in reliability, and responds to increase in the number of pins and downsizing of the package. Has been proposed. A semiconductor device according to this method is similar to a conventional BGA using a double-sided wiring board, in which a part of an external terminal for connecting to an external circuit is exposed on one surface of the semiconductor device from a sealing resin and arranged. Is a new type of plastic BGA, CSP (Chip
(size package).
The method for manufacturing a semiconductor device shown in FIG.
A circuit member 200 on which a circuit portion 210 made of a conductive metal is formed by a plating method is prepared (FIG. 1A), a semiconductor element 250 is mounted on the circuit portion 210, and necessary electrical connections are made. After performing (FIG. 2 (b)), the semiconductor device 280A sealed with resin is obtained on the conductive substrate 220 (FIG. 2 (c)), and the resin-sealed semiconductor device 280A is peeled off from the conductive substrate 220 (FIG. 2 (b)). 2 (d), FIG. 2 (e)), or obtained by attaching a solder ball 290 to the further exposed surface of the circuit section 210 (FIG. 2).
(F))). In the case of this method, the circuit portion 21 made of a conductive metal formed on the conductive substrate 220 is used.
0 is set in advance on the conductive substrate 22 so that
For example, a treatment such as performing a surface treatment for providing irregularities on one surface and performing a peeling treatment for imparting peelability is performed.
The surface treatment here includes blasting by sandblasting, and the peeling treatment includes treatment for forming an oxide film on the surface of the conductive substrate.
【0006】また、図3に示す半導体装置の製造方法
は、導電性基板320として、その一面にめっき法等に
より、金属層323を設けたものを使用して、金属層3
23上に、めっき法により回路部310を形成した回路
部材300を用意し(図3(a))、該回路部310上
に半導体素子350を搭載し、必要な電気的接続を行っ
た(図3(b))後に、導電性基板320上で樹脂封止
し、樹脂封止された半導体装置380Aを、前記金属層
323を溶解する(図3(d))ことにより、該導電性
基板320から剥離して得る(図3(d))、更に露出
した回路部310の面に半田ボール390を付けて得る
(図3(e))ものである。In the method of manufacturing a semiconductor device shown in FIG. 3, a conductive substrate 320 having a metal layer 323 provided on one surface thereof by plating or the like is used.
A circuit member 300 having a circuit portion 310 formed thereon by plating is prepared on the substrate 23 (FIG. 3A), a semiconductor element 350 is mounted on the circuit portion 310, and necessary electrical connections are made (FIG. 3A). 3 (b)), resin sealing is performed on the conductive substrate 320, and the resin-sealed semiconductor device 380A is dissolved by dissolving the metal layer 323 (FIG. 3 (d)). 3 (d), and further obtained by attaching a solder ball 390 to the exposed surface of the circuit portion 310 (FIG. 3 (e)).
【0007】[0007]
【発明が解決しようとする課題】しかし、図2や、図3
に示す半導体装置の製造方法は、樹脂封止された半導体
装置を導電性基板から剥離した際、個々のパッケージが
独立し、その後の取扱が、困難であるという不具合があ
り、問題となっていた。本発明は、これに対応するもの
で、図2や図3に示す、エレクトロフォーミング法(め
っき法)により回路部を形成した回路部材を用いた、プ
ラスチックBGA等の樹脂封止型半導体装置の作製にお
いて、通常の面付けされたリードフレーム(1連とも言
う)を用いた樹脂封止型の半導体装置作製の場合と同様
に、複数に面付けされた状態(1連の状態)で工程進行
ができる半導体装置の製造方法を提供しようとするもの
である。However, FIG. 2 and FIG.
The manufacturing method of the semiconductor device shown in (1) has a problem that when the resin-sealed semiconductor device is peeled from the conductive substrate, the individual packages are independent and the subsequent handling is difficult, which has been a problem. . The present invention corresponds to this, and manufactures a resin-sealed semiconductor device such as a plastic BGA using a circuit member having a circuit portion formed by an electroforming method (plating method) as shown in FIGS. In the same manner as in the case of manufacturing a resin-encapsulated semiconductor device using a normal imposed lead frame (also referred to as a series), the process progresses in a state where a plurality of impositions are performed (a series). It is an object of the present invention to provide a method of manufacturing a semiconductor device which can be performed.
【0008】[0008]
【課題を解決するための手段】本発明の樹脂封止型半導
体装置の製造方法は、導電性基板と、導電性基板上にめ
っきにより形成された導電性金属により少なくとも二次
元的に形成された回路部等を有する半導体装置用の回路
部材で、且つ、少なくとも回路部の一部が、導電性基板
の一面上に、直接または絶縁層を介してめっきにより形
成されている回路部材を用い、該回路部材に半導体素子
を搭載し、必要な電気接続を施し、樹脂封止した後に、
前記導電性基板から分離させて半導体装置を作製する方
式の、樹脂封止型半導体装置の製造方法であって、一つ
の半導体装置用の単位回路部を、面付けされた状態に、
複数個、導電性基板の上に作製し、該導電性基板の各回
路部毎に半導体素子を搭載し、必要な電気接続を行った
後、順次、各半導体装置毎の樹脂封止とともに、半導体
装置の封止用樹脂部と少なくとも一部において一体的に
連結する封止用樹脂からなる連結部を設けて、隣接する
半導体装置間を連結させ、処理する複数個の半導体装置
全てを封止用樹脂にて連結させた状態に樹脂封止する樹
脂封止工程と、処理する複数個の半導体装置全てを封止
用樹脂にて連結させた状態で、導電性基板より剥離する
剥離工程と、剥離後に、各半導体装置を互いに分離させ
るための、封止用樹脂からなる連結部を除去するトリミ
ング工程とを有することを特徴とするものである。According to a method of manufacturing a resin-encapsulated semiconductor device of the present invention, at least two-dimensionally a conductive substrate and a conductive metal formed by plating on the conductive substrate are formed. A circuit member for a semiconductor device having a circuit portion and the like, and at least a part of the circuit portion is formed on one surface of a conductive substrate by plating directly or through an insulating layer, After mounting the semiconductor element on the circuit member, making the necessary electrical connections, and sealing with resin,
A method of manufacturing a semiconductor device by separating from the conductive substrate, a method of manufacturing a resin-encapsulated semiconductor device, a unit circuit portion for one semiconductor device, in a state of being imposed,
A plurality of semiconductor devices are manufactured on a conductive substrate, and a semiconductor element is mounted on each circuit portion of the conductive substrate, and necessary electric connections are made. A connecting portion made of a sealing resin that is integrally connected at least partially with the sealing resin portion of the device is provided to connect adjacent semiconductor devices, and to seal all of a plurality of semiconductor devices to be processed. A resin sealing step of resin sealing in a state of being connected with a resin, a peeling step of peeling from a conductive substrate in a state where all of a plurality of semiconductor devices to be processed are connected by a sealing resin, and a peeling; And a trimming step of removing a connecting portion made of a sealing resin for separating the semiconductor devices from each other.
【0009】[0009]
【作用】本発明の樹脂封止型半導体装置の製造方法は、
上記のような構成にすることにより、BGAの作製プロ
セスの簡略化、信頼性の低下を回避し、多ピン化、パッ
ケージの小型化に対応する図2や、図3に示すエレクト
ロフォーミング法(めっき法)により回路部を形成し
た、プラスチックBGAの作製において、通常の面付け
されたリードフレーム(1連とも言う)を用いた樹脂封
止型の半導体装置作製の場合と同様に、複数に面付けさ
れた状態(1連の状態)で工程進行を可能とするもの
で、この結果、作業が安定的にでき、コスト低下にも繋
がる。具体的には、必要に応じてパッケージ裏面に絶縁
層を塗布する工程や、半田めっき工程を、処理する複数
個の半導体装置全てを封止用樹脂にて連結させた状態
で、且つ、導電性基板より剥離した状態で行うことを可
能とするものである。詳しくは、導電性基板と、導電性
基板上にめっきにより形成された導電性金属により少な
くとも二次元的に形成された回路部等を有する半導体装
置用の回路部材で、且つ、少なくとも回路部の一部が、
導電性基板の一面上に、直接または絶縁層を介してめっ
きにより形成されている回路部材を用い、該回路部材に
半導体素子を搭載し、必要な電気接続を施し、樹脂封止
した後に、前記導電性基板から分離させて半導体装置を
作製する方式の、樹脂封止型半導体装置の製造方法であ
って、一つの半導体装置用の単位回路部を、面付けされ
た状態に、複数個、導電性基板の上に作製し、該導電性
基板の各回路部毎に半導体素子を搭載し、必要な電気接
続を行った後、順次、各半導体装置毎の樹脂封止ととも
に、半導体装置の封止用樹脂部と少なくとも一部におい
て一体的に連結する封止用樹脂からなる連結部を設け
て、隣接する半導体装置間を連結させ、処理する複数個
の半導体装置全てを封止用樹脂にて連結させた状態に樹
脂封止する樹脂封止工程と、処理する複数個の半導体装
置全てを封止用樹脂にて連結させた状態で、導電性基板
より剥離する剥離工程と、剥離後に、各半導体装置を互
いに分離させるための、封止用樹脂からなる連結部を除
去するトリミング工程とを有することにより、これを達
成している。The method of manufacturing a resin-encapsulated semiconductor device according to the present invention comprises:
With the above-described configuration, the electroforming method (plating) shown in FIGS. 2 and 3 corresponding to the simplification of the manufacturing process of the BGA, the reduction in the reliability, the increase in the number of pins, and the miniaturization of the package are avoided. In the production of a plastic BGA in which a circuit portion is formed by a method, a plurality of impositions are performed in the same manner as in the case of manufacturing a resin-encapsulated semiconductor device using a normal impositioned lead frame (also referred to as a series). This allows the process to proceed in a completed state (a series of states). As a result, the work can be performed stably, leading to a reduction in cost. Specifically, if necessary, a step of applying an insulating layer to the back surface of the package or a solder plating step is performed in a state where all of a plurality of semiconductor devices to be processed are connected by a sealing resin, and This can be performed in a state of being separated from the substrate. Specifically, a circuit member for a semiconductor device having a conductive substrate and a circuit portion or the like formed at least two-dimensionally by a conductive metal formed by plating on the conductive substrate, and at least one of the circuit portions Department
On one surface of the conductive substrate, using a circuit member formed by plating directly or via an insulating layer, mounting a semiconductor element on the circuit member, making necessary electrical connections, and after resin sealing, A method for manufacturing a resin-encapsulated semiconductor device, in which a semiconductor device is manufactured by being separated from a conductive substrate, wherein a plurality of unit circuit portions for one semiconductor device are electrically After mounting on a conductive substrate, mounting a semiconductor element for each circuit portion of the conductive substrate, making necessary electrical connections, sequentially sealing the resin for each semiconductor device, and sealing the semiconductor device. A connecting portion made of a sealing resin integrally connected to at least a part of the sealing resin portion is provided to connect adjacent semiconductor devices, and all of a plurality of semiconductor devices to be processed are connected by the sealing resin. Resin sealing for resin sealing A peeling step of peeling the semiconductor device from the conductive substrate in a state where all of the plurality of semiconductor devices to be processed are connected with the sealing resin, and a sealing process for separating the semiconductor devices from each other after the peeling. This is achieved by having a trimming step of removing the connecting portion made of resin.
【0010】[0010]
【発明の実施の形態】本発明の樹脂封止型半導体装置の
製造方法を図に基づいて説明する。図1は本発明の樹脂
封止型半導体装置の製造方法の実施の形態の1例を示し
たものである。図1中、110は回路部材、113は単
位回路部、115は治具孔、117はダイパッド、11
8は端子部、120は封止用樹脂、125は連結部、1
25Aはトリミング部、130は連結状態の半導体装置
群、140は半導体装置(1個)である。先ず、1つの
半導体装置用の回路である単位回路部113を、複数個
面付けした状態で、導電性基板110Aの表面処理を施
した一面に形成した回路部材110を用意する。(図1
(a))表面処理はブラスト処理で、導電性基板110
Aの回路を形成する側の面を粗化するものである。回路
部の形成は、めっきレジストを導電性基板の表面処理面
側にパターンニング形成し、露出した面にめっきを施す
ものである。半導体素子1個に対応する単位回路部11
3は、例えば、図1(a1)に示すような形状のもので
ある。回路部のめっき構成は、特に限定されないが、ワ
イヤボンディング性等から、例えば、導電性基板側か
ら、順に、Pd、Ni、Pdをそれぞれ0.1μm、5
μm、0.1μmの厚に形成するものが挙げられる。図
1に示す回路部材は、導電性基板の一面に、回路部全体
を直接めっき形成したものであるが、特にこれに限定は
されない。DESCRIPTION OF THE PREFERRED EMBODIMENTS A method for manufacturing a resin-sealed semiconductor device according to the present invention will be described with reference to the drawings. FIG. 1 shows an example of an embodiment of a method of manufacturing a resin-sealed semiconductor device according to the present invention. In FIG. 1, 110 is a circuit member, 113 is a unit circuit portion, 115 is a jig hole, 117 is a die pad, 11
8 is a terminal part, 120 is a sealing resin, 125 is a connecting part, 1
25A is a trimming unit, 130 is a semiconductor device group in a connected state, and 140 is a semiconductor device (one). First, in a state where a plurality of unit circuit portions 113, which are circuits for one semiconductor device, are mounted, a circuit member 110 formed on one surface of the conductive substrate 110A that has been subjected to a surface treatment is prepared. (Figure 1
(A)) The surface treatment is a blast treatment, and the conductive substrate 110
The surface on the side where the circuit A is formed is roughened. The circuit portion is formed by patterning a plating resist on the surface-treated surface side of the conductive substrate and plating the exposed surface. Unit circuit section 11 corresponding to one semiconductor element
3 has a shape as shown in FIG. 1 (a1), for example. Although the plating configuration of the circuit portion is not particularly limited, for example, from the conductive substrate side, Pd, Ni, and Pd are each 0.1 μm and 5 μm in order from the conductive substrate side.
One having a thickness of 0.1 μm or 0.1 μm is exemplified. The circuit member shown in FIG. 1 is obtained by directly plating the entire circuit portion on one surface of a conductive substrate, but is not particularly limited thereto.
【0011】次いで、半導体素子をそれぞれの単位回路
部113のダイパッド117に搭載した後、半導体素子
の端子部と単位回路部113の端子部118とワイヤボ
ンディング接続を行った後、各半導体装置毎の樹脂封止
とともに、半導体装置の封止用樹脂部と少なくとも一部
において一体的に連結する封止用樹脂からなる連結部1
25を設けて、隣接する半導体装置140間を連結さ
せ、処理する複数個の半導体装置全てを封止用樹脂にて
連結させた状態に樹脂封止する。(図1(b))次い
で、処理する複数個の半導体装置140全てを封止用樹
脂120にて連結させた状態(130)で、導電性基板
110Aより剥離する。(図1(c))剥離後、封止用
樹脂からなる連結部125を除去するトリミング工程を
行い、各半導体装置140を互いに分離させる。(図1
(d))Then, after mounting the semiconductor element on the die pad 117 of each unit circuit section 113, and performing wire bonding connection between the terminal section of the semiconductor element and the terminal section 118 of the unit circuit section 113, Connecting portion 1 made of a sealing resin integrally connected at least partially with the sealing resin portion of the semiconductor device together with the resin sealing.
The semiconductor device 140 is connected to the semiconductor device 140, and the plurality of semiconductor devices to be processed are all sealed with a sealing resin. (FIG. 1B) Next, in a state (130) in which all of the plurality of semiconductor devices 140 to be processed are connected by the sealing resin 120, the semiconductor device 140 is separated from the conductive substrate 110A. (FIG. 1C) After the peeling, a trimming step of removing the connecting portion 125 made of the sealing resin is performed to separate the semiconductor devices 140 from each other. (Figure 1
(D))
【0012】図1に示す例は、図2に示す半導体装置製
造の場合と同様に、導電性基板の面から樹脂封止後、半
導体装置を引張り剥離するものであるが、図3に示す半
導体装置製造の場合のように、予め導電性基板一面上に
金属層を設けておき、樹脂封止後、導電性基板一面上に
設けられている金属層を溶解することにより剥離しても
良い。この場合は、例えば、導電性基板としては、鉄−
ニッケル系、鉄−ニッケル−クロム系、鉄−ニッケル−
カーボン系のものを用い、予め、その一面に、後に剥離
の為に溶解させる金属層として銅層を設けておき、銅層
上に回路部として、順次、Au、Ni、Pd層をそれぞ
れ0.1μm、5μm、0.1μm厚にめっき形成す
る。In the example shown in FIG. 1, as in the case of manufacturing the semiconductor device shown in FIG. 2, after the resin is sealed from the surface of the conductive substrate, the semiconductor device is pulled off, and the semiconductor device shown in FIG. As in the case of manufacturing a device, a metal layer may be provided on one surface of a conductive substrate in advance, and after sealing with a resin, the metal layer provided on one surface of the conductive substrate may be dissolved to be separated. In this case, for example, iron-
Nickel-based, iron-nickel-chromium-based, iron-nickel-
Using a carbon-based material, a copper layer is previously provided on one surface as a metal layer to be dissolved later for peeling, and Au, Ni, and Pd layers are sequentially formed on the copper layer as circuit portions in the order of 0.1. Plating is formed to a thickness of 1 μm, 5 μm, and 0.1 μm.
【0013】[0013]
【発明の効果】本発明は、上記のように、更なる樹脂封
止型半導体装置の高集積化、高機能化が求められる状況
のもと、従来のBGAにおける不具合を伴なわず、多ピ
ン化、ハッケージの小型化を達成でき、図2や図3に示
す、エレクトロフォーミング法(めっき法)により回路
部を形成した、プラスチックBGAの作製において、通
常の面付けされたリードフレーム(1連とも言う)を用
いた樹脂封止型の半導体装置作製の場合と同様に、複数
に面付けされた状態(1連の状態)で工程進行ができる
製造方法の提供を可能としている。According to the present invention, as described above, under the circumstances where higher integration and higher functionality of a resin-encapsulated semiconductor device are required, the conventional multi-pin type semiconductor device can be used without a defect in a conventional BGA. In the production of a plastic BGA having a circuit portion formed by an electroforming method (plating method) as shown in FIGS. As in the case of manufacturing a resin-encapsulated semiconductor device using the above-described method, it is possible to provide a manufacturing method in which the process can be performed in a state in which a plurality of semiconductor devices are imposed (a series).
【図1】本発明の樹脂封止型半導体装置の製造方法の1
例を示した図FIG. 1 shows a method 1 for manufacturing a resin-sealed semiconductor device of the present invention.
Figure showing an example
【図2】エレクトロフォーミング法(めっき法)により
作製された回路部材を用いた半導体装置の製造方法の工
程図FIG. 2 is a process chart of a method for manufacturing a semiconductor device using a circuit member manufactured by an electroforming method (plating method).
【図3】エレクトロフォーミング法(めっき法)により
作製された回路部材を用いた半導体装置の製造方法の工
程図FIG. 3 is a process diagram of a method for manufacturing a semiconductor device using a circuit member manufactured by an electroforming method (plating method).
【図4】リードフレームとQFPを説明するための図FIG. 4 is a diagram for explaining a lead frame and a QFP.
110 回路部材 113 単位回路部 115 治具孔 117 ダイパッド 118 端子部 120 封止用樹脂 125 連結部 125A トリミング部 130 連結状態の半導体装置群 140 半導体装置(1個) 200 回路部材 210 回路部 220 導電性基板 225 治具孔 230 銀めっき部 250 半導体素子 251 端子部 255 ワイヤ 270 封止用樹脂 280、280A 半導体装置 290 半田ボール 300 回路部材 310 回路部 320 導電性基板 321 導電性基板素材 323 金属層 325 治具孔 330 銀めっき部 350 半導体素子 351 端子部 355 ワイヤ 370 封止用樹脂 380、380A 半導体装置 390 半田ボール 410 単層リードフレーム 411 ダイパッド 412 インナーリード 413 アウターリード 414 ダムバー 415 吊りリード 416 枠部(フレーム) 420 半導体素子 421 端子(電極パッド) 430 ワイヤ 440 樹脂 110 circuit member 113 unit circuit part 115 jig hole 117 die pad 118 terminal part 120 sealing resin 125 connecting part 125A trimming part 130 connected semiconductor device group 140 semiconductor device (one piece) 200 circuit member 210 circuit part 220 conductivity Substrate 225 Jig hole 230 Silver plated part 250 Semiconductor element 251 Terminal part 255 Wire 270 Sealing resin 280, 280A Semiconductor device 290 Solder ball 300 Circuit member 310 Circuit part 320 Conductive substrate 321 Conductive substrate material 323 Metal layer 325 Hole 330 Silver plating section 350 Semiconductor element 351 Terminal section 355 Wire 370 Sealing resin 380, 380A Semiconductor device 390 Solder ball 410 Single layer lead frame 411 Die pad 412 Inner lead 413 Outer 414 dam bar 415 hanging lead 416 frame part (frame) 420 semiconductor devices 421 terminal (electrode pad) 430 wire 440 resin
Claims (1)
より形成された導電性金属により少なくとも二次元的に
形成された回路部等を有する半導体装置用の回路部材
で、且つ、少なくとも回路部の一部が、導電性基板の一
面上に、直接または絶縁層を介してめっきにより形成さ
れている回路部材を用い、該回路部材に半導体素子を搭
載し、必要な電気接続を施し、樹脂封止した後に、前記
導電性基板から分離させて半導体装置を作製する方式
の、樹脂封止型半導体装置の製造方法であって、一つの
半導体装置用の単位回路部を、面付けされた状態に、複
数個、導電性基板の上に作製し、該導電性基板の各回路
部毎に半導体素子を搭載し、必要な電気接続を行った
後、順次、各半導体装置毎の樹脂封止とともに、半導体
装置の封止用樹脂部と少なくとも一部において一体的に
連結する封止用樹脂からなる連結部を設けて、隣接する
半導体装置間を連結させ、処理する複数個の半導体装置
全てを封止用樹脂にて連結させた状態に樹脂封止する樹
脂封止工程と、処理する複数個の半導体装置全てを封止
用樹脂にて連結させた状態で、導電性基板より剥離する
剥離工程と、剥離後に、各半導体装置を互いに分離させ
るための、封止用樹脂からなる連結部を除去するトリミ
ング工程とを有することを特徴とする樹脂封止型半導体
装置の製造方法。1. A circuit member for a semiconductor device having a conductive substrate and a circuit portion formed at least two-dimensionally by a conductive metal formed on a conductive substrate by plating, and at least a circuit portion. A part of the circuit member is formed on one surface of the conductive substrate by plating directly or via an insulating layer, a semiconductor element is mounted on the circuit member, necessary electric connection is performed, and resin sealing is performed. A method of manufacturing a semiconductor device by separating the conductive substrate from the conductive substrate, wherein the unit circuit portion for one semiconductor device is placed in an imposed state. , A plurality, prepared on a conductive substrate, mounted with a semiconductor element for each circuit portion of the conductive substrate, after making the necessary electrical connection, sequentially, with resin sealing for each semiconductor device, The sealing resin part of the semiconductor device At least a part of a sealing resin that is integrally connected is provided to connect adjacent semiconductor devices, and a plurality of semiconductor devices to be processed are all connected by the sealing resin. A resin encapsulating step, a peeling step of peeling the semiconductor device from the conductive substrate in a state where all of the plurality of semiconductor devices to be processed are connected with the sealing resin, and after peeling, the semiconductor devices are separated from each other. A trimming step of removing a connecting portion made of a sealing resin for separating the semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17658597A JP3678883B2 (en) | 1997-06-18 | 1997-06-18 | Manufacturing method of resin-encapsulated semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17658597A JP3678883B2 (en) | 1997-06-18 | 1997-06-18 | Manufacturing method of resin-encapsulated semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH118260A true JPH118260A (en) | 1999-01-12 |
| JP3678883B2 JP3678883B2 (en) | 2005-08-03 |
Family
ID=16016146
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17658597A Expired - Fee Related JP3678883B2 (en) | 1997-06-18 | 1997-06-18 | Manufacturing method of resin-encapsulated semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3678883B2 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002289739A (en) * | 2001-03-23 | 2002-10-04 | Dainippon Printing Co Ltd | Resin-sealed semiconductor device, circuit member for semiconductor device, and method of manufacturing the same |
| JP2003046055A (en) * | 2001-07-31 | 2003-02-14 | Sanyo Electric Co Ltd | Plate, lead frame, and method of manufacturing semiconductor device |
| JP2005241629A (en) * | 2004-01-30 | 2005-09-08 | Semiconductor Energy Lab Co Ltd | Inspection device, inspection method, and manufacturing method for semiconductor device |
| JP2012134563A (en) * | 2012-04-06 | 2012-07-12 | Dainippon Printing Co Ltd | Resin sealed semiconductor device and semiconductor device circuit member |
-
1997
- 1997-06-18 JP JP17658597A patent/JP3678883B2/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002289739A (en) * | 2001-03-23 | 2002-10-04 | Dainippon Printing Co Ltd | Resin-sealed semiconductor device, circuit member for semiconductor device, and method of manufacturing the same |
| JP2003046055A (en) * | 2001-07-31 | 2003-02-14 | Sanyo Electric Co Ltd | Plate, lead frame, and method of manufacturing semiconductor device |
| JP2005241629A (en) * | 2004-01-30 | 2005-09-08 | Semiconductor Energy Lab Co Ltd | Inspection device, inspection method, and manufacturing method for semiconductor device |
| JP2012134563A (en) * | 2012-04-06 | 2012-07-12 | Dainippon Printing Co Ltd | Resin sealed semiconductor device and semiconductor device circuit member |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3678883B2 (en) | 2005-08-03 |
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