JPH1166127A - Signal observation method in logic simulation - Google Patents

Abstract

(57) [Summary] [Problem] To integrate partial circuits, the signal names connecting the partial circuits are changed to variable names to be temporarily stored. A signal whose signal cannot be observed is made observable, and efficient logic circuit verification is made possible. Before integrating partial circuits, partial circuits are integrated.
The input / output signals and the hierarchical identifiers of the hierarchical logic and the lower hierarchical logic are stored in the hierarchical information management table and the input / output signal table, respectively, and when integrating the partial circuits, a plurality of partial circuits are integrated into the partial circuit of the event evaluation unit. Then, since the signal name for event evaluation is replaced with a variable, the signal names before and after replacement are registered in the hierarchical information management table and the input / output signal table, and the signal names before and after optimization are associated with each other.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a technique for creating and optimizing a model of a target logic circuit for logic simulation.

[0002]

2. Description of the Related Art In order to speed up a logic simulation, there are the following methods for creating a simulation model of a target logic circuit.

A method of increasing the execution speed by reducing the number of partial circuits in the event evaluation unit. This method is described in, for example, application number P08-078999.
No. This is to determine whether or not the partial circuit is a combinational circuit, integrate the partial circuits that are the combinational circuits, and make one event evaluation unit, thereby reducing the number of partial circuits in the event evaluation unit, This is a method for speeding up the simulation.

[0004]

However, in the prior art, the partial circuits which are combinational circuits are integrated into one event evaluation unit, thereby reducing the number of partial circuits in the event evaluation unit and reducing the number of partial circuits in the simulation. It can be faster. However, when integrating the partial circuits, the names of the signal lines connecting the partial circuits (hereinafter, referred to as signal names) are changed to the names of the variables to be temporarily stored (hereinafter, referred to as variable names). Therefore, there is a problem that a signal cannot be observed with a signal name described by a designer during a simulation.

[0005]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, in the signal observation method in the logic simulation according to the present invention, before integrating the partial circuits, the input / output signals of the partial circuits, the hierarchical logic and the lower hierarchical logic, the hierarchical identifiers are stored in the hierarchical information management table, the input / output. Each of them is stored in a signal table, and it is determined whether the event evaluation unit is a partial circuit or a hierarchical logic. In the case of hierarchical logic, a library in which the hierarchical logic is registered is searched for using the identifier of the circuit as a key, and , A signal name connecting a plurality of partial circuits is converted into a signal name considering the hierarchy, the hierarchical logic is deleted, and the corresponding partial circuit is developed (hereinafter, flattening). ). The circuit to be simulated in which the hierarchical logic is composed of all partial circuits by the above means is referred to as application number P08-0.
No. 78999 integrates partial circuits (hereinafter referred to as optimization). At this time, if a plurality of partial circuits are integrated into a partial circuit of the event evaluation unit, the signal name for event evaluation is replaced with a variable, so the signal names before and after replacement are registered in the hierarchical information management table and the input / output signal table, Enables a signal to be observed using the logic signal name described by the designer.

[0007]

Embodiments of the present invention will be described below.
In this embodiment, a process is a partial circuit that is an event evaluation unit in a logic simulation. FIG.
FIG. 2 is a schematic explanatory view showing a logic simulation model creation processing procedure according to one embodiment of the present invention, FIG. 2 is a schematic explanatory view showing a target logic circuit for performing a logic simulation in one embodiment of the present invention, and FIG. Hierarchical logic in which one function is realized by combining a plurality of partial circuits in one embodiment and its logic description. FIG. 4 is a logic description based on FIG. 2 of a target logic circuit for performing a logic simulation in one embodiment of the present invention. 5, FIG. 5 is a schematic diagram of a logic simulation target circuit after flattening in which all the hierarchical logic circuits of FIG. 2 are replaced with partial circuits, and FIG. 6 is a schematic explanatory diagram of the logic simulation target logic circuit of FIG. −078
No. 999, a process integrable range diagram showing a range in which partial circuits can be conditionally integrated, FIG. 7 is a schematic explanatory diagram showing a data structure of a table storing hierarchical information of a logic circuit in the present invention, and FIG. 6 is a logical description in which some processes in the process integration possible range are integrated.

FIG. 1 shows a processing procedure when creating logic simulation data according to the present invention.
Input the logic circuit description 101 and store the hierarchical information storage unit 103
Is created as shown in FIG. Based on the hierarchy information storage unit 103, the hierarchy logic determination unit 104 determines whether or not the logic is hierarchical logic having a hierarchy. If the logic is not hierarchical logic, the next partial circuit is performed by the hierarchical logic determination unit 104. If the logic is determined to be hierarchical logic, the hierarchical identifier updating unit 10 expands the partial circuit of the lower hierarchy or the hierarchical logic having a further hierarchy.
In order to give uniqueness to the layer identifiers assigned to the sub-circuits in the lower layer, for example, “generated layer identifier” = “lower layer identifier” + “.” + “Higher layer” An identifier is generated according to the rule “identifier”, and the generated hierarchical identifier is stored in the hierarchical information management table of FIG. In the signal name conversion unit 106, for example, “generated signal name” = “lower layer signal name” in order to similarly give uniqueness to signal names connecting partial circuits in lower layers.
+ "." + "Identifier of higher hierarchy"
The generated signal name is stored in the input / output signal table. When the hierarchical logic has a multi-level hierarchy, the process proceeds to the level where the hierarchical logic disappears, and the hierarchical identifier updating unit 105 and the signal name converting unit 106 are sequentially performed from the lowest hierarchical level. After preparing to expand the lower hierarchy in this way, if the hierarchy is expanded by the hierarchy logic expansion unit 107, it can be expanded into partial circuits as shown in FIG. Processing Procedure 1 of Application No. P08-078999
Before 09 to 118, until all partial circuits are processed,
Steps 102 to 108 are repeated. 114, 115
Is a processing unit added according to the present invention. The variable name storage unit 114 stores the variable names generated by the process integration unit 113 in the input / output signal table of FIG.

FIG. 2 shows a target circuit for performing a logic simulation used in the present embodiment. P1, P2, P in the figure
3, P6, P7, P8, P9, P10, F11, F12
Is a hierarchy identifier. S1 to S15, SA1 to SA7, and SB1 to SB7 are signal names for connecting partial circuits. If F11 and F12 are applied to the hierarchical identifier of the hierarchical logic FA in the logic circuit according to the above rule, functional logic circuits, processes 7 and 9 are sequential circuits, processes 1, 2, 3, and
6, 8, and 10 are combinational circuits.

FIG. 3 shows an example of hierarchical logic (lower hierarchical logic) used in this embodiment. The functional logic 150 has the hierarchical identifier: FA, and the cut signal name: F1, F2, F3, F
4, F5 are input, and F6 and F7 are output. Hierarchical logic 1
50 functions are shown in the logic circuit: 151. Logic circuit: 15
Reference numeral 1 denotes four processes, each of which is composed of hierarchical identifiers A1, B1, C1, and D1 of each process and signal names SA1 and SA2 for connecting the partial circuits, all of which are combined circuits.

FIG. 4 shows an example of a logical description of a target circuit handled in this embodiment. For each process, the process type, process name, input / output signal name, variable name used in the process,
In addition, operations and the like are described according to syntax rules. The hierarchical logic is expressed by an instance sentence of the VHDL language.

Hereinafter, 101 to 108 and 11 in FIG.
4 will be described with reference to FIGS. 2 to 8. In the logical description input unit: 102, the logical description: 101
In the hierarchical information storage unit 103, the pointers to the character string table of the hierarchical information table and the input / output signal table and the pointers to the lower layers of the hierarchical information table are all null, and each table is Create For example, in the case of the process 1 of FIG. 2, the No. of the hierarchical information management table of FIG. 1, the pointer to the input / output signal table is set to 1, and other items are null.
To Next, the hierarchical logic determining unit 104 determines whether or not the hierarchical logic is present. When the hierarchical logic is determined, as shown in FIG. 2, a library is searched using, for example, a hierarchical logical name: FA, and the hierarchical logic shown in FIG. When registered in the hierarchy information table as a lower hierarchy, the No. of the hierarchy information management table in FIG. 11 to N
o. 14 and No. of the input / output signal table. 44 to N
o. 58, the character string being processed is sequentially registered in the character string hash table. At this time, the hierarchical information table No. The pointer to the lower hierarchy of No. 4 is changed from null to 11, and the No. of the table is no. After 11, the layer identifiers of the partial circuits in FIG. 3 and the pointers to the input / output signal table are registered as 44, 50, 53, and 56, respectively. The input / output signal name of each partial circuit is represented by the No. of the input / output signal table. Input / output divisions are added to each of the partial circuits from 44, 50, 53, and 56, and the signal names are registered in the character string table.
Registered in the input / output signal table. After all the partial circuits are registered in each table in this manner, the layer identifier updating unit 105 applies the above rule, and “generated layer identifier” = “layer identifier of lower layer” + “.” + “ When generated according to the rule “layer identifier of upper layer”, for example, FIG.
“A1” in FIG. 5 becomes “A1.F11” in FIG. The generated hierarchical identifier is registered in the character string table, and a pointer to the table is set in a corresponding area of the hierarchical information table, in this case, the No. of the hierarchical information table. The pointer to the character string table after conversion of 11 is converted from null to 51.
Update to Similarly, the layer identifiers B1, C1, D1 in FIG.
Is processed as shown in the hierarchical information table of FIG. Next, the signal name conversion unit 106 also applies the above rule,
“Generated signal name” = “Lower layer signal name” + “.” +
When the signal name “SA1” other than the cut edge in FIG.
A1. F11 ". The generated signal name is registered in a character string table, and in this case, N
o. The pointer to the character string table after the conversion of 49 is updated from null to 55. Similarly, when the signal name SA2 in FIG. 3 is processed, the input / output signal table in FIG. 7 is obtained. Also, the signal names F1 to F7 of the cuts connecting the signal connected to the hierarchical logic (the signal of the upper hierarchy) of FIG. 3 and the partial circuit of the lower hierarchy of the hierarchical logic are signals connected to the signal of the upper hierarchy. All of these signal names are registered in the input / output signal table as the converted signal names of the upper signal names. For example, since the cut signal name F1 of F11 in FIG. 2 is connected to the signal name SA1 of the upper layer, the pointer 3 to the converted character string table is set to the input / output signal table No.
Null pointer to the converted string table of 44
Update from to 3. Similarly, the cut signals F2 and F in FIG.
Processing of 3, F4, F5, F6, and F7 results in the input / output signal table of FIG. As a result, the hierarchy information before and after the hierarchical logic development can be stored. Further, by integrating the process-integrable partial circuits in the process-integrable range diagram in FIG. 6 after the hierarchical logic development, unnecessary signals can be recognized.
For example, the outputs SA4 and SA5 of the process P2 in FIG.
If these signals are unnecessary when integrated, and if you want to make these variables, create a new variable name, for example, $ svar1,
The generated name $ svar1 is registered in the character string table.
The pointer 57 to the character string table is set to No. of the input / output table in FIG. The pointer to the converted character string table in 47 is updated from 8 to 57. If the signal is not deleted and made a variable, the outputs SA4 and SA4 of the process P2 in FIG.
5 by the hierarchical identifiers B1. In order to make it the input of F11, it is substituted into the right side of the equation. In this case, the process 2 and the process B1 in the hierarchical identifier PA in FIG. 6 are changed from the logic circuit description in FIG. 4 to the logic circuit description after integration in FIG. Therefore, v2: = (S3 AND S4) OR (S3 O
RS4). The processing related to FIG.
No. 08-078999. However, the signal whose unnecessary event evaluation unit has been optimized and which has become an unnecessary signal in the simulation is a signal necessary for the designer to observe the signal. Then, application number P08-078
In addition to the processing of No. 999, the processing section of the variable name storage section: 114 will be described. The aforementioned signals: SA4 and SA5 are
The variables are $ svar1 and $ svar2, respectively. When this signal name conversion information is registered in the hierarchical information storage table of FIG. 7, No. of the input / output signal table corresponding to the output signal of process 2 in FIG. The pointer null to the character string table after the conversion of 8 and 9 is updated to the pointers 57 and 58 to the corresponding character string hash table, and the process 3 in FIG.
No. of the input / output signal table corresponding to the output signal No. 1
Null pointer to character string table after conversion of 7, 18
l is a pointer 5 to the corresponding character string hash table
7 and 58, respectively. Also, the process A of FIG.
No. 1 of the input / output signal table corresponding to the input signal No. 1 4
Pointers to character string tables after conversion of 7, 48
To the corresponding string hash table 57,
No. 58 in the input / output signal table corresponding to the input signal of the process B1 in FIG. The pointers 8 and 9 to the converted character string tables 50 and 51 are updated to pointers 57 and 58 to the corresponding character string hash tables, respectively. In this way, from the hierarchical information storage table expressing the signals before and after the optimization, an area for holding the value of the event at the time of the simulation corresponding to the signal after the optimization is provided, and the value of the signal in the already known simulation is provided. It can be easily observed.

As described above, application number P08-07
When observing a signal after optimization according to No. 8999 at the time of logic simulation, a designer can observe the signal with the signal name described at the time of logic design.

[0014]

Advantageous effects obtained by typical ones of the inventions disclosed in the present application will be briefly described.
It is as follows. That is, according to the signal observation method in the logic simulation of the present invention, since the signals before and after the optimization are associated with each other, the signal can be observed by the signal name described at the time of the logic design by the designer, so that the time for analyzing the logic circuit is reduced. , And efficient logic circuit verification can be performed.

[Brief description of the drawings]

FIG. 1 is a schematic explanatory diagram showing a logic simulation data creation processing procedure according to an embodiment of the present invention.

FIG. 2 is a schematic explanatory view showing a target logic circuit for performing a logic simulation in one embodiment of the present invention.

FIG. 3 is a hierarchical logic circuit diagram in which one function is realized by combining a plurality of partial circuits in one embodiment of the present invention.

FIG. 4 is a part of a logic description based on FIG. 2 of a target logic circuit to be subjected to a logic simulation in one embodiment of the present invention.

FIG. 5 is a schematic explanatory diagram showing a target logic circuit for performing a logic simulation after optimization in one embodiment of the present invention.

FIG. 6 is a schematic explanatory diagram showing a range in which processes can be integrated in one embodiment of the present invention.

FIG. 7 is a schematic explanatory diagram showing a data structure of a hierarchical information table and an input / output signal table of a target logic circuit to be subjected to a logic simulation in one embodiment of the present invention.

FIG. 8 is a part of a description of a logic circuit after process integration in one embodiment of the present invention.

[Explanation of symbols]

101: logic description, 109: logic circuit connection information,
117 ... Logic simulation model.

Claims (4)

[Claims] A plurality of logic expressions or logic gates are connected by a signal line to a partial logic of an event evaluation unit, which is an element for calculating an output signal with respect to a change in an input signal, and a plurality of partial logics. A hierarchical identifier for identifying a hierarchical logic expressed only by an input / output signal line other than a signal line obtained by connecting partial logics in a logic having one function is provided, and a circuit configured by the partial logic and the hierarchical logic is provided. In the method of simulating logic and observing signals in the circuit, it is determined whether or not the hierarchical identifier of the logic in the circuit is hierarchical logic. The name of the signal line connecting the logics can be immediately identified as being developed from the hierarchical logic, and the name of the signal line that is unique at the development destination (hereinafter referred to as signal name)
An area in which the signal names before and after optimization can be uniquely determined so that the signal names before and after optimization can be retained so that the signal names before and after optimization can be retained, and the event evaluation value can be retained. A signal line name generation method characterized in that the signal names before and after the optimization are stored in a character string area linked with the above, and the signal names before and after the optimization can be immediately obtained. 2. A partial logic of an event evaluation unit, which is an element for calculating a signal on the output side in response to a change in a signal on the input side, and a plurality of partial logics are connected by a signal line. A hierarchical logic expressed only by input / output signal lines other than signal lines in which partial logics in a logic having one function are connected to each other, and a part of an event evaluation unit of a circuit constituted by the partial logic and the hierarchical logic In the method of simulating an optimized circuit that combines partial logics to reduce the number of circuits and observing the signals in the circuit, the event evaluation value of the signal line that was connected before the combination by combining the partial logics When generating a variable name for holding a variable, a word that can be identified as a generated name (hereinafter referred to as a search identifier) in order to generate a variable name in consideration of ease of signal observation, A character string that includes a signal name and is linked by a symbol that separates the word from the signal name (hereinafter, referred to as a generated name separator) is generated as a variable name, and the signal name before and after optimization is retained so that the signal name before and after optimization can be retained. A signal line in which a signal name can be uniquely determined and stored in a character string area linked to an area holding an event evaluation value, and a signal name generated after coupling of partial circuits can be obtained immediately. Name generation method. 3. A method for performing a logic simulation of a partial logic circuit coupled with a signal name and a signal name not optimized as in claim 1 and observing a signal in the circuit, wherein the signal name before optimization is used. When observing a signal in the above, it is specified from the layer identifier of claim 1 whether the corresponding layer logic or partial logic,
2. A signal observing method in a logic simulation, wherein a signal can be observed with a signal name before generation by following the signal name according to claim 1 with a signal name before optimization. 4. A method for performing a logic simulation of a partial logic circuit coupled by a signal name and a signal name not optimized as in claim 2 and observing a signal in the circuit, wherein the signal name before optimization is used. (1) A search identifier and a generated name separator are added to a signal name before optimization to generate a signal name after optimization, and (2) the signal name holds an event evaluation value. Since it is uniquely determined to be a character string area linked to the area to be optimized, it is immediately determined whether or not the signal name has been optimized. (3) If the signal name has been optimized, it is linked to the character string area (4) In the case of a signal name before optimization, a character string area is uniquely determined based on the signal name before optimization and linked to the character string area. Get the event value from the area that holds the event evaluation value , Signal observing method in logic simulation, characterized in that the method for observing signals with a signal name before optimization.