JPH0756656B2 - Gate logic automatic update method - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an automatic logic design system using a computer, and more particularly to updating gate logic in a packaging design phase.

[Background of the Invention]

In recent years, as logic devices have grown in scale and VLSI, the functional gates such as Boolean expressions, truth tables, and standard macro logic have been input to the computer for the purpose of improving the design quality of logic devices and reducing man-hours. An automatic logic generation system has been developed which automatically generates a gate logic indicating a level connection. The automatic logic generation system handles only logic information generated by itself, such as gate information and net information, and is therefore useful for initial conversion from functional logic to gate logic in the design phase before implementation design. The mounting position information of the gate, mounting information such as gate and pin exchange information, and acquisition optimization information are added in the mounting design phase. When a part of the functional logic is changed in such an implementation design phase, a new gate logic is generated from the changed functional logic by an automatic logic generation system,
There is a big problem that all the information added by the mounting design phase concerning the existing portion of the old gate logic which does not need to be changed is also lost.

To solve this problem, one must know how to automatically identify the unneeded part of the old gate logic and combine it with the new gate logic. However, at the moment such methods are, to our knowledge,
Not known. An example of a method for automatically verifying the equivalence of logic functions between logic circuits is described in the following document, but it cannot solve the above problem by itself.

Reference (1) GLSmith et al. “Boolean Comparison of Hardw
are and Flowcharts "IBM J. Res. Develop., Vol.26, No.1,
Jan.1982, pp. 106-116 Reference (2) SBAkers “A Procedure for Functional De
sign Verification "10th FTCS, 1980, pp. 65-67 [Object of the invention] An object of the present invention is to implement a function included in an old gate logic part that does not need to be changed when a functional logic is changed in an implementation design phase in an automatic logic design system. It is to provide a new method for automatically inheriting information or manual optimization information to a new gate logic.

[Outline of Invention]

The present invention relates to a new intermediate gate logic (which does not have mounting information or manual optimization information) derived from the changed functional logic by the automatic logic generation system, and an existing old gate logic (which has the above information). ), The correspondence between partial logics is checked to identify common partial logics and non-common partial logics of both gate logics. For that purpose, for example, the sharing ratio of the external input / output signal or the input / output gate can be used as an index, and in some cases, the logic function verification method described in the above-mentioned document can be used. Then, by selecting the corresponding part of the old gate logic for the common partial logic and selecting the corresponding part of the new intermediate gate logic for the non-common partial logic, and merging them, The new gate logic in which the implementation information and the manual optimization information about the unneeded portion of the old gate logic are stored is generated.

Example of Invention

First, the operating environment of the gate logic automatic update system according to the present invention will be described with reference to FIG. The left part of FIG. 2 shows an operation flow at the time of initial design. After the functional logic design, a functional logic file 110 is created using the functional logic input system 100, a gate logic file 111 is created using the automatic logic generation system 101, and mounting information is added using the placement and routing system 102. A gate logic file 112 with mounting information is created, and if necessary, the gate logic is manually optimized using the gate logic input system 103, and a manually optimized gate logic file 113 with mounting information is created.

The right part of FIG. 2 shows the operation flow when the functional logic design is changed. The functional logic input system 100 is used to update the functional logic file 110 to create a functional logic file 114 after logic change, and the automatic logic generation system 101 is used to create a gate logic file 115 after logic change. And manual optimization gate logic file with mounting information 11
By inputting 3 and using the automatic logic update system 104, the gate logic file 116 with mounting information and manual optimization information after the logic change is created and the gate logic file 116 is added using the gate logic input system 103. Of the gate logic file 117 is added, and if necessary, the gate logic is further manually optimized to create a gate logic file 117 with the logic-changed mounting information and manual optimization information.

Next, the contents of each of the gate logic file 111 created by the automatic logic generation system 101 and the gate logic file 113 with mounting information and human optimization information created by the placement and routing system 102 and the gate logic input system 103 are stored. The difference will be described. Figure 3 shows the gate logic file 11
An example of the gate logic which is the content of 1 is shown, and FIG. 4 shows the gate logic which is the content of the gate logic file 113 corresponding to this gate logic. The differences between the gate logics of FIGS. 3 and 4 are as follows.

(1) Gate replacement: In the gate array design, generally 1
There may be a plurality of gates in one cell, and gates of the same gate type may exist in two or more different cells or two or more in the same cell. Since the logic automatic generation system 101 generates the gate logic by using the representative gate, the placement and routing system 102 performs the gate replacement. The gate 201 in FIG. 3 is a 3-input AND
The gate is a representative gate, and its gate type is represented by a pair of a cell type LPG101 and a logical symbol name L1.
3 and 4, LPG101 / L1, LPG101 / L9, LPG101
Since / L11 represents the same gate type, gates 202 and 20
Gate 7 is replaced by gates 302 and 307, respectively.

(2) Pin exchange: When the input / output pins are selectable, the logic automatic generation system 101 selects the pin numbers in ascending order to generate the gate logic, so that the placement and routing system 102 performs the pin exchange. The pin interchangeability is as follows.

(A) In a single function gate such as the gate 201 in FIG. 3, each input pin is replaceable.

(B) A composite gate, such as the gate 204 in FIG. 3, is composed of multiple subgates.

More specifically, the gate 204 is a 3-input AND sub-gate 204-A having input pins of 3, 4, 5 and output pin of 2.
And has 16th, 17th and 18th input pins and 19th output pin 3
It is composed of an input AND sub-gate 204-B and a 2-input OR sub-gate which receives the outputs of these sub-gates and has the first output pin. In such a composite gate,
The sub-gates of the same sub-gate type can have their pins exchanged for each sub-gate, and each sub-gate can have its input pin exchanged.

In FIGS. 3 and 4, the gate 201 has its input pins replaced like the gate 301, and the gate 204 has its sub-gate input / output pins replaced like the gate 304.

(3) Manual logic optimization: Since the number of cells that can be arranged in one LSI is limited, the number of gates of a specific gate type that can be used is also limited. Therefore, when there is a shortage of gates of a specific gate type, gates of other alternative gate types are assigned. In this way, various human logic optimizations are performed from the viewpoint of optimizing the entire LSI. In FIGS. 3 and 4, gate 206 has been replaced by gate 306 by manual logic optimization.

Next, the functional logic corresponding to the gate logic shown in FIG. 3 is logically changed, and the contents of the gate logic file 115 after the logical change are created by the automatic logic generation system 101 from the functional logic file 114 after the logical change. Fifth gate logic
The points where logic changes between these gate logics are shown in the figure will be described.

(1) Gate 203 and connection nets 214, 215, 223 for this gate
Has been removed and the connection net 436,4 between this gate and gate 407
37,423 have been added.

(2) The connection net 213 of the gate 201 is deleted, and the gate 20
Connection net 216 of 4,205 is connection net 416 of gate 403,404.
And a connection net 415 for the gate 402 is added.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a flow chart showing the entire gate logic automatic updating process according to the present invention. Below, 2 in FIG. 4 and FIG.
Taking one gate logic as an example, the gate logic automatic update processing procedure will be sequentially described based on the processing flow of FIG.

Step 501: The gate logic is defined in a fixed length record format called IC operation, together with mounting information for each gate component. This step is performed for the subsequent steps from the IC operation of each of the old gate logic (content of file 113) and the new intermediate gate logic (content of file 115), gate table, input / output pin table, input / output connection. Create a net table composed of tables and so on.

Step 502: This step recognizes the corresponding gate using the following four indexes.

(1) External input signal sharing ratio: R _CIS (G _I , G _J ) Here, N _IS (G _I ) and N _IS (G _J ) represent the number of external input signals that determine the output logical value of the gate G _I of the old gate logic and the gate G _J of the new intermediate gate logic, respectively. In addition, N _CIS (G _I ,
G _J ) represents the number of common signals among the external input signals of G _I and G _J.

(2) External output signal sharing rate: R _COS (G _I , G _J ) Here, N _OS (G _I ) and N _OS (G _J ) represent the number of external output signals whose output logical values of the gates G _I and G _J determine the logical value of the external output signal. Further, N _COS (G _I , G _J ) represents the number of common signals among the external output signals of G _I and G _J.

(3) Input gate sharing ratio: R _CIG (G _I , G _J ) Here, N _IG (G _I ) and N _IG (G _J ) represent the number of input gates or external input signals directly connected to the respective input pins of G _I and G _J. N _IG (G _I , G _J ) is the sum of the number of gate pairs recognized as corresponding gates in each of the input gates of G _I and G _J and the number of common signals among the external input signals. Represents

(4) Output gate sharing ratio: R _COG (G _I , G _J ) Here, N _OG (G _I ) and N _OG (G _J ) represent the number of output gates or external output signals directly connected to the output pins of G _I and G _J , respectively. N _COG (G _I , G _J ) is the sum of the number of gate pairs recognized as corresponding gates among the output gates of G _I and G _J and the number of common signals among external output signals. Represents

The processing procedure of this step 502 is slightly different depending on the size relationship between the number of external input signals and the number of external output signals of the new intermediate gate logic. Procedure 6 when the number of external input signals is larger
Shown in the figure. Hereinafter, the processing procedure of this step 502 will be sequentially described based on the processing flow of FIG.

Steps 601, 602: The corresponding gate is recognized by this step R _CIS (G _I , G _J ).

(1) Initialize the collision gate table.

(2) When each gate pair (G _I , G _J ) of G _I (I = 1, ..., N _I ) and G _J (J = 1, ..., N _J ) satisfies the following two conditions, R _CIS (G
_I , G _J ), and if R _CIS (G _I , G _J )> 0, triple
Create (R _CIS (G _I , G _J ), G _I , G _J ) and register it to the stack. In addition, this triple and various trips appearing in the following explanation
In le, the gate identification symbols (G _I , G
_(J, etc.) is actually a code that can be ranked, such as a number or an alphabet, and in the description of the present embodiment, reference numerals in the drawings are used for convenience.

(A) G _I and G _J have the same gate type.

(B) Neither G _I nor G _J is recognized as a corresponding gate.

(3) If the number of triples on the stack is 0, the corresponding gate recognition step 502 ends.

(4) Otherwise, select the triples on the stack, the first key is R _CIS (G _I , G _J ), the second key is G _I , and the third key is G _J. , And the second and third keys are sorted in ascending order.

(5) Perform the following processing in order from the triple with the largest R _CIS (G _I , G _J ). Now, the trip target of the c-th sort order
Le is represented by ([R _CIS (G _I , G _J )] _C [G _I ] _C , [G _J ] _C ), and subsequent triples are sequentially expressed as ([R _CIS (G _I , G _J )] _{C + 1.} ,
[G _I ] _{C + 1} , [G _J ] _{C + 1} ), ...

(A) If either [G _I ] _C or [G _J ] _C is recognized as a corresponding gate or a collision gate, the process is skipped.

(B) [G _I ] _C and [G _J ] if the following logical expressions hold:
Correlate _C.

(([R _CIS (G _I , G _J )) _C = [R _CIS (G _I , G _J )] _{C + 1} ) ∧ (([G _I ] _C = [G _I ] _{C + 1} ) ∨ ([ G _J ] _C = [G _J ] _{C + 1} ))) = 0 Here, “0” on the right side represents “false”, that is, failure, and therefore, this expression is “triple to be processed and next order The external input signal sharing ratio is the same between triples, and
The condition that at least one of the gate of the old gate logic and the gate of the intermediate gate logic matches is not satisfied, in other words, whether the external input signal sharing ratio is different between the triple to be processed and the next triple. , Or the gate of the old gate logic and the gate of the intermediate gate logic do not match. A logical formula similar to this that appears afterwards,
This should be interpreted accordingly.

(C) When the above logical expression is not satisfied, this means that one or a plurality of gates on one gate logic side apparently correspond to a plurality of gates on the other gate logic side. This state is called a gate collision, and the gate related to this is called a collision gate. Specifically, ((R _CIS
(G _I, G _{J)] C,} G _I, all G _I of triple serving as [G _{J] C)}
Becomes the collision gate on the old gate logic side, and ((R _CIS (G _I , G
_J ) _C , [G _J ] _C , G _J ) All G _{J of} triples are collision gates on the new intermediate gate logic side. These collision gate groups are registered in the collision gate table with the minimum value of the level (the number of gate stages) starting from the external output signal of each collision gate on the new intermediate gate logic side in the collision gate group as a key.

Steps 603 and 604: The corresponding gate is recognized by this step R _COG (G _I , G _J ).

(1) If the number of entries in the collision gate table is 0,
This step ends.

(2) Otherwise, the collision gate groups GR _K (K = 1, ...,) in ascending order of the key level (minimum level).
Taken out N _K), performs the following processing for each GR _K.

(A) The collision gate recognized as the corresponding gate in GR _K is removed.

(B) As a result, if all the collision gates are eliminated, the processing is skipped.

(C) If one gate is left on the old gate logic side and one on the new intermediate gate logic side, both gates are associated and the processing is skipped.

(D) In cases other than the above (b) and (c), the collision gate CG _KI (I = 1, ..., N _KI ) on the old gate logic side and the collision gate CG _KJ (I = 1 on the intermediate gate logic side) , ..., N _KJ ), the following processing is performed.

(I) Re-register the remaining collision gate groups in the collision gate table.

(Ii) For each collision gate pair (CG _KI , CG _KJ ) R _COG (CG
_KI , CG _KJ ) is calculated and triple (R _COG (CG _KI , CG _KJ ), CG _KI ,
CG _KJ ) and create a stack.

(Iii) The triple on the stack, the first key is R _COG (CG _KI ,
CG _KJ ), the second key is CG _KI , and the third key is CG _KJ
The keys are sorted in descending order, and the second and third keys are sorted in ascending order.

(Iv) The next triple processing is performed in order from the triple having the largest R _COG (CG _KI , CG _KJ ). Now, the sort order is c-th trip
It is represented by le ([R _COG (CG _KI , CG _KJ ) _C , [CG _KI ] _C , [CG _KJ ] _C ), and subsequent triples are in order ((R _COG (CG _KI , CG _KJ ) _{C + 1} ,
It is represented by [CG _KI ] _{C + 1} , [CG _KJ ] _{C + 1} ), .... As long as the following logical expression is established, [CG _KI ] _C and [CG _KJ ] _C are associated with each other. If this logical expression is no longer satisfied, the process of associating ends.

(([R _COG (CG _KI , CG _KJ ) _C = [R _COG (CG _KI , C
G _KJ ) _{C + 1} ) ∧ (([CG _KI ] _C ＝ [CG _KI ] _{C + 1} ) ∨ ([CG _KJ ) _C ＝ [CG
_KJ ] _{C + 1} ))) = 0 This expression is basically the triple to be processed and the next triple.
Indicates that the output zate sharing ratios are different, or that the collision gate of the old gate logic and the collision gate of the intermediate gate logic do not match.

Steps 605 and 606: This step recognizes the corresponding gate by R _CIG (G _I , G _J ). This step is step 603,604
_Is basically the same as R _COG (CG _I , CG _J )
(G _I , G _J ), and the extraction order of the collision gate groups is changed from the smallest key level to the largest key level.

Step 607, 608: Through the series of processing from Step 603 to Step 606, if at least one corresponding gate is recognizable, this step ends. Otherwise, forcibly associate the collision gates with R _COG (CG _I , CG _J ) as follows.

(1) Collision gate group GR with the highest key level
_Take out _K.

(2) Collision gate CG _KI (I = 1, ...,
N _KI ) and new intermediate gate Logic side collision gate CG _KJ (I = 1,
, N _KJ ), the following processing is performed.

(A) The collision gate group is re-registered in the collision gate table.

(B) For each collision gate pair (CG _KI , CG _KJ ) R _COG (CG
_KI , CG _KJ ) is calculated and triple (R _COG (CG _KI , CG _KJ ), CG _KI ,
CG _KJ ) and create a stack.

(C) The triple on the stack, the first key is R _COG (CG _KI , C
G _KJ ), 2nd key is CG _KI , 3rd key is CG _KJ
The keys are sorted in ascending order, and the second and third keys are sorted in ascending order.

(D) C of the first triple with the largest R _COG (CG _KI , CG _KJ )
Forcibly associate G _KI and CG _KJ .

When the number of external output signals is larger than the number of external input signals, the procedure of R _CIS (G _I ,
G _J ) is replaced with R _COS (G _I , G _J ) and R at steps 604 and 608
Replace _COG (G _I , G _J ) with R _CIG (G _I , G _J ), and replace the collision gate group with the highest key level at the beginning of the collision gate forcing process in step 608. Take out the collision gate group with the lowest key level, and then at step 606, R _CIG (G _I , G _J ) to R _COG
It is equivalent to the one replaced with (G _I , G _J ).

In the following, using the two gate logics of FIG. 4 and FIG. 5 as an example,
The above processing procedure will be specifically described. Gate 301 of FIG. 4,
Let 302, ..., 307 be G _I, and replace the gates 401, 402, ..., 407 in FIG.
G _J. In FIG. 5, since the number of external input signals is six, which is larger than the number of external output signals, three, the corresponding gate is recognized by R _CIS (G _I , G _J ). First, an example of calculating R _CIS (G _I , G _J ) is shown. As an example, if G _I = 304 and G _J = 404, then R
_CIS (304,404) is N _IS (304) = 6 (D−N, C−N, A−N,
B−N, E−N, F−N), and N _IS (404) = 6 (A−N, B−
N, DX-N, E-N, F-N, G-N), so N _CIS (304,40
4) = 4 (A-N, B-N, E-N, F-N), and as a result,
R _CIS (304,404) is Becomes R of each gate pair calculated in this way
The calculation result of _CIS (G _I , G _J ) is shown in FIG. Next, FIG. 8 shows the results of sorting triples (R _CIS (G _I , G _J ), G _I , G _J ) for each gate pair. At this time, the triple processing is as follows.

(1) triple1: The gate 301 and the gate 401 are associated with each other.

(2) triple2: The gate 302 and the gate 402 are associated with each other.

(3) triple 3 to 5: Since the gate 302 is recognized as a corresponding gate, skip.

(4) triples 6 to 9: Since the gates 304, 305, 403, and 404 become collision gates, these are registered in the collision gate table.
Here, the minimum level of the collision gate group (the key level) is 2.

(5) triple10: Since the gate 401 is recognized as the corresponding gate in (1) above, skip.

(6) triples 11 to 13: Since the gates 307, 405, 406, and 407 become collision gates, these are registered in the collision gate table. Here, the minimum value of the level of this collision gate group (the key level) is 1.

(7) triples 14 to 17: Gate 301 corresponds to gate 30, gate 30
Since 7 is recognized as a collision gate, skip it.

FIG. 9 shows the collision gate table after the above triple processing.

Next, the corresponding gate is recognized by R _COS (G _I , G _J ).
Take out the collision gate groups in ascending order of key level. The constituent gates of the first collision gate group are the gates 307, 405, 406, 407 of the group having the key level (minimum level) of 1. First, R _COG (CG _KI , C
An example of calculating G _KJ ) is shown below. If CG _KI = 307 and CG _KJ = 406, then R _COG (307,406) is N _CG (307) = 1 (YP), N
_{Since OG} (406) = 1 (Y-P), N _COG (307,406)
= 1 (Y-P), resulting in R _COG (307,406)
Is Becomes Figure 10 shows the calculation results of R _COG (CG _KI , CG _KJ ) of each collision gate pair, and tr created for each collision gate pair
Figure 11 shows the sorted results of iple (R _COG (CG _KI , CG _KJ ), CG _KI , CG _KJ ). At this time, the triple processing is as follows.

(1) triple1: The gate 307 and the gate 406 are associated with each other.

(2) triple2,3: Since the gate 307 is recognized as a corresponding gate, skip.

The constituent gates of the second collision gate group are the gates 304, 305, 403, 404 of the group whose key level (minimum level) is 2. R _COG (C
The calculation result of G _KI , CG _KJ ) is shown in FIG. 12, and the triple sorting result is shown in FIG. At this time, the triple processing is as follows.

(1) triple1: The gate 305 and the gate 404 are associated with each other.

(2) triple2,3: Since the gates 404 and 305 are recognized as corresponding gates respectively, skip.

(3) triple 4: The gate 304 and the gate 403 are associated with each other.

With the above processing, recognition of all corresponding gates is completed,
Step 502 ends.

Step 503: This step recognizes a corresponding sub-gate for each composite gate recognized as a corresponding gate. The processing procedure of this step will be sequentially described based on the processing flow of FIG.

Step 1401: This step recognizes the corresponding sub-gate by R _CIG (G _I , G _J ).

(1) Old gate logic side sub-gate SG _I (I = 1, ...,
N _SI ) and new intermediate gate Logic side sub gate SG _J (J = 1,
, N _SJ ; N _SI ＝ N _SJ ), R _CIG (SG _I , SG _J ) is calculated for each sub-gate pair (SG _I , SG _J ), and triple (R _CIG (SG _I , S _J
Create G _J ), SG _I , SG _J ), and stack it in the stack.

(2) The triple on the stack, the first key is R _CIG (SG _I ,
SG _J ), the second key is SG _I , and the third key is SG _J , and the first key is sorted in descending order, and the second and third keys are sorted in descending order.

(3) Perform the following processing in order from the triple with the largest R _CIG (SG _I , SG _J ). Now, the tr that is the processing target whose sort order is c
iple is represented by ([R _CIG (SG _I , SG _J )] _C , [SG _I ] _C , [SG _J ] _C , and subsequent triples are sequentially represented by ([R _CIG (SG _I , S _J
G _J )] _{C + 1} , [SG _I ] _{C + 1} , [SG _J ] _{C + 1} ).

(A) If either [SG _I ] _C or [SG _J ] _C is recognized as the corresponding sub-gate, the process is skipped.

(B) If the following logical expression is established, [SG _I ] _C and [SG _J ] _C are associated with each other.

(([R _CIG (SG _I , SG _J )] _C = [R _CIG (SG _I , SG _J )] _{C + 1} ) ∧ (([[SG _I ] _C = [SG _I ] _{C + 1} ) ∨ ( [SG _J ] _C = [SG _J ] _{C + 1} ))) = 0 This expression is, in effect, the triple to be processed and the next triple.
Indicates that the input gate sharing ratio is different, or that the sub-gate of the old gate logic and the sub-gate of the intermediate gate logic do not match.

(C) When the above logical expression is not satisfied, the collision subgate is taken out.

Steps 1402, 1403: If there are no collision subgates, the corresponding subgate recognition step 503 ends. Otherwise, the corresponding sub-gate is recognized by R _COG (G _I , G _J ).

(1) Collision sub-gate on the old gate logic side CSG _I (I = 1,
…, N _CSI ) and new intermediate gate Logic side collision Subgate CSG _J
Each collision subgate pair (CSG _I , CSG _J ) of (J = 1, ..., N _CSJ )
R _COG (CSG _I , CSG _J ), and triple (R _COG
Create (CSG _I , CSG _J ), CSG _I , CSG _J ) and stack.

(2) The triple on the stack, the first key is R _COG (CSG _I , C
SG _J ), the second key is CSG _I , and the third key is CSG _J
The keys are sorted in ascending order, and the second and third keys are sorted in ascending order.

(3) Perform the following processing in order from the triple with the largest R _COG (CSG _I , CSG _J ). Now, the sort target is the c-th processing target
triple ((R _COG (CSG _I , CSG _J ) _C , [CSG _I ] _C , [CSG _J ])
_C ) and the subsequent triples in order ((R _COG (CSG _I , CSG
_J ) _{C + 1} , [CSG _I ] _{C + 1} , [CSG _J ] _{C + 1} ), ...

(A) If either [CSG _I ] _C or [CSG _J ] _C is recognized as a corresponding sub-gate, the process is skipped.

(B) If the following logical expression is established, [CSG _I ] _C and [CSG _J ] _C are associated with each other.

(([R _COG (CSG _I , CSG _J )) _C = [R _COG (CSG _I , CSG _J )] _{C + 1} ) ∧ (([[CSG _I ] _C = [CSG _I ] _{C + 1} ) ∨ ( [CSG _J ] _C = [CSG _J ] _{C + 1} ))) = 0 This expression is, in effect, the triple to be processed and the next triple.
The output gate sharing rate is different, or the sub-gate of the old gate logic and the conflicting sub-gate of the intermediate gate logic do not match.

(C) When the above logical expression is not satisfied, the collision subgate is taken out.

Steps 1404 and 1405: If there is no collision subgate, the recognition step 503 of the corresponding subgate ends. Otherwise, R _CIG (G _I , G _J ) will be used for compulsory mapping of collision subgates.

(1) Collision sub-gate on the old gate logic side CSG _I (I = 1,
…, N _CSI ) and new intermediate gate Logic side collision Subgate CSG _J
Each collision subgate pair (CSG _I , CSG _J ) of (J = 1, ..., N _CSJ )
For calculates the _{R CIG (CSG I, CSG J} ), triple (R CIG
Create (CSG _I , CSG _J ), CSG _I , CSG _J ) and stack.

(2) Triple on the stack, the first key is R _CIG (CSG _I , C
SG _J ), the second key is CSG _I , and the third key is CSG _J
The keys are sorted in ascending order, and the second and third keys are sorted in ascending order.

(3) Forcibly associate CSG _I and CSG _J in order from the top triple with the largest R _CIG (CSG _I , CSG _J ).

In the following, using the two gate logics of FIG. 4 and FIG. 5 as an example,
The above processing procedure will be specifically described. In these figures, gate 304 and gate 403 and gate 305 and gate 404
Each gate pair is a corresponding composite gate pair to be processed.
R _CIG (SG _I , SG _I of each subgate pair of gate 304 and gate 403
The calculation results of _J) shown in FIG. 15 shows triple created for each sub-gate pair _{(R CIG (SG I, SG} J), SG I, the sorting result of SG _J) in FIG. 16. At this time, the triple processing is as follows.

(1) triple1: subgate 304-B and subgate 403-A
Correspond to.

(2) triple2: Since subgate 403-A is recognized as a corresponding subgate, it is skipped.

(3) triple3: subgate 304-A and subgate 403-B
Correspond to.

(4) triple4: Since the subgate 304-B is recognized as the corresponding subgate, it is skipped.

Similarly, in the case of the gate 305 and the gate 404, the sub gate 305-A and the sub gate 404-A are associated with each other,
Subgate 305-B and subgate 404-B are associated with each other.

Step 504: This step recognizes the corresponding pin for each corresponding gate (or each corresponding subgate when the corresponding gate is a composite gate). The corresponding pin is recognized for each net pair according to the following rules.

(1) The source side of the net is a replaceable pin of the corresponding gate (sub-gate), and the sink side of the net is a replaceable pin of the corresponding gate (sub-gate). For example, in the net 333 and the net 433, the output pin pair of the 9th pin of the gate 302 and the 2nd pin of the gate 402 are corresponding pins, and the 3rd pin of the gate 305 and the input pin pair of 3rd pin of the gate 404 are corresponding. Become a pin.

(2) The source side of the net is a replaceable pin of the corresponding gate (sub-gate), and the sink side of the net is the same external output signal. For example, in net 322 and net 422, the output pin pair of pin 12 of gate 307 and pin 2 of gate 406 is a corresponding pin.

(3) The source side of the net is the same external input signal, and the sink side of the net is the exchangeable pin of the corresponding gate (sub-gate). For example, in the net 312 and the net 411, the input pin pair of the fourth pin of the gate 301 and the third pin of the gate 401 are corresponding pins.

Step 505: This step recognizes the extended correspondence of the non-corresponding gate structure when either of the following two conditions is satisfied.

(1) The source side of the net is a replaceable pin of the corresponding gate (sub-gate), but there is an input pin pair that is not recognized as the corresponding input pin.

(2) Although the sink side of the net is the same external output signal,
There is the same external output signal pair whose source side is not recognized as the corresponding output pin.

The processing procedure of this step will be sequentially described based on the processing flow shown in FIG.

Step 1701: This step performs a variable consistency check.

(1) Corresponding gate (sub-gate) starting from each input pin (external output signal) of the input pin pair (same external output signal pair)
Perform fan-in trace to the output pin or external input signal.

(2) Between the old gate logic side and the new intermediate gate logic side, the output pin of the corresponding gate (sub-gate) traced in (1) above and the external input signal are associated with each other, and one of the following conditions is satisfied. If there are output pin pairs or external input signal pairs to be filled, common variable names X1, X2, ... Are given to the output pin pairs or external input signal pairs.

(A) Corresponding gate (sub-gate) output pin pair with pin interchangeability (b) Same external input signal pair Steps 1702, 1703: Between the old gate logic side and the new intermediate gate logic side, the above If all of the output pins of the corresponding gate (sub-gate) traced in (1) and the external input signal can be associated with each other, the logical equivalence check is performed.

(1) With respect to each input pin (external output signal) that is the starting point of fan-in trace and each partial logic cut out by a common variable, the output logical value of each input pin (external output signal) is determined using these common variables. Create a Boolean expression to represent.

(2) Check the logical equivalence of the pair of Boolean expressions by using the method equivalent to the above-mentioned document (1) or (2).

Steps 1704 and 1705: If the logics of the Boolean expressions are equivalent, the gate kind matching check is performed.

(1) This check is performed in two steps, that is, the gate on the most output side and all the remaining gates. The check contents are
A gate type that represents physical characteristics such as gate power and speed.

(2) Check whether the gate pair on the most output side has the same gate type.

(3) All the remaining gates on the old gate logic side and the new intermediate gate logic side are of the same gate type.

(4) In the above (2) and (3), when there is no gate to be compared, it is assumed that the same gate type is used.

Steps 1706 to 1708: If the gate types match, the partial logic on the old gate logic side is selected, and if any of the above three types of check results do not match, the partial logic on the new intermediate gate logic side is selected. To do.

In the following, using the two gate logics of FIG. 4 and FIG. 5 as an example,
The above processing procedure will be specifically described. In these figures, the external output signal pair with the external output signal name XP is to be processed. In FIG. 4, when fan-in tracing is performed from XP, pin 19 of the gate 304 becomes the output pin of the corresponding gate (sub-gate). Also, in FIG.
Performing a fan-in trace from XP, gate 403
No. 2 pin becomes a variable. At this time, since the gate 304 and the gate 403 are a corresponding gate pair and the pin 19 and the pin 2 are pin-exchangeable output pin pairs, this output pin pair becomes a common variable and is named X1. Next, if you generate an XP boolean expression using this common variable,
X1 and the logic is equivalent. Finally, the gate type check is performed on the gate 306 and the gate 405 to match the gate types. Therefore, since all three check results match, the partial logic on the old gate logic side in FIG. 4 is selected. The following three types of information are obtained by the processing from step 502 to step 505 described above, and these pieces of information are registered in the net table created in step 501 described above.

(1) Correspondence information: This is the correspondence gate recognized in step 502 and the correspondence sub-gate recognized in step 503.
It is the information consisting of the corresponding gate and the corresponding internal net (the net connecting the corresponding output pin of a certain corresponding gate and the corresponding input pin of another corresponding gate) obtained from the information of the corresponding pin recognized in step 504, and the old gate logic. The correspondence information on the side is registered in the net table of the old gate logic, and the correspondence information on the side of the new intermediate gate logic is registered in the net table of the new intermediate gate logic.

(2) Selection information: This is information consisting of the gate that constitutes the partial logic selected in step 505 and the internal net (the net that connects the output pin of one gate and the input pin of another gate), and the old gate logic side. When the partial logic of is selected, the selection information is registered in the net table of the old gate logic, and when the partial logic of the new intermediate gate logic is selected, the selection information is changed to the net of the new intermediate gate logic. Registered in the table. In the following, the gate and the internal net belonging to the selection information will be referred to as the selection gate and the selected internal net, respectively.

(3) Additional information: In the new intermediate gate logic,
This information is composed of all the remaining gates except the corresponding gates and select gates, and all the remaining internal nets except the corresponding internal nets and the selected internal nets, and is registered in the net table of the new intermediate gate logic. Hereinafter, the gate and the internal net which belong to the additional information are referred to as an additional gate and an additional internal net, respectively.

Step 506: This step pre-edits the new gate logic.

(1) Gate ID: A gate ID is given to each gate. For example, K.01 described below the gate 401 is the gate ID. In this step, a new gate ID is given to each select gate and each additional gate on the new intermediate gate logic side so as not to overlap with the gate ID of the corresponding gate and select gate on the old gate logic side.

(2) Internal signal name: An internal signal name is given to each internal net. In this step, a new internal signal name is assigned to each selected internal net and each additional internal net on the new intermediate gate logic side so that they do not overlap with the internal signal names on the corresponding internal net and selected internal net on the old gate logic side. . However, when a fan-out net is newly added to the corresponding output pin, the original internal signal name on the old gate logic side is given to the internal net.

Step 507: This step generates a new gate logic of the IC operation type based on the correspondence information on the net table of the old gate logic and the new intermediate gate logic, the selection information and the additional information. A new gate logic generated from the two gate logics of FIGS. 4 and 5 is shown in FIG. Note that in FIG. 18, in order to facilitate understanding of the processing procedure, step 506
Note that the processing results of and 507 are omitted.

In the above gate logic automatic updating method, it is also preferable to perform the following in order to improve the storage ratio of the mounting information and the manual logic optimization information.

(1) Identification of internal parameter signal: There are three types of signals: an external input / output signal, an internal parameter signal, and an internal signal. The internal parameter signal is X corresponding to a local variable when the functional logic is described as X = A · B, Y = X + C. Like the external input / output signal, the internal parameter signal is a unique signal designated by the logic designer, and is treated the same as the external input / output signal.

(2) Equivalent signal group signal introduction: When the external input / output signal and the internal parameter signal are changed, when the same equivalent signal group number is given to the signal name before change and the signal name after change, these different signal names Consider signal pairs with the same signal.

[Advantages of the Invention] According to the present invention, when the gate logic is automatically updated according to the change of the functional logic in the packaging design phase, the packaging information and the human optimization information in the unneeded portion of the old gate logic are updated. Saved automatically in gate logic. Therefore, the provision of mounting information and the manual optimization need only be performed for the part where the substantial change is made, and as a result, the man-hour of the logical design change and the resulting improvement in the logical quality are significantly effective. There is.

[Brief description of drawings]

FIG. 1 is a flow chart of an example of a logic automatic update process according to the present invention, FIG. 2 is a schematic diagram of the whole process of automatic generation and automatic update of gate logic, and FIG. 3 is an example of an intermediate gate logic before logic change. FIG. 4 is a gate logic diagram showing an old gate logic obtained by performing an implementation design process on the intermediate gate logic of FIG. 3, and FIG. 5 is a basis of the gate logic of FIG. A gate logic diagram showing a new intermediate gate logic automatically generated after partially changing the functional logic, FIG. 6 is a flow chart of corresponding gate recognition processing, and FIGS. 7 to 13 are flow charts of the processing of FIG. FIG. 14 shows an example of the result, FIG. 14 is a flow chart of the corresponding sub-gate recognition process, FIGS. 15 and 16 are diagrams showing an example of the result of the process of FIG. 14, and FIG. Processing flow chart, Fig. 18 shows old gate logic and Fig. 5 in Fig. 4. A gate logic diagram showing a new gate logic generated from the new intermediate gate logic. 100 …… Function logic input system, 101 …… Automatic logic generation system, 113 …… Old gate logic file with mounting information / manual optimization information, 115 …… New intermediate gate logic file after functional logic change, 104 …… Logic Automatic update system, 116…
… New gate logic file that stores old gate logic implementation information / manual optimization information that need not be changed, 502-505 ……
Partial logic correspondence recognition step, 506, 507 ... Gate logic merge step.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Masato Morita, 1 Horiyamashita, Hinoyama, Hadano, Kanagawa Pref., Kanagawa Plant, Hitate Manufacturing Co., Ltd. (72) Yoshinori Sakata, 1 Horiyamashita, Hadano, Kanagawa Factory Kanagawa Plant (72) Inventor Yoji Tsuchiya 1 Horiyamashita, Hadano City, Kanagawa Pref.Hitate Manufacturing Co., Ltd. Kanagawa Factory (72) Inventor Mitsuhiro Hikosaka 1479, Kamisuimotocho, Kodaira, Tokyo Hitachi My Cro Computer Computer Engineering Co., Ltd. In-house (72) Inventor Junji Echige 6-81 Onoe-cho, Naka-ku, Yokohama-shi, Kanagawa Hitachi Software Engineering Co., Ltd. In-house (72) Inventor Keiho Akiyama 6-81, Onoe-machi, Naka-ku, Yokohama, Kanagawa Hitachi Software Engineering Stock Company In-house (72) Inventor Hisashi Takashige Kawasaki City, Kanagawa Prefecture Aso District Ozenji 1099 address Co., Ltd. Systems Development in the Institute

Claims (7)

[Claims] 1. A computer which generates an intermediate gate logic which is a gate logic which does not include mounting information according to a given functional logic and which performs a designing process on the intermediate gate logic to obtain a gate logic including mounting information. In the automatic logic design system using, when a part of the functional logic in which the old gate logic that has undergone the implementation design process already exists is changed,
A step between the old gate logic and the new intermediate gate logic to generate new gate logic for the modified functional logic, in accordance with the modified functional logic, to generate new intermediate gate logic. Corresponding recognition step for checking the logic correspondence and identifying the common part logic and non-common part logic of both gate logics, the part of the old gate logic corresponding to the common part logic and the non-common part logic And a merge step for merging parts of a new intermediate gate logic to generate a new gate logic in which the old gate logic subjected to the packaging design process is stored for the common partial logic. 2. The correspondence recognition step according to claim 1, wherein the correspondence recognition step is an external input signal sharing rate or an external output signal sharing rate according to the magnitude relationship between the number of external input signals and the number of external output signals of the new intermediate gate logic. A gate logic automatic updating method including a step for checking the correspondence between gates by using as an index. 3. The correspondence recognition step according to claim 2, further comprising: input gate sharing ratio and output gate sharing ratio for a gate group whose correspondence relationship is not uniquely determined by the signal sharing ratio. A gate logic automatic updating method including a step of checking a correspondence relationship using at least one as an index. 4. The correspondence recognition step according to claim 3, further comprising: for a gate pair associated with any of the steps included therein, they are a plurality of sub-gates. In case,
A gate logic automatic updating method including a step of determining a correspondence relationship between sub-gates using at least one of an input gate sharing rate and an output gate sharing rate as an index. 5. A gate logic automatic update according to claim 4, wherein the correspondence recognition step further includes a step of associating an input / output pin with respect to a corresponding gate or sub-gate based on net information and pin interchangeability. Method. 6. The correspondence recognition step according to claim 5, further comprising: a non-corresponding partial logic connected to a non-corresponding input / output pin of a corresponding gate or sub-gate.
A method for automatically updating a gate logic including a step for checking an expanded correspondence between non-corresponding partial logics based on the logic function and a gate type representing a physical characteristic. 7. The merge step according to any one of claims 1 to 6, wherein the merging step is performed for each gate and each internal net included in the non-common partial logic selected from the new intermediate gate logic. A gate logic automatic updating method including a step of giving an identification name which does not overlap with an identification name of a gate and an internal net in a common partial logic selected from the old gate logic.