JPH11511871A - スーパースカラ型プロセサにおいて命令処理を制御するためタグを割り当てるシステム及び方法 - Google Patents
スーパースカラ型プロセサにおいて命令処理を制御するためタグを割り当てるシステム及び方法Info
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- JPH11511871A JPH11511871A JP7525914A JP52591495A JPH11511871A JP H11511871 A JPH11511871 A JP H11511871A JP 7525914 A JP7525914 A JP 7525914A JP 52591495 A JP52591495 A JP 52591495A JP H11511871 A JPH11511871 A JP H11511871A
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
- G06F9/3856—Reordering of instructions, e.g. using queues or age tags
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
- G06F9/3858—Result writeback, i.e. updating the architectural state or memory
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
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- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Advance Control (AREA)
- Executing Machine-Instructions (AREA)
Abstract
Description
Claims (1)
- 【特許請求の範囲】 1. 命令のソースから命令情報を受け取りレジスタ・ファイルに格納する可変 アドバンス命令ウインドウを実現する方法で、 レジスタ・ファイルに関連する命令情報を格納できる新規命令がいくつあ るか決定するステップと、 特定の命令のタグはその命令に関連する情報がレジスタ・ファイルに存在 している限り変わることがないように、新規命令毎にタグを割り当てるステップ と、 各命令に関する情報をレジスタ・ファイル内のその命令に割り当てられた タグで指定された場所に格納し、前記レジスタ・ファイルは複数のレジスタと、 複数の読み出しアドレス・ポート及び複数の読み出しデータポートとを備える、 情報格納のステップと、 キューのスロット毎にタグを1個づつ格納し、前記キューは所定の時点で レジスタ・ファイルに命令情報を入れられる上限の命令数に等しいスロット数を 有し、タグは各命令に対する命令情報がレジスタ・ファイルに格納されるのと同 じ順序でキューに入られ、前記キューはさらにスロット毎にスロット出力を有し 、各スロット出力によって対応するスロットのタグをアクセスできるようになる 、タグ格納のステップと、 前記スロットの1個を対応するスロット出力を介してアクセスするステッ プと、 そのスロットに格納されたタグをレジスタ・ファイルの前記複数の読み出 しアドレス・ポートのうちの特定の1個に引き渡してレジスタ・ファイルがその タグに対応する命令に関連する情報を前記読み出しアドレス・ポートに対応する 特定の読み出しデータポートから出力するようにするステップと、 を含むことを特徴とする方法。 2. さらにレジスタ・ファイルに入れられるべき新規命令の数と同じスロット 数だけ前記キューをアドバンスさせるステップを有することを 特徴とする請求項1に記載の方法。 3. 情報格納の前記ステップがデコードされた命令情報を格納してなることを 特徴とする請求項1に記載の方法。 4. 情報格納の前記ステップが命令のメモリ・アドレスを格納してなることを 特徴とする請求項1に記載の方法。 5. デコードされた命令情報を格納する前記ステップが機能ユニットの要件を 指定する情報を格納してなることを特徴とする請求項3に記載の方法。 6. デコードされた命令情報を格納する前記ステップが実行されるオペレーシ ョンのタイプを指定する情報を格納してなることを特徴とする請求項3に記載の 方法。 7. デコードされた命令情報を格納する前記ステップが命令結果を格納する記 憶場所を指定する情報を格納してなることを特徴とする請求項3に記載の方法。 8. デコードされた命令情報を格納する前記ステップが命令オペランドを格納 する記憶場所を指定する情報を格納してなることを特徴とする請求項3に記載の 方法。 9. デコードされた命令情報を格納する前記ステップが命令のターゲット・ア ドレスを指定する情報を格納してなることを特徴とする請求項3に記載の方法。 10. デコードされた命令情報を格納する前記ステップが命令によって指定した オペレーションで用いられるイミディエト・データを指定する 情報を格納してなることを特徴とする請求項3に記載の方法。 11. デコードされた命令情報を格納する前記ステップが第2のレジスタ・ファ イルの機能ユニット要件を指定する情報を格納してなることを特徴とする請求項 3に記載の方法。 12. デコードされた命令情報を格納する前記ステップが第2のレジスタ・ファ イルで実行されるオペレーションのタイプを指定する情報を格納してなることを 特徴とする請求項3に記載の方法。 13. デコードされた命令情報を格納する前記ステップ命令結果を格納する第2 のレジスタ・ファイルの記憶場所を指定する情報を格納してなることを特徴とす る請求項3に記載の方法。 14. デコードされた命令情報を格納する前記ステップが命令オペランドが格納 される第2のレジスタ・ファイルの記憶場所を指定する情報を格納してなること を特徴とする請求項3に記載の方法。 15. デコードされた命令情報を格納する前記ステップが第2のレジスタ・ファ イル内の制御フロー命令のターゲット・アドレスを指定する情報を格納してなる ことを特徴とする請求項3に記載の方法。 16. デコードされた命令情報を格納する前記ステップが命令によって指定した オペレーションで用いられる第2のレジスタ・ファイルのイミディエト・データ を指定する情報を格納してなることを特徴とする請求項3に記載の方法。 17. 前記キューの中にタグ毎の有効ビットを格納するステップをさらに有し、 有効ビットと対応しているタグに該当する命令が有効ならば有効ビットが設定さ れることを特徴とする請求項3に記載の方法。 18. 情報を格納する前記ステップが命令を格納してなることを特徴とする請求 項1に記載の方法。 19. 命令のソースから命令情報を受け取りレジスタ・ファイルに格納する可変 アドバンス命令ウインドウを実現するシステムで、 レジスタ・ファイルに関連命令情報を入れられる新規命令がいくつあるか 決定し、特定の命令に関する情報がレジスタ・ファイルにある限りその命令のタ グが変わることがないように新規命令毎にタグを割り当てる制御手段と、 前記制御手段に接続され、各命令に関する情報を前記レジスタ・ファイル 内の1つの場所に格納し、前記場所はその命令に割り当てられたタグで指定され 、前記レジスタ・ファイルは前記場所を形成する複数からなるレジスタと、複数 の読み出しデータポート及び複数の読み出しアドレス・ポートを有し、読み出し アドレス・ポートには読み出しデータポートが対応している、レジスタ・ファイ ルと、 前記制御手段及び前記レジスタ・ファイルに接続され、複数のスロットを 有し、前記スロットには各々に前記レジスタ・ファイル内の場所のアドレスに対 応する固有のタグが収めれ、さらにスロット毎にスロット出力を有し、各スロッ ト出力によって対応するスロットにあるタグをアクセスできるようになる、リサ イクル型キューを備え、 スロットに格納されたタグをレジスタ・ファイルの前記複数の読み出しア ドレス・ポートの特定の1個に引き渡してレジスタ・ファイルがそのタグに対応 するレジスタ・ファイルの場所に格納された命令情報を対応する読み出しデータ ポートから出力するようにすることを特徴とするシステム。 20. 前記制御手段がレジスタ・ファイルに新たに入れられた命令数と同じスロ ット数だけ前記タグを前記リサイクル型キューの中でアドバンスさせることを特 徴とする請求項9に記載のシステム。 21. 命令のソースから命令情報を受け取りメモリ素子に格納する可変アドバン ス命令ウインドウを実現する方法で、 前記メモリ素子に入れる関連情報をもつ新規命令毎にタグを割り当て、各 タグは前記メモリ素子の固有のアドレスに相当する値を有する、タグ割り当ての ステップと、 前記メモリ素子内のその対応するタグで識別されたアドレスに各命令に関 する情報を格納するステップと、 リサイクル型キューに入るタグの順序が前記メモリ素子に入る命令情報の 順序に一致し、リサイクル型キューのスロットのタグの順序が前記メモリ素子か ら読み出される命令情報の正しい順序を識別するように、リサイクル型キューの 最上部のスロットにタグを入れるステップと、 前記メモリ素子から出ていく実行済みの命令に対応したタグをリサイクル し、前記メモリ素子に入る新規命令に前記リサイクルされたタグを割り当てるス テップと、 を含むことを特徴とする方法。 22. 新規命令をいくつメモリ素子に入れられるか決定するステップをさらに含 むことを特徴とする請求項21に記載の方法。 23. さらにタグは、前記メモリ素子に入れる命令にタグが既に割り当てられて いるかどうか示すバリディティ・ビットを有することを特徴とする請求項22に記 載の方法。 24. 命令のソースから命令情報を受け取りメモリ素子に格納する可変アドバン ス命令ウインドウを実現するシステムで、 複数のスロットを有するリサイクル型キューと、 タグによって識別されるアドレスに命令に関する情報を格納し、複数の読 み出しアドレス・ポートと複数の読み出しデータポートを有するメモリ素子と、 前記メモリ素子に入れる関連情報をもつ新規命令毎にタグを割り 当て、タグは各々前記メモリ素子の固有なアドレスに該当する値を有する、タグ 割り当て手段と、 前記リサイクル型キューのスロットに入るタグの順序が命令情報が前記メ モリ素子に入る順序に一致するように前記リサイクル型キューにタグを入れる手 段と、 前記リサイクル型キューのタグの値を前記読み出しアドレス・ポートに送 り、前記メモリ素子の命令情報が前記読み出しデータから読み出される順序を決 定する手段と、 前記メモリ素子に入れる一つ新規命令情報にリサイクルされたタグを1個 割り当てる手段と、 を備えることを特徴とするシステム。 25. 新規命令をいくつメモリ素子に入れられるか決定する手段をさらに備える ことを特徴とする請求項24に記載のシステム。 26. タグは、前記メモリ素子に入る命令にタグが既に割り当てられているかど うか示すバリディティ・ビットをさらに有することを特徴とする請求項25に記載 のシステム。 27. 命令のソースから命令情報を受け取りメモリ素子に格納する可変アドバン ス命令ウインドウを実現する方法で、 レジスタ・ファイルに関連命令情報を格納できる新規命令がいくつあるか 決定するステップと、 特定の命令のタグはその命令に関する情報がレジスタ・ファイルに存在す る限り変わることがないように新規命令毎にタグを割り当てるステップと、 各命令に関連する情報をレジスタ・ファイル内のその命令に割り当てられ たタグで指定する場所に格納し、前記レジスタ・ファイルは複数のレジスタと、 複数の読み出しアドレス・ポート及び複数の読み出しデータポートを含む、情報 格納のステップと、 キューのスロット毎にタグを1個づつ格納し、前記キューは所定の時点で レジスタ・ファイルに命令情報を入れられる上限の命令数に等しいスロット数を 有し、タグは各命令に対する命令情報がレジスタ・ファイルに格納されるのと同 じ順序でキューの中に入れられ、前記キューはスロット毎にスロット出力を有し 、各スロット出力によって対応するスロットのタグをアクセスできるようになる 、タグ格納のステップと、 前記キューのスロットに格納されたタグをレジスタ・ファイルの複数から なる読み出しアドレス・ポートに引き渡してレジスタ・ファイルの複数の読み出 しデータポートから命令に関する情報がレジスタ・ファイルに格納されたと同じ 順序でレジスタ・ファイルが命令に関する情報を出力するようにするステップと 、 を含むことを特徴とする方法。 28. 命令のソースから命令情報を受け取りレジスタ・ファイルに格納する可変 アドバンス命令ウインドウを実現するシステムで、 レジスタ・ファイルに関連する命令情報を入れられる新規命令がいくつあ るか決定し、特定の命令に関する情報がレジスタ・ファイルにある限りその命令 のタグが変わることがないように新規命令毎にタグを割り当てる制御手段と、 前記制御手段に接続され、各命令に関する情報をレジスタ・ファイル内の 1個の場所に格納し、前記場所はその命令に割り当てられたタグで指定され、レ ジスタ・ファイルは前記場所を形成する複数からなるレジスタと、複数の読み出 しデータポート及び複数の読み出しアドレス・ポートを有し、読み出しアドレス ・ポートには読み出しデータポートが対応している、レジスタ・ファイルと、 前記制御手段及びレジスタ・ファイルに接続され、複数のスロットを有し 、前記スロットには各々にレジスタ・ファイル内の場所のアドレスに対応する固 有のタグが収めれ、さらにスロット毎のスロット出力を有し、各スロット出力に よって対応するスロットにあるタグをアクセスできるようになる、リサイクル型 キューを備え、 前記リサイクル型キューのスロットに格納されたタグはレジスタ・ファイ ルの前記複数の読み出しアドレス・ポートに引き渡され、レジスタ・ファイルは 前記複数の読み出しデータポートから命令情報がレジスタ・ファイルに格納され たと同じ順序でレジスタ・ファイルに格納されている命令情報を出力するように することを特徴とするシステム。
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US08/224,328 | 1994-04-04 | ||
| US08/224,328 US5628021A (en) | 1992-12-31 | 1994-04-04 | System and method for assigning tags to control instruction processing in a superscalar processor |
| PCT/US1995/004132 WO1995027247A1 (en) | 1994-04-04 | 1995-04-04 | System and method for assigning tags to control instruction processing in a superscalar processor |
Related Child Applications (7)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2002246592A Division JP3587261B2 (ja) | 1994-04-04 | 2002-08-27 | 命令処理制御方法 |
| JP2002246587A Division JP3587256B2 (ja) | 1994-04-04 | 2002-08-27 | コンピュータ装置 |
| JP2002246590A Division JP3587259B2 (ja) | 1994-04-04 | 2002-08-27 | 命令処理制御システム |
| JP2002246586A Division JP3587255B2 (ja) | 1994-04-04 | 2002-08-27 | スーパースカラプロセッサ |
| JP2002246588A Division JP3587257B2 (ja) | 1994-04-04 | 2002-08-27 | 命令実行監視システム |
| JP2002246591A Division JP3587260B2 (ja) | 1994-04-04 | 2002-08-27 | 命令処理制御方法 |
| JP2002246589A Division JP3587258B2 (ja) | 1994-04-04 | 2002-08-27 | 命令実行監視方法 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH11511871A true JPH11511871A (ja) | 1999-10-12 |
| JP3561915B2 JP3561915B2 (ja) | 2004-09-08 |
Family
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Family Applications (8)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP52591495A Expired - Lifetime JP3561915B2 (ja) | 1994-04-04 | 1995-04-04 | スーパースカラ型プロセサにおいて命令処理を制御するためタグを割り当てるシステム及び方法 |
| JP2002246590A Expired - Lifetime JP3587259B2 (ja) | 1994-04-04 | 2002-08-27 | 命令処理制御システム |
| JP2002246592A Expired - Lifetime JP3587261B2 (ja) | 1994-04-04 | 2002-08-27 | 命令処理制御方法 |
| JP2002246587A Expired - Lifetime JP3587256B2 (ja) | 1994-04-04 | 2002-08-27 | コンピュータ装置 |
| JP2002246589A Expired - Lifetime JP3587258B2 (ja) | 1994-04-04 | 2002-08-27 | 命令実行監視方法 |
| JP2002246591A Expired - Lifetime JP3587260B2 (ja) | 1994-04-04 | 2002-08-27 | 命令処理制御方法 |
| JP2002246588A Expired - Lifetime JP3587257B2 (ja) | 1994-04-04 | 2002-08-27 | 命令実行監視システム |
| JP2002246586A Expired - Lifetime JP3587255B2 (ja) | 1994-04-04 | 2002-08-27 | スーパースカラプロセッサ |
Family Applications After (7)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2002246590A Expired - Lifetime JP3587259B2 (ja) | 1994-04-04 | 2002-08-27 | 命令処理制御システム |
| JP2002246592A Expired - Lifetime JP3587261B2 (ja) | 1994-04-04 | 2002-08-27 | 命令処理制御方法 |
| JP2002246587A Expired - Lifetime JP3587256B2 (ja) | 1994-04-04 | 2002-08-27 | コンピュータ装置 |
| JP2002246589A Expired - Lifetime JP3587258B2 (ja) | 1994-04-04 | 2002-08-27 | 命令実行監視方法 |
| JP2002246591A Expired - Lifetime JP3587260B2 (ja) | 1994-04-04 | 2002-08-27 | 命令処理制御方法 |
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| US (8) | US5628021A (ja) |
| JP (8) | JP3561915B2 (ja) |
| WO (1) | WO1995027247A1 (ja) |
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1995
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Also Published As
| Publication number | Publication date |
|---|---|
| US7430651B2 (en) | 2008-09-30 |
| US5896542A (en) | 1999-04-20 |
| JP2003076541A (ja) | 2003-03-14 |
| JP2003122565A (ja) | 2003-04-25 |
| JP3587256B2 (ja) | 2004-11-10 |
| JP2003122563A (ja) | 2003-04-25 |
| US8074052B2 (en) | 2011-12-06 |
| US6757808B2 (en) | 2004-06-29 |
| JP2003076540A (ja) | 2003-03-14 |
| JP3561915B2 (ja) | 2004-09-08 |
| JP2003122562A (ja) | 2003-04-25 |
| US20090013158A1 (en) | 2009-01-08 |
| US5628021A (en) | 1997-05-06 |
| US20060123218A1 (en) | 2006-06-08 |
| US6360309B1 (en) | 2002-03-19 |
| US7043624B2 (en) | 2006-05-09 |
| JP3587255B2 (ja) | 2004-11-10 |
| JP3587261B2 (ja) | 2004-11-10 |
| US20020053014A1 (en) | 2002-05-02 |
| JP2003122564A (ja) | 2003-04-25 |
| JP3587257B2 (ja) | 2004-11-10 |
| US20040199746A1 (en) | 2004-10-07 |
| JP3587260B2 (ja) | 2004-11-10 |
| JP3587259B2 (ja) | 2004-11-10 |
| US6092176A (en) | 2000-07-18 |
| JP2003076542A (ja) | 2003-03-14 |
| JP3587258B2 (ja) | 2004-11-10 |
| WO1995027247A1 (en) | 1995-10-12 |
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