JPH1141130A - Mixer circuit and receiver - Google Patents

Abstract

PROBLEM TO BE SOLVED: To quickly follow input level fluctuations and to compensate direct current offset voltage with high accuracy. SOLUTION: A switch 10 is connected to a test signal generation circuit 8 side of a terminal 10b at the time of non-information/start, and a continuous wave test signal is given to a balance mixer 3. In an input level detection circuit 9, an input level of the mixer 3 is detected and supplied to a compensation voltage generating circuit 6A. Compensation voltage V1 through compensation voltage Vn are stored in a storing part which supplies to an addressing part comprising from an address ADR1 to an address ADRn and corresponds detection results of output direct current offset voltage to the address ADR1 through the address ADRn of a storage circuit 6A1 in the circuit 6A. Compensation voltages Vi to Vn which correspond to an input level that is fluctuated by fading, etc., are stored in the circuit 6A. Offset voltage of an output of the mixer 3 that includes direct current offset voltage from an addition circuit 34 is compensated with the read compensation voltage Vi and is outputted.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a mixer circuit and a receiving apparatus, and more particularly to a mixer circuit and a receiving apparatus which can be applied to a balanced mixer circuit of a radio communication apparatus.

[0002]

2. Description of the Related Art Conventionally, a balance mixer having an output DC offset voltage compensation function averages an integrated voltage obtained by integrating a mixer output during communication, and compensates the average as an offset voltage.

FIG. 2 is a configuration diagram of a DC offset compensation balance mixer having a conventional configuration. In FIG. 2, an input signal 1a is applied to a signal input terminal 1 and applied to a balance mixer 3 together with a local oscillation signal of a local oscillator 2. The balance mixer 3 includes a first mixer 32, a second mixer 33, a phase inverting circuit 31 for inverting the phase of a local oscillation signal, and an adding circuit 34, and includes a first mixer 32 and a second mixer 32. 2 and the local oscillator signal in a state where the phases are inverted.
eLo is multiplied by the input signal ei.

The input signal 1a applied to the first mixer 32 and the second mixer 33 is ei, and the local oscillation signal applied to the first mixer 32 and the second mixer 33 is eLo.
1, eLo2. Assuming that the secondary conversion coefficient of the first mixer 32 is k1 and the secondary conversion coefficient of the second mixer 33 is k2, it can be expressed as follows.

[0005]

[Equation 1] ei = A (t) cos (ωt + Φ) (1)

[0006]

[Equation 2] eLo1 = -B (t) cos (ωt) ··· (2)

[0007]

## EQU00003 ## eLo2 = B (t) cos (.omega.t) (3) From these equations, the mixer output eo can be expressed as follows.

[0008]

[Equation 4] eo = k1 (ei + eLo1) ² -k2 (ei-eLo2) ² = k1 (2 × ei × eLo1 + ei ² + eLo1 ² ) -k2 (-2 × ei * eLo2 + eLo2 ² + ei ² ) (4) Here, when only the base frequency signal is extracted, it can be expressed as follows.

[0009]

Eo = -k1A (t) B cos (Φ) -k2A (t) B cos (Φ) + 1 / 2k1A ² (t) -1 / 2k2A ² (t) + 1 / 2k1B ² -1 / 2k2B ² ... (5) The first and second terms of this equation (5) are the mixer output converted to the original required base frequency of the mixer. The fourth term is a signal output by squaring the input signal itself to the first mixer 32 and the second mixer 33. The fifth and sixth terms are DC components output by squaring the local oscillation signal. The signals in the third and fourth terms are interference components due to second-order distortion, and the difference between the respective DC components is the DC offset voltage due to the signal component. The fifth and sixth terms are the generation of DC by the local oscillation signal, and the difference is the DC offset voltage by the local oscillation signal.

Ideally, it is necessary that k1A1 = k2A2 and k1 = k2. However, the magnitude of the signal of the third term differs from that of the signal of the fourth term due to the variation of the conversion coefficients k1 and k2 of the mixer and the loss of the phase inverting circuit.

[0011]

As described above, variations in the conversion coefficients of the respective mixers of the balance mixer,
There are an offset voltage caused by an input signal and an offset voltage caused by a local oscillation signal due to variations in the loss of the peripheral circuit.

The offset voltage due to the local oscillation signal is constantly constant, but the offset voltage due to the input signal fluctuates due to fading at a high speed, although the receiver is subject to AGC (automatic gain control). As a result, the AGC could not sufficiently follow, and the offset voltage could not be sufficiently compensated for the high-speed input level fluctuation.

[0013] Accordingly, there is a demand for a mixer circuit and a receiver capable of quickly following input level and frequency fluctuations and performing highly accurate DC offset voltage compensation.

[0014]

SUMMARY OF THE INVENTION Accordingly, the present invention provides a mixer which takes in an input signal and a local oscillation signal and outputs a mixing signal, and a DC offset compensator which detects a DC offset voltage contained in the mixing signal and performs offset compensation. The above-mentioned problem is solved by the following characteristic configuration in the mixer circuit including the means.

That is, the present mixer circuit includes (1) a test signal generating means for generating a test signal for performing offset compensation on the mixer, and (2) an input level detecting means for detecting an input level of the mixer. (3) The DC offset compensating means detects an input level detection result when the test signal is input to the mixer and a DC offset voltage included in the mixing signal at this time, and obtains an offset compensation voltage for the DC offset voltage. And manage
An offset compensation voltage management unit that sets and manages the offset compensation voltage according to a change in the level of the input test signal is included. When a non-test signal is input, offset compensation is performed using the offset compensation voltage that is set and managed. Do.

By employing such a configuration, a test signal (for example, a modulated signal or a non-modulated signal)
Since the offset compensation voltage according to the input level is set and managed, it is possible to set an appropriate offset compensation voltage with higher accuracy than before. Therefore, when an original input signal (for example, a communication signal) which is not a test signal is input to the mixer, appropriate offset compensation is performed using the offset compensation voltage set and managed by the offset compensation voltage management unit. Will be able to Therefore, even if the input level fluctuates at high speed, the offset voltage can be sufficiently compensated for the fluctuation by sufficiently following the input level.

The offset compensation voltage management section is constituted by, for example, a memory circuit, and the memory circuit is configured to control parameters (for example, level and frequency) of the input signal.
By using the address as the address and storing the offset compensation voltage corresponding to this address, it is possible to realize a simple and small circuit configuration, increase the storage information capacity, and increase the access speed for searching the offset compensation voltage. Will be able to

Further, the present invention includes (1) a test signal generating means for generating a test signal for performing offset compensation on the mixer, and (2) an input frequency detecting means for detecting an input frequency of the mixer. 3) The DC offset compensating means detects an input frequency detection result when the test signal is input to the mixer and a DC offset voltage included in the mixing signal at this time, and obtains an offset compensation voltage for the DC offset voltage. An offset compensation voltage management unit for setting and managing the offset compensation voltage in accordance with a change in the frequency of the input test signal; and when the non-test signal is input, the offset compensation voltage being set and managed. By performing the above-described offset compensation by using the above, even when a large frequency variation occurs in the input signal, the circuit can be rotated at high speed. Select offset compensation voltage according to the variation of the number appropriately it is possible to perform the offset compensation.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a preferred embodiment of the present invention will be described with reference to the drawings. Therefore, in this embodiment, first, in a balance mixer having an output DC offset compensation function, an input level detection circuit and a test signal input circuit including a test signal generator and a switch are provided at a signal input terminal of the balance mixer. . Further, there are provided a DC offset detection circuit for detecting a mixer output DC offset voltage when a test signal is input, a compensation voltage generation circuit for generating a compensation voltage, and a compensation voltage adding circuit for adding a compensation voltage to the balance mixer output.

This compensation voltage generation circuit stores a corresponding detected DC offset compensation voltage in a storage circuit (for example, a memory circuit) having a test signal input level as an address. The received signal input level is detected by an input level detection circuit, a compensation voltage stored at a corresponding address of a storage circuit is selected based on the level detection result, and the selected DC offset compensation voltage is added through an addition circuit. It is configured to add.

With this configuration, an accurate DC offset compensation voltage can be generated even if the input level fluctuates due to fading or the like. In addition, the compensation voltage stored in the storage device is updated when the device is started and / or when non-information communication is performed.

FIG. 1 is a configuration diagram of a DC offset compensation balance mixer circuit. In FIG. 1, a DC offset compensating balance mixer circuit includes an input signal from a receiver.
An input terminal 1 to which 1a is supplied and a switch 10 for selecting a continuous wave test signal from a test signal generation circuit 8 for generating a continuous wave (CW) as a test signal are connected to the input side of the balance mixer 3. . Further, an input level detection circuit 9 is connected to the input side of the balance mixer 3, and detects an input level of the balance mixer.

The balance mixer 3 includes a first mixer 32 to which a local oscillation signal 2a obtained by inverting a local oscillation signal from the local oscillator 2 by a phase inversion circuit 31 and a signal obtained by branching the input signal 1a are supplied. The second mixer 33 and the first
And an adder 34 for inverting and adding the output signals of the second mixer 32 and the second mixer 33.

On the output side of the balance mixer 3, there is provided an addition circuit 4 for adding the compensation signal from the compensation voltage generation circuit 6A and the output signal of the addition circuit 34 of the balance mixer 3;
This addition result is output to the output terminal 7. The DC offset detection circuit 5 detects the DC offset voltage output to the output terminal 7, and supplies the detection result to the compensation voltage generation circuit 6A. Further, the input level detection circuit 9 detects the input level of the balance mixer 3 and supplies the input level detection result to the compensation voltage generation circuit 6A.

Next, the operation of the DC offset compensation balance mixer circuit will be described. FIG. 3 is an operation flowchart at the time of non-information communication / start-up in the DC offset compensation balance mixer circuit of the present embodiment. FIG. 4 is an operation flowchart at the time of communication in the DC offset compensation balance mixer circuit of the present embodiment.

First, the switch 10 is connected to the test signal generating circuit 8 at the terminal 10b at the time of non-information communication or at the time of startup (step S10), and a continuous wave test signal is supplied to the balance mixer 3 (step S20). This continuous wave test signal is composed of a sine wave having the same frequency as the original received signal, and changes its amplitude sequentially.

The input level detection circuit 9 detects the input level of the balance mixer 3 (step S30) and supplies it to the compensation voltage generation circuit 6A. The input level detection result is supplied to an address section consisting of an address ADR1 to an address ADRn of a storage circuit 6A1 composed of, for example, a memory element or a processor in the compensation voltage generation circuit 6A. The offset voltage detection result is stored from the compensation voltage V1 to the compensation voltage Vn in the storage unit corresponding to the address ADR1 to the address ADRn (steps S40 to S80).

That is, for the first input level detection (step S30), the address ADRi is set (step S4).
0) Then, the output DC offset voltage at that time is detected (step S50), and the compensation voltage Vi for this address ADRi is set (step S60). If the address ADRi is equal to or smaller than the address ADRn (step S70), the input level is changed (step S80) in order to set the next address ADRi = i + 1, and the above steps S30 to S30 are similarly performed.
Execute S70 to set the compensation voltage Vi for all addresses.
Set ~ Vn.

As a result, the compensation voltage generating circuit 6A includes:
Compensation voltages Vi to Vn corresponding to input levels that change due to fading or the like are stored.

The stored compensation voltages Vi to Vn are updated at the time of starting the apparatus or at the time of non-information communication, and are optimally updated in response to a temperature change or a change with time (step).
S10-S80). When the compensation voltage of the compensation voltage generation circuit 6A is updated, the operation at the time of communication is performed (step S90 in FIGS. 3 and 4). That is, first, the switch 10 is connected to the input terminal side 10.
a, the input signal 1a from the original receiver is supplied. The input level of the input signal 1a is detected by the input level detection circuit 9 (step S92 in FIG. 4), and the detection result is given to the compensation voltage generation circuit 6A, and is sent to the address ADRi (step S94) corresponding to this detection level. The stored compensation voltage Vi is read out (step S96), and the addition circuit 4
Supplied to In the adding circuit 4, the offset voltage of the output of the balance mixer 3 including the DC offset voltage from the adding circuit 34 is compensated by the read compensation voltage Vi (step S98) and output to the output terminal 7 (step S98). S10
0).

As described above, the DC offset voltage that fluctuates according to the input level can be optimally compensated, and the compensation voltage of the compensation voltage generating circuit 6A can be optimized even if there is a temperature variation or a variation over time. , It is possible to obtain a good balance mixer circuit output.

Further, in a mobile communication system in which a plurality of high frequency (RF) channels exist, conversion coefficients and the like vary depending on the high frequency channel. This can be dealt with as follows.

That is, the local oscillation frequency and the frequency of the test signal generation circuit may be sequentially changed, and the compensation voltage may be set for each frequency in the compensation voltage generation circuit.

In the embodiment described above, the test signal is a non-modulated sine wave, but the same effect can be obtained by using a modulated signal. Furthermore, although the DC offset voltage changes due to power supply voltage fluctuations, the offset compensation voltage can be updated during non-communication, so that the compensation of the DC offset voltage due to the power supply voltage fluctuations can be effectively performed. It can be carried out.

[0035]

As described above, according to the present invention, the input level (or frequency) detection result when the test signal is input to the mixer and the DC offset voltage included in the mixing signal at this time are detected, and this DC An offset compensation voltage management unit for obtaining and setting and managing an offset compensation voltage with respect to the offset voltage, and setting and managing the offset compensation voltage in accordance with a change in the level (or frequency) of the input test signal; Since the offset compensation is performed using the offset compensation voltage which is sometimes set and managed, it is possible to quickly follow an input level or a frequency variation and perform a highly accurate DC offset voltage compensation. become able to.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a DC offset compensation balance mixer circuit according to an embodiment of the present invention.

FIG. 2 is a configuration diagram of a conventional DC offset compensation balance mixer circuit.

FIG. 3 is an operation flowchart at the time of non-information communication / start-up in the DC offset compensation balance mixer circuit of the present embodiment.

FIG. 4 is an operation flowchart at the time of communication in the DC offset compensation balance mixer circuit of the present embodiment.

[Explanation of symbols]

 2 Local oscillator 3 Balance mixer 5 DC offset detection circuit 6A Compensation voltage generation circuit 6A1 Storage circuit 8 Test signal generation circuit 9 Input level detection circuit

Claims (6)

[Claims] 1. A mixer circuit comprising: a mixer for receiving an input signal and a local oscillation signal to output a mixing signal; and a DC offset compensating means for detecting a DC offset voltage included in the mixing signal and performing offset compensation. The circuit includes: a test signal generation unit that generates a test signal for performing offset compensation on the mixer; and an input level detection unit that detects an input level of the mixer. An input level detection result when input to the mixer, and at this time, the DC offset voltage included in the mixing signal is detected and an offset compensation voltage for the DC offset voltage is obtained and managed, and the management is performed. The offset compensation voltage is set according to the level change of the input test signal, and A mixer circuit that includes an offset compensation voltage management unit that performs offset compensation by using the set and managed offset compensation voltage when a non-test signal is input. 2. The mixer circuit according to claim 1, wherein
When the non-test signal is input to the mixer, the input level detecting means detects an input level, and the DC offset compensating means outputs an offset compensation voltage corresponding to the detection result of the input level to the offset compensation voltage. A mixer circuit, which is selected from a management unit and offset-compensates the DC offset voltage included in the mixing signal. 3. A mixer circuit comprising: a mixer for receiving an input signal and a local oscillation signal and outputting a mixing signal; and a DC offset compensating means for detecting a DC offset voltage included in the mixing signal and performing offset compensation. The circuit includes: a test signal generation unit that generates a test signal for performing offset compensation on the mixer; and an input frequency detection unit that detects an input frequency of the mixer. An input frequency detection result when input to the mixer, and at this time, the DC offset voltage included in the mixing signal is detected and an offset compensation voltage for the DC offset voltage is obtained and managed, and the input is detected. Set and manage the offset compensation voltage according to the change in the frequency of the test signal A mixer circuit that includes an offset compensation voltage management unit that performs the offset compensation by using the set and managed offset compensation voltage when a non-test signal is input. 4. The mixer circuit according to claim 3, wherein
When the non-test signal is input to the mixer, the input frequency detecting means detects an input frequency, and the DC offset compensating means outputs an offset compensating voltage corresponding to the result of detecting the input frequency to the offset compensating voltage. A mixer circuit, which is selected from a management unit and offset-compensates the DC offset voltage included in the mixing signal. 5. The mixer circuit according to claim 1, wherein the offset compensation voltage management unit includes a memory circuit, and the memory circuit corresponds to the address using a parameter of the input signal as an address. A mixer circuit for storing an offset compensation voltage. 6. A receiving device including the mixer circuit according to claim 1, wherein the receiving device supplies the test signal to the mixer immediately after activation or when information is not received. The offset compensation voltage is set and managed by the DC offset compensating means, or the offset compensation voltage is updated, and when receiving information, the offset compensation is performed using the offset compensation voltage which is set and managed. A receiving device characterized by the above-mentioned.