JPH113990A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

(57) [Problem] To reduce the thickness of a gate insulating film and, when a high dielectric constant material is used for the gate insulating film, increase the gate electric field, thereby increasing current leakage and deteriorating device characteristics. I was In addition, a short channel effect has occurred due to the overlap between the gate electric field and the drain electric field. SOLUTION: The semiconductor device 1 in which a gate electrode 13 is formed on a semiconductor substrate 11 via a gate insulating film 12 and diffusion layers 14 and 15 are formed in the semiconductor substrate 11 on both sides of the gate electrode 13 is provided. The gate insulating film 12 is formed to be shorter in the gate length direction than the gate electrode 13, and the side of the gate insulating film 12 in the gate length direction and the gate electrode 13 and the semiconductor substrate.
11 and a region where at least the gate electrode 13 and the diffusion layers 14 and 15 overlap in plan view,
A space 21 is formed. Further, a dielectric (not shown) is embedded in the space 21.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method for manufacturing the same.

[0002]

2. Description of the Related Art In a conventional gate structure of a semiconductor device, a gate insulating film is formed on a semiconductor substrate, and a gate electrode is further formed thereon. Was formed of a single kind of material and formed over the entire surface below the gate electrode. As a conventional gate electric field relaxation structure, there is a so-called LDD (Lightly Doped Drain) structure. That is, the semiconductor substrate on both sides of the gate electrode has a structure in which a source / drain is formed via a low concentration diffusion layer, so-called LDD (Lightly Doped Drain).
In this LDD structure, an impurity is doped (for example, ion-implanted) using a gate electrode as a mask to form an LDD serving as a low-concentration diffusion layer in a semiconductor substrate, and then sidewalls are formed on both sides of the gate electrode. This sidewall has a length of, for example, 100 nm in the gate length direction.
Formed to the extent. Then, the source and the drain are formed on the semiconductor substrate on both sides of the gate electrode via the LDD by doping (for example, ion implantation) impurities using the sidewall and the gate electrode as a mask.

[0003]

With the progress of miniaturization of the element size in the semiconductor device, the electric field inside the semiconductor device tends to increase. One of the bad effects of a high electric field on the characteristics of a semiconductor device is a current leakage caused by a gate electric field (hereinafter referred to as GIDL;
Induced Drain Leakage), IEDM, (1987) TYCha
n, J. Chen, PKKoand C. Hu, p718-721.

[0004] As shown in FIG.
Gate electrode 111 and diffusion layer 1 in semiconductor device 101
In the semiconductor in the vicinity of the interface between the gate insulating film 114 and the semiconductor substrate 115 in the overlap region A when viewed in plan view with respect to the gate electrode 12 and the overlap region B between the gate electrode 111 and the diffusion layer 113 when viewed in plan view, Electrode 1
This is caused by a mechanism in which the carrier leaks due to the strong electric field generated from the carrier 11. This current leak occurs as the gate insulating film 114 becomes thinner.
In addition, it is known that as the dielectric constant of the gate insulating film 114 increases, the gate insulating film 114 increases in the direction of deterioration.

As a method of suppressing the current leakage, a structure has been proposed in which the thickness of the gate insulating film in this region is locally increased to reduce the gate electric field. In this structure, there is a problem that the insulating film around the corresponding region is thickened by, for example, a bird's beak.
Eventually, fabrication of the gate structure becomes difficult.

In the case where the semiconductor device is a field-effect transistor and the LDD is formed on the source and drain, it is necessary to form sidewalls on both sides of the gate electrode in order to form the LDD. Therefore, some hot carriers stay in the sidewall,
There is a problem that the element is deteriorated. Further, since an LDD formation region is required, miniaturization of the element is hindered.

[0007]

SUMMARY OF THE INVENTION The present invention is directed to a semiconductor device and a method of manufacturing the same to solve the above-mentioned problems.

The semiconductor device is a semiconductor device in which a gate electrode is formed on a semiconductor substrate via a gate insulating film, and a diffusion layer is formed in the semiconductor substrate on both sides of the gate electrode. Is formed shorter in the gate length direction than the gate electrode, and the space between the gate electrode and the semiconductor substrate at least overlaps the gate electrode and the diffusion layer in plan view on the side of the gate insulating film in the gate length direction. It is formed in the area to be wrapped. The space is preferably formed wider in the thickness direction than the thickness of the gate insulating film.

Alternatively, the gate insulating film is formed to be shorter in the gate length direction than the gate electrode, and is formed on a side of the gate insulating film in the gate length direction and in a region sandwiched between the gate electrode and the semiconductor substrate, and A dielectric having a dielectric constant lower than that of the gate insulating film is formed in a region where the electrode and the diffusion layer overlap in a plan view. The dielectric is preferably formed to be thicker in the thickness direction than the thickness of the gate insulating film.

In the above semiconductor device, a space is provided in a region sandwiched between the gate electrode and the semiconductor substrate and where the gate electrode and the diffusion layer overlap in plan view, or the dielectric constant of the gate insulating film is increased. Since a dielectric having a lower dielectric constant is provided, the dielectric constant is lower in the space or the region where the dielectric is provided than in the gate insulating film. Therefore, the electric field intensity in the space or the region where the dielectric is provided is reduced, so that the occurrence of tunnel leak is reduced. In a configuration in which the space is formed wider in the thickness direction than the gate insulating film, or in a configuration in which the dielectric is formed thicker in the thickness direction than the gate insulating film, the electric field strength of the space or the region where the dielectric is provided further increases. As a result, the occurrence of tunnel leak is greatly reduced. Further, since it is not necessary to form an LDD, the element can be miniaturized. In addition, since it is not necessary to form a sidewall, deterioration of the element due to retention of hot carriers is eliminated.

In the above semiconductor device, the gate electrode portion on the space may be separated from the gate electrode portion on the gate insulating film via an isolation space or an isolation insulating film. The gate electrode side of the diffusion layer may be formed at a low concentration. Alternatively, a diffusion layer having a lower concentration than that of the diffusion layer may be formed on the semiconductor substrate under the space to be connected to the diffusion layer. Alternatively, instead of providing the space, a dielectric having a lower dielectric constant than the gate insulating film may be provided.

In the semiconductor device in which the gate electrode is separated, it is possible to apply an arbitrary voltage to the gate electrode in the space (dielectric) regardless of the voltage of the gate electrode on the gate insulating film. Thereby, a large electric field relaxation effect is obtained. In a semiconductor device having a low-concentration diffusion layer formed thereon, an electric-field relaxation effect by the low-concentration diffusion layer can be obtained in addition to the electric-field relaxation effect by forming a space (dielectric). That is, the electric field relaxation effect is further increased.

A method of manufacturing a semiconductor device includes a step of forming a gate insulating film on a semiconductor substrate, a step of forming a gate electrode on the gate insulating film, and a step of forming a diffusion layer on the semiconductor substrate on both sides of the gate electrode. After the gate electrode is formed, the gate insulating film is removed in a state in which the gate insulating film is shorter in the gate length direction than the gate electrode, and the gate electrode and the semiconductor substrate are laterally located on the gate insulating film in the gate length direction. Is formed in a region where at least the gate electrode and the diffusion layer overlap in a plan view. Also, after forming the gate electrode and before forming the space, the end of the gate insulating film in the gate length direction is heated,
The end of the gate insulating film may be thick. Alternatively, after forming the space, the surface of the gate electrode may be oxidized, and the oxidized portion may be removed to form a space wider than the gate insulating film in the thickness direction.

Alternatively, after forming the space, a dielectric having a dielectric constant lower than that of the gate insulating film is buried in the space.

In the method of manufacturing a semiconductor device, after the gate electrode is formed, the gate insulating film is removed so as to be shorter in the gate length direction than the gate electrode, and the gate is formed on the side of the gate insulating film in the gate length direction. Because a space between the electrode and the semiconductor substrate is formed in a region where the gate electrode and the diffusion layer overlap in plan view, or a dielectric having a dielectric constant lower than that of the gate insulating film in the space. Since the body is provided, the dielectric constant is lower in the space or the region where the dielectric is provided than in the gate insulating film. Therefore, the electric field intensity in the space or the region where the dielectric is provided is reduced, so that the occurrence of tunnel leak is reduced. In the method of forming a space wider than the thickness of the gate insulating film and the method of forming a dielectric thicker than the thickness of the gate insulating film, the electric field strength in the space or the region where the dielectric is provided is further reduced. Therefore, the occurrence of tunnel leak is greatly reduced.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An example of the first embodiment of the present invention will be described below.
This will be described with reference to the schematic configuration diagram of FIG.

As shown in FIG. 1, a gate insulating film 12 is formed on a semiconductor substrate 11. A gate electrode 13 longer than the gate insulating film 12 is formed on the gate insulating film 12 in the gate length direction. In other words,
The gate insulating film 12 is formed shorter in the gate length direction than the gate electrode 13. A space 21 between the gate electrode 13 and the semiconductor substrate 11 is formed on the side of the gate insulating film 12 in the gate length direction. Diffusion layers 14 and 15 are formed on the semiconductor substrate 11 on both sides of the gate electrode 13. The space 21 is formed in a region where at least the gate electrode 13 and the respective diffusion layers 14 and 15 overlap in a plan view. Further, the space 21 has a vacuum atmosphere or an inert atmosphere. The semiconductor device 1 is configured as described above.

In the semiconductor device 1, the space 21 is provided in a region sandwiched between the gate electrode 13 and the semiconductor substrate 11 and in which the gate electrode 13 and the respective diffusion layers 14 and 15 overlap in plan view. Therefore, the dielectric constant of the region where the space 21 is provided is lower than that of the gate insulating film 12. Therefore, the electric field intensity in that region is reduced, so that the occurrence of tunnel leak is reduced. Further, since it is not necessary to form an LDD as in the prior art, the device can be miniaturized. In addition, since it is not necessary to form a sidewall, deterioration of the device due to retention of hot carriers is eliminated.

A simple GIDL analysis model is shown in the explanatory diagram of the GIDL analysis model shown in FIG.
Note that the reference numerals given to each component in the following description are based on the reference numerals shown in FIG.

Drain leakage current I caused by GIDL
d is expressed as follows using the surface electric field strength Es at the interface between the semiconductor substrate 11 and the gate insulating film 12.

[0021]

(Equation 1)

Here, A and B are constants, respectively. The above equation (1) shows that the smaller the surface electric field strength Es, the smaller the drain leak current Id.
The surface electric field strength Es is expressed by the gate-drain voltage V
gd, thickness tox of gate insulating film 12 and gate insulating film 1
When the relative dielectric constant εox of 2 and the relative dielectric constant εs of the semiconductor substrate 11 are used, they are expressed as follows. The relative permittivity is usually expressed as shown on the left side of equation (3), but in this specification, (3)
Expressed as ε as in the right side of the equation.

[0023]

(Equation 2)

[0024]

(Equation 3)

However, Vbend is the semiconductor band bending caused by the gate electric field, and when this value exceeds the forbidden band width Eg of the semiconductor substrate 11, a tunnel leak occurs.
Therefore, in the analysis of the leakage current, Vbend {Eg}
The above equation (2) is calculated by substituting 1.2V. In the semiconductor device 1, each diffusion layer 14,
The relative permittivity εox is reduced by setting the area where 15 overlaps as the space 21. As a result, the value of the term [epsilon] ox / [epsilon] s in the above equation (2) decreases, and the surface electric field strength Es can be reduced.

By appropriately designing the structure of the semiconductor device 1, the leakage current caused by GIDL can be reduced by the leakage current caused by other factors (for example, the generated recombination current or diffusion current at the PN junction around the element isolation LOCOS). A model of the effect of suppressing the current or less will be described below.

Quantitatively, when the gate insulating film 13 is formed of a silicon oxide film (SiO ₂ film), its relative dielectric constant is εox ≒ 4. On the other hand, when the space 21 is replaced with, for example, air, the relative dielectric constant is εox ≒ 1.
become. Therefore, according to the above equation (2), there is an effect that the surface electric field strength Es is reduced to about 1/4 under the condition that tox and Vgd-Vbend are constant. This is the gate insulating film 1
The effect is equivalent to quadrupling the film thickness tox of No. 2.

As a result, as shown by the solid line in the relationship diagram between the drain junction leak current Id (shown by natural logarithm) and the drain voltage Vd in FIG. 3, even if the drain voltage Vd is increased, the drain junction leak current Id is almost constant. Be kept constant. In the figure, the broken line shows the current-voltage relationship in the case of the conventional semiconductor device, and the solid line shows the current-voltage relationship in the structure of the semiconductor device 1 described with reference to FIG. The gate voltage was set to 0V.

Next, suppression of the short channel effect of this structure will be described. The short-channel effect is that when an electric field extending from a source (for example, the diffusion layer 14) or a drain (for example, the diffusion layer 15) extends to a region under the gate insulating film 12 where a gate electric field is strongly applied, the electric field is This is an effect of applying an electric field more than intended by controlling the gate electrode 13 in the overlapped region, which causes a problem such as a decrease in threshold voltage.

In the structure of the semiconductor device 1, the region where the gate electric field is strongly applied (the region above the semiconductor substrate 11 immediately below the gate insulating film 12) is the source / drain (diffusion layer 1).
4, 15), the electric field overlap region, which has been a problem, is small. Therefore, the short channel effect is reduced.

The provision of the space 21 has substantially the same effect as the increase in the thickness of the gate insulating film 12 at that portion. This is the source / drain (or LDD)
In the configuration where the channel length is shortened, the roll-off effect due to the short channel effect is alleviated, so that the threshold voltage is reduced. The decrease can be suppressed. This means that the threshold voltage can be used without fluctuation even for a transistor having a short channel length, which is advantageous for further miniaturization. Further, since the dielectric constant at the end of the gate insulating film 12 is reduced, the electric field is reduced as described above, and the reliability for hot carriers is increased.

In such a case, as shown in FIG.
The ion implantation for forming the diffusion layers 14 and 15 is performed by so-called oblique ion implantation in which the gate electrode 13 is shaded, so that a region 16 (shown by a two-dot chain line) where a gate electric field is strongly applied from the diffusion layer 14 (source diffusion layer). Part) can be reduced. However, in this case, it is necessary that the source of each transistor formed simultaneously is designed in the same direction with respect to the gate.

Next, a configuration example in which the configuration of the semiconductor device 1 is applied to a nonvolatile semiconductor memory device will be described with reference to FIG. In FIG. 5, the same components as those described with reference to FIG. 1 are denoted by the same reference numerals.

As shown in FIG. 5, in the semiconductor device 2, the gate insulating film 12 is formed on the semiconductor substrate 11 and the floating gate 31 (the gate electrode of FIG. 13). The gate insulating film 12 is formed to be shorter in the gate length direction than the floating gate 31, and a space 21 between the floating gate 31 and the semiconductor substrate 11 is provided on the side of the gate insulating film 12 in the gate length direction. Are formed. Diffusion layers 14 and 15 are formed in the semiconductor substrate 11 on both sides of the floating gate 31. The space 21 is formed at least in a region where the floating gate 31 and each of the diffusion layers 14 and 15 overlap in a plan view. Further, the space 21 has a vacuum atmosphere or an inert atmosphere. Further, in the present semiconductor device 2, an insulator film 32 is formed on the floating gate 31 and a control gate 33
Are formed. The semiconductor device 2 is configured as described above.

In the semiconductor device 2 as well, the provision of the space 21 has the effect of reducing the current leakage and the short channel effect, similarly to the semiconductor device 1 described above.

Next, an example of the second embodiment according to the semiconductor device of the present invention will be described with reference to the schematic configuration diagram of FIG. In FIG. 6, the same components as those described with reference to FIG. 1 are denoted by the same reference numerals.

As shown in FIG. 6, a gate insulating film 12 is formed on a semiconductor substrate 11. A gate electrode 13 longer than the gate insulating film 12 is formed on the gate insulating film 12 in the gate length direction. In other words,
The gate insulating film 12 is formed shorter in the gate length direction than the gate electrode 13. A space 21 between the gate electrode 13 and the semiconductor substrate 11 is formed on the side of the gate insulating film 12 in the gate length direction. The space 21 is formed, for example, with a length of about 50 nm in the gate length direction, and has a vacuum atmosphere or an inert atmosphere. Diffusion layers 14 and 15 are formed on the semiconductor substrate 11 on both sides of the gate electrode 13. Each of the diffusion layers 14 and 15 is formed so as not to overlap the gate electrode 13 in a plan view. The semiconductor device 3 is configured as described above. Note that the length of the space 21 in the gate length direction is not limited to the above value, and is appropriately selected.

In the semiconductor device 3, the semiconductor device 1
Similarly to the above, since the space 21 is provided in the region between the gate electrode 13 and the semiconductor substrate 11, the dielectric constant is lower in the region where the space 21 is provided than in the gate insulating film 12. Therefore, the electric field intensity in that region is reduced, so that the occurrence of tunnel leak is reduced. Moreover, since each of the diffusion layers 14 and 15 is formed so as not to overlap the gate electrode 13 in a plan view, an electric field relaxation effect larger than that of the semiconductor device 1 can be obtained. In addition, since it is not necessary to form an LDD as in the related art, the device can be miniaturized. In addition, since it is not necessary to form a sidewall, deterioration of the device due to retention of hot carriers is eliminated.

Next, an example of the third embodiment according to the semiconductor device of the present invention will be described with reference to the schematic configuration diagram of FIG. In FIG. 7, the same components as those described with reference to FIGS. 1 and 6 are denoted by the same reference numerals.

As shown in FIG. 7, the semiconductor device 4 is the same as the semiconductor device 3 described with reference to FIG.
The upper gate electrode portion 13 (13s) is the gate insulating film 12
It is separated from the upper gate electrode portion 13 (13c) via a separation space 25. As a result, the gate electrode portion 1
3 (13s) is in a floating state on the active area, but the above configuration is possible by supporting it in a field area (not shown) surrounding the side circumference of the active area. The separation space 25 is formed, for example, to have a length in the gate length direction of about 20 nm to 30 nm, and has a vacuum atmosphere or an inert gas atmosphere. Or separation space 2
Instead of 5, an isolation insulating film (not shown) may be formed. This isolation insulating film is preferably formed of a material having a lower dielectric constant than the gate insulating film. The semiconductor substrate 11, the gate insulating film 12, the diffusion layer 14, the diffusion layer 15, and the like, which are other components other than those described above, have the same configuration as the semiconductor device 3. The semiconductor device 4 is configured as described above. Note that the length of the space 21 in the gate length direction is not limited to the above value, and is appropriately selected.

On the other hand, as described with reference to FIG.
In the configuration in which the semiconductor device 4 is formed such that the diffusion layers 14 and 15 and the gate electrode 13 overlap in a plan view, the space 21 includes at least the gate electrode 13 and each of the diffusion layers 14. , 15 are preferably formed in a region overlapping in plan view.

In the semiconductor device 4, the semiconductor device 3
The same operation as described above is obtained, and the gate electrode 13
Is formed between the gate electrode portion 13c on the gate insulating film 12 and the space 2
1 and the gate electrode portion 13s on the space 21, it is possible to apply an arbitrary voltage to the gate electrode portion 13s on the space 21 regardless of the voltage on the gate electrode portion 13c on the gate insulating film 12. . Therefore, the electric field relaxation effect is larger than that of the semiconductor device 3.

Next, an example of the third embodiment according to the semiconductor device of the present invention will be described with reference to the schematic configuration diagram of FIG. In FIG. 8, the same components as those described with reference to FIGS. 1 and 6 are denoted by the same reference numerals.

As shown in FIG. 8, the semiconductor device 5 is the same as the semiconductor device 3 described with reference to FIG.
4 is a low concentration diffusion layer, ie, L
DD (Lightly Doped Drain) 16
The gate electrode 13 side of the diffusion layer 15 is similarly formed of the LDD 17 which is a low concentration diffusion layer.
Therefore, the diffusion layer 14 is composed of the LDD 16 and the source / drain 18 having a higher concentration, and the diffusion layer 15 is composed of the LDD 17 and the source / drain 19 having the higher concentration. The semiconductor substrate 11, the gate insulating film 12, the gate electrode 13, the space 21, and the like of other components other than those described above have the same configuration as the semiconductor device 3. This space 21 is formed, for example, with a length of about 50 nm in the gate length direction, and has a vacuum atmosphere or an inert gas atmosphere. The semiconductor device 5 is configured as described above. The above space 2
The length in the gate length direction of 1 is not limited to the above value and is appropriately selected.

In the semiconductor device 5, the semiconductor device 3
Since the same operation as described above is obtained and the LDDs 16 and 17 serving as low concentration diffusion layers are formed, the space 2
In addition to the electric field relaxation effect of the formation of
The electric field relaxation effect is obtained. That is, the effect of alleviating the electric field is larger than that of the semiconductor device 3.

Next, an example of the fourth embodiment according to the semiconductor device of the present invention will be described with reference to the schematic configuration diagram of FIG. In FIG. 9, the same components as those described with reference to FIGS. 1 and 8 are denoted by the same reference numerals.

As shown in FIG. 9, the semiconductor device 6 is the same as the semiconductor device 1 described with reference to FIG.
The lower semiconductor substrate 11 is connected to the diffusion layer 14 so that the LDD 16 which is a diffusion layer having a lower concentration than the diffusion layer 14 is formed, and the semiconductor substrate 11 under one space 21 is formed.
The LDD 17 which is a diffusion layer having a lower concentration than that of the diffusion layer 15 is also connected to the diffusion layer 15. Therefore, the diffusion layer 14 is composed of the LDD 16 and the source / drain 18 having a higher concentration, and the diffusion layer 15 is composed of the LDD 17 and the source / drain 19 having the higher concentration. In addition, the semiconductor device 11, the gate insulating film 12, the gate electrode 13, the space 21 and the like other components other than those described above are the same as those of the semiconductor device 1.
This is the same configuration as. This space 21 is formed, for example, with a length of about 50 nm in the gate length direction, and has a vacuum atmosphere or an inert gas atmosphere. The semiconductor device 6 is configured as described above. Note that the length of the space 21 in the gate length direction is not limited to the above value, and is appropriately selected.

In the semiconductor device 6, the semiconductor device 1
Since the same operation as described above is obtained and the LDDs 16 and 17 serving as low concentration diffusion layers are formed, the space 2
In addition to the electric field relaxation effect of the formation of
The electric field relaxation effect is obtained. That is, the effect of alleviating the electric field is larger than that of the semiconductor device 1.

Next, an example of the sixth embodiment according to the semiconductor device of the present invention will be described with reference to the schematic configuration diagram of FIG.
In FIG. 10, the same components as those described with reference to FIG. 1 are denoted by the same reference numerals.

As shown in FIG. 10, the semiconductor device 7 is such that the space 21 of the semiconductor device 1 described with reference to FIG. 1 is formed wide in the film thickness direction. That is, a gate insulating film 12 is formed on the semiconductor substrate 11, and a gate electrode 13 longer than the gate insulating film 12 in the gate length direction is formed on the gate insulating film 12. A space 23 between the gate electrode 13 and the semiconductor substrate 11 is formed on the side of the gate insulating film 12 in the gate length direction. The space 23 is formed to be wider than the thickness of the gate insulating film 12 in the thickness direction of the gate insulating film 12. Diffusion layers 14 and 15 are formed on the semiconductor substrate 11 on both sides of the gate electrode 13. The space 23 is formed in a region where at least the gate electrode 13 and the respective diffusion layers 14 and 15 overlap in a plan view. Further, the space 23 has a vacuum atmosphere or an inert atmosphere. The semiconductor device 7 is configured as described above.

In the semiconductor device 7, the space 23 is formed in the thickness direction of the gate insulating film larger than the space 21 of the semiconductor device 1 described with reference to FIG.
The electric field in the region where the space 23 is provided is further reduced than in the semiconductor device 1. In particular, the electric field near the drain is reduced. Also in the semiconductor device 2 described with reference to FIG. 5, it is desirable to form a space 23 that is formed wider in the thickness direction of the gate insulating film 12 as described with reference to FIG. By forming such a space 23, in the semiconductor device 2, the effects of further reducing the current leakage and reducing the short channel effect can be obtained.

Although not shown, in the semiconductor devices 3 to 6 described with reference to FIGS. 6 to 9, a space 23 like the semiconductor device 7 can be formed instead of the space 21. Even with such a configuration, an electric field relaxation effect that is even greater than that provided with the space 21 can be obtained as in the case of the semiconductor device 7.

Next, an example of the seventh embodiment according to the semiconductor device of the present invention will be described with reference to the schematic configuration diagram of FIG.
In FIG. 11, the same components as those described with reference to FIG. 1 are denoted by the same reference numerals.

As shown in FIG. 11, in the semiconductor device 8, a dielectric 22 having a dielectric constant lower than that of the gate insulating film 12 is provided in the space 21 of the semiconductor device 1 described with reference to FIG. Things. That is, a gate insulating film 12 is formed on a semiconductor substrate 11, and the gate insulating film 12 is formed on the gate insulating film 12 in a gate length direction.
A longer gate electrode 13 is formed. Further, a space 21 sandwiched between the gate electrode 13 and the semiconductor substrate 11 is formed on the side of the gate insulating film 12 in the gate length direction, and the dielectric 22 is provided in this space 21. Diffusion layers 14 and 15 are formed on the semiconductor substrate 11 on both sides of the gate electrode 13. The dielectric 22 is formed in a region where at least the gate electrode 13 and the respective diffusion layers 14 and 15 overlap in plan view.

For example, the gate insulating film 12 is formed of silicon nitride.
Con (Si_ThreeN_Four) [Relative permittivity εSi _ThreeN_Four{6-8], acid
Tantalum fluoride (Ta_TwoO_Five) [Relative permittivity εTa_TwoO_Five$ 20 ~
25], a material having a high dielectric constant such as
For example, silicon oxide (SiO 2)_Two)
Use a material with a low dielectric constant such as [relative dielectric constant εox ≒ 4]
You. The dielectric 22 is made of a fluorocarbon (CF) film.
[Relative permittivity εCF ≒ 2.2-2.7], oxidation containing fluorine
Silicon (SiOF) film [relative permittivity εSiOF ≒ 3.2-
3.7], polyparaxylylene [relative permittivity ε ≒ 2.4]
It is also possible to use a so-called low dielectric constant film.

In the semiconductor device 8, the dielectric of the gate insulating film 12 is interposed between the gate electrode 13 and the semiconductor substrate 11 and in a region where the gate electrode 13 and each of the diffusion layers 14 and 15 overlap in a plan view. Since the dielectric 22 having a dielectric constant lower than the dielectric constant is provided, the dielectric constant is lower in the region where the dielectric 22 is provided than in the gate insulating film 12. Therefore, the electric field intensity in that region is reduced, so that the occurrence of tunnel leak is reduced.

The provision of the dielectric 22 has substantially the same effect as the increase in the thickness of the gate insulating film 12 at that portion. This is the source / drain (or LD
D) has the same effect as the electric field in the vicinity of the diffusion layers 14 and 15 is reduced, and in a configuration in which the channel length is shortened, the roll-off effect due to the short channel effect is reduced. Voltage drop can be suppressed. This means that the threshold voltage can be used without fluctuation even for a transistor having a short channel length, which is advantageous for further miniaturization. Further, since the dielectric constant at the end of the gate insulating film 12 is reduced, the electric field is reduced as described above, and the reliability for hot carriers is increased.

Next, a configuration example in which the configuration of the semiconductor device 8 is applied to a nonvolatile semiconductor memory device will be described with reference to FIG. 12, the same components as those described with reference to FIG. 10 are denoted by the same reference numerals.

As shown in FIG. 12, the semiconductor device 9 has a semiconductor substrate 11 similar to that described with reference to FIG.
A gate insulating film 12 is formed thereon, and a floating gate 31 (corresponding to the gate electrode 13 in FIG. 10) is further formed. The gate insulating film 12 is formed to be shorter in the gate length direction than the floating gate 31, and is formed in a region between the floating gate 31 and the semiconductor substrate 11 on the side of the gate insulating film 12 in the gate length direction. A dielectric 22 having a dielectric constant lower than that of the gate insulating film 12 is formed. Diffusion layers 14 and 15 are formed in the semiconductor substrate 11 on both sides of the floating gate 31. The dielectric 22 is formed in a region where at least the floating gate 13 and the respective diffusion layers 14 and 15 overlap in plan view. Further, in the present semiconductor device 9, the insulator film 32 is formed on the floating gate 31, and the control gate 3
3 are formed. The semiconductor device 9 is configured as described above.

In the semiconductor device 9 as well, since the dielectric 22 is provided, similar to the semiconductor device 4 described above,
The current leakage is reduced and the short channel effect is reduced.

Next, an example of the eighth embodiment according to the semiconductor device of the present invention will be described with reference to the schematic configuration diagram of FIG.
In FIG. 13, the same components as those described with reference to FIG. 10 are denoted by the same reference numerals.

As shown in FIG. 13, the semiconductor device 10
A dielectric 24 having a dielectric constant lower than that of the gate insulating film 12 is provided in the space 23 of the semiconductor device 7 described with reference to FIG. That is, a gate insulating film 12 is formed on the semiconductor substrate 11, and a gate electrode 13 longer than the gate insulating film 12 in the gate length direction is formed on the gate insulating film 12. A space 23 between the gate electrode 13 and the semiconductor substrate 11 is formed on the side of the gate insulating film 12 in the gate length direction. The space 23 is formed to be wider than the thickness of the gate insulating film 12 in the thickness direction of the gate insulating film 12. Further, in the space 23, the dielectric 24 is provided. Diffusion layers 14 and 15 are formed on the semiconductor substrate 11 on both sides of the gate electrode 13. The dielectric 24 is formed in a region where at least the gate electrode 13 and the respective diffusion layers 14 and 15 overlap in plan view. The semiconductor device 10 is configured as described above.

For example, the gate insulating film 12 is
Con (Si_ThreeN_Four) [Relative permittivity εSi _ThreeN_Four{6-8], acid
Tantalum fluoride (Ta_TwoO_Five) [Relative permittivity εTa_TwoO_Five$ 20 ~
25], a material having a high dielectric constant such as
For example, silicon oxide (SiO 2)_Two)
Use a material with a low dielectric constant such as [relative dielectric constant εox ≒ 4]
You.

In the semiconductor device 10, the gate electrode 13
A dielectric 24 having a dielectric constant lower than the dielectric constant of the gate insulating film 12 is formed in a region between the gate electrode 13 and the semiconductor substrate 11 and where the gate electrode 13 and each of the diffusion layers 14 and 15 overlap in plan view. Because of the provision, the dielectric constant of the region where the dielectric 24 is provided is lower than that of the gate insulating film 12. Moreover, since the dielectric 24 is formed to be thicker than the gate insulating film 12 in the thickness direction, the electric field in the region where the dielectric 24 is provided is larger than that of the semiconductor device 8 described with reference to FIG. Therefore, the occurrence of tunnel leak is greatly reduced.

In the semiconductor device 9 described with reference to FIG. 12, as described with reference to FIG.
It is desirable to form a space 23 formed widely in the thickness direction of the gate insulating film 12 and to provide a dielectric 24 in the space 23. Such a space 23 is formed and the dielectric 2
By providing the semiconductor device 4, in the semiconductor device 5, the effects of further reducing the current leakage and reducing the short channel effect can be obtained.

Although not shown, in each of the semiconductor devices 3 to 6 described with reference to FIGS. 6 to 9, a dielectric having a lower dielectric constant than the gate insulating film 12 can be formed in the space 21. When the dielectric is formed in this manner, the same operation as that of the semiconductor devices 3 to 6 can be obtained. In each of the semiconductor devices 3 to 6 described with reference to FIGS. 6 to 9, a space 23 like the semiconductor device 7 is formed instead of the space 21, and the space 23 has a dielectric constant higher than that of the gate insulating film 12. It is also possible to form low dielectrics. Even when the dielectric is formed in this manner, the semiconductor devices 3 to
The same operation as that of No. 6 is obtained.

Next, an example of the first embodiment according to the manufacturing method of the present invention will be described with reference to the manufacturing process diagram of FIG.

As shown in FIG. 14A, a gate insulating film 12 is formed on a semiconductor substrate 11. When the gate insulating film 12 is formed of silicon oxide, it is formed by oxidizing the surface of the semiconductor substrate 11 by, for example, a thermal oxidation method. In the case where the gate insulating film 12 is formed of, for example, silicon nitride (Si ₃ N ₄ ), for example, chemical vapor deposition (hereinafter referred to as CVD) is a chemical vapor deposition (CVD) process.
Silicon nitride is deposited and formed on the semiconductor substrate 11 by a method (abbreviation of position).

Thereafter, a conductive film 51 for forming a gate electrode is formed on the gate insulating film 12. The conductive film 51 is made of, for example, polycrystalline silicon doped with impurities, and is formed by, for example, a CVD method. The impurity may be introduced at the time of CVD, or may be introduced by ion implantation after forming the polycrystalline silicon film.

Thereafter, as shown in FIG. 14B, the conductive film 51 and the gate insulating film 12 are patterned to form the gate electrode 13 with the conductive film 51, and the gate insulating film 12 Leave. At this time, the exposed upper layer portion of the gate insulating film 12 is also etched. Then, the exposed portion of the gate insulating film 12 may be removed. As the patterning method, the conductive film 51 is used.
After applying a resist thereon to form a resist film, the resist film is patterned by a lithographic technique to form a resist mask 52. The gate electrode 13 is formed of the conductive film 51 by etching using the resist mask 52 as an etching mask, and the gate insulating film 12 is left under the gate electrode 13. Thereafter, the resist mask 52 is removed by, for example, ashing and cleaning.

Next, as shown in FIG. 14C, the gate insulating film 12 is selectively etched (so-called side etching) by wet etching. In this etching, the gate insulating film 12 is
The space 21 sandwiched between the gate electrode 13 and the semiconductor substrate 11 is formed on both sides of the gate insulating film 12 in the gate length direction after the gate electrode 13. It is formed in a region where the diffusion layer overlaps in plan view.

Thereafter, as shown in FIG. 14 (4), by the ion implantation method using the gate electrode 13 as a mask,
The semiconductor substrate 11 is doped with an impurity, and the diffusion layers 14 and 1 are formed in the semiconductor substrate 11 on both sides of the gate electrode 13.
5 is formed. After that, activation annealing of the diffusion layers 14 and 15 is performed. When the diffusion layers 14 and 15 are made of LDD (Lightly Doped Drain), a sidewall insulating film (not shown) is formed on the side wall of the gate electrode 13 and then the semiconductor substrate on both sides of the gate electrode 13 is formed. A high-concentration diffusion layer (not shown) may be formed on the substrate 11 via the diffusion layers 14 and 15.

In the first embodiment of the manufacturing method, after the gate electrode 13 is formed, the gate insulating film 12 is removed so as to be shorter than the gate electrode 13 in the gate length direction.
A space 21 sandwiched between the gate electrode 13 and the semiconductor substrate 11 is formed on the side of the gate insulating film 12 in the gate length direction at least in a region where the gate electrode 13 and the diffusion layers 14 and 15 overlap in plan view. Therefore, the dielectric constant of the region where the space 21 is provided is lower than that of the gate insulating film 12. Therefore, the electric field intensity in that region is reduced, so that it is possible to form a semiconductor device in which the occurrence of tunnel leak is reduced.

In the first embodiment of the manufacturing method, a manufacturing method for forming the space 21 wide in the thickness direction of the gate insulating film 12 will be described with reference to a manufacturing process diagram of FIG.
In FIG. 15, the same components as those described with reference to FIG. 14 are denoted by the same reference numerals.

As shown in FIG. 14A, a gate insulating film 12 is formed on a semiconductor substrate 11 in the same manner as described with reference to FIGS. Is formed. Next, the conductive film 51 and the gate insulating film 12 are patterned using a lithographic technique and an etching technique to form a gate electrode 13 with the conductive film 51, and the gate insulating film 12 is left under the conductive film 51. At this time, the exposed upper layer portion of the gate insulating film 12 is also etched. Then, the exposed portion of the gate insulating film 12 may be removed.

Thereafter, the resist mask 52 is removed by, for example, ashing and cleaning. Then Figure 1
As shown in (2) of FIG. 5, the gate electrode 13 on the end of the gate insulating film 12 in the gate length direction is heated by irradiating a hot wire L in, for example, an oxygen atmosphere or an atmosphere containing oxygen. The gate insulating film 12 is formed thick in the heated portion. As the heat ray L, for example, a laser beam having a wavelength easily absorbed by the silicon oxide film, for example, an excimer laser beam is used.

Thereafter, in the same manner as described with reference to FIGS. 14 (3) to 14 (4), as shown in FIG. 15 (3), the gate insulating film 12 is selectively etched by wet etching. (So-called side etching). In this etching, the gate insulating film 12 was removed so as to be shorter than the gate electrode 13 in the gate length direction, and was sandwiched between the gate electrode 13 and the semiconductor substrate 11 on both sides of the gate insulating film 12 in the gate length direction. Space 2
3 is formed in a region where the gate electrode 13 and a diffusion layer to be formed later overlap in a plan view.

After that, the semiconductor substrate 11 is doped with impurities by ion implantation using the gate electrode 13 as a mask, and the semiconductor substrate 11 on both sides of the gate electrode 13 is doped.
Then, a diffusion layer 14 and a diffusion layer 15 are formed. Subsequently, activation annealing of the diffusion layers 14 and 15 is performed. In addition,
The diffusion layers 14 and 15 are formed by LDD (Lightly Doped Drain).
), After forming a sidewall insulating film (not shown) on the side wall of the gate electrode 13, the semiconductor substrate 11 on both sides of the gate electrode 13 is formed with a high concentration through the diffusion layers 14 and 15. A diffusion layer (not shown) may be formed.

Alternatively, although not shown, before irradiating the heat rays, the gate electrode 13 is placed in a nitrogen (N ₂ ) atmosphere.
A nitride film is formed on the surface of the substrate to deactivate it. Then, the gate electrode 13 on the end of the gate insulating film 12 in the gate length direction
Is irradiated with heat rays and heated, and the gate insulating film 12
May be formed thick.

Next, another manufacturing method for forming a space similar to that described with reference to FIG. 15 will be described with reference to the manufacturing process diagram of FIG. In FIG. 16, the same components as those described with reference to FIG. 14 are denoted by the same reference numerals.

In the same manner as described with reference to FIGS. 14A to 14C, as shown in FIG. 15A, a gate electrode 13 is formed on a semiconductor substrate 11 with a gate insulating film 12 interposed therebetween. I do. Further, a space 21 sandwiched between the gate electrode 13 and the semiconductor substrate 11 on both sides of the gate insulating film 12 in the gate length direction is a region where the gate electrode 13 and a diffusion layer to be formed later overlap in plan view. Formed.

Thereafter, as shown in FIG. 16B, the surface of the gate electrode 13 is thinly oxidized to form an oxide film 71 by an oxidation method. At this time, the surface of the semiconductor substrate 11 is also oxidized (not shown). Normally, polysilicon is more easily oxidized than single-crystal silicon constituting semiconductor substrate 11, so oxide film 71 formed on the surface of gate electrode 12 made of polysilicon is thicker than an oxide film on semiconductor substrate 11. It is formed. Next, the oxide film 71 is selectively removed by etching. As a result, the gate insulating film 12 is located between the semiconductor substrate 11 and the gate electrode 13 at the end of the gate insulating film 12 in the gate length direction.
A space 23 that is wider in the thickness direction than the film thickness is formed.

Thereafter, the diffusion layers 14 and 15 are formed on the semiconductor substrate 11 on both sides of the gate electrode 13 in the same manner as described with reference to FIG. continue,
Activation annealing of the diffusion layers 14 and 15 is performed. The diffusion layers 14 and 15 are formed by using an LDD (Lightly Doped Dr.).
ain), after forming a sidewall insulating film (not shown) on the side wall of the gate electrode 13, the semiconductor substrate 11 on both sides of the gate electrode 13 is doped with a high concentration through the diffusion layers 14 and 15. (Not shown) may be formed.

In each of the other manufacturing methods of the first embodiment described with reference to FIGS. 15 and 16, the space 23 is formed wider than the gate insulating film 12 in the thickness direction. Since the electric field strength is further reduced, the occurrence of tunnel leak is greatly reduced.

Next, an example of the second embodiment according to the manufacturing method of the present invention will be described with reference to the manufacturing process diagram of FIG.

According to the manufacturing method described with reference to FIGS. 14A to 14C, as shown in FIG.
A gate electrode 13 is formed on a semiconductor substrate 11 with a gate insulating film 12 interposed therebetween, and a gate insulating film 12 in a gate length direction is formed.
Is formed between the gate electrode 13 and the semiconductor substrate 11. Further, diffusion layers 14 and 15 are formed on the semiconductor substrate 11 on both sides of the gate electrode 13.

Thereafter, as shown in FIG. 17B, a dielectric 22 is buried in the space 21. The dielectric 22
Is made of, for example, silicon oxide, and is formed by, for example, a CVD method. Therefore, the dielectric 22 is also formed on the semiconductor substrate 11 and the surface of the gate electrode 13. Therefore, if the dielectric 22 is formed only in the space 21, as shown in FIG. 17C, the semiconductor substrate 11 and the gate electrode 13 are removed by anisotropic etching except for a portion shadowed by the gate electrode 13. The dielectric 22 (the portion indicated by the two-dot chain line) formed on the upper surface and the side surface of 13 may be etched to leave the dielectric 22 in the space 21. Thereafter, diffusion layers 14 and 15 are formed on the semiconductor substrate 11 in the same manner as described with reference to FIG.

In the second embodiment of the manufacturing method, the space 2
1 is provided with a dielectric 22 having a dielectric constant lower than the dielectric constant of the gate insulating film 12, the dielectric constant of the region where the dielectric 22 is provided is lower than that of the gate insulating film 12. Therefore, similarly to the manufacturing method described in the first embodiment, the electric field intensity in the region is reduced, so that the occurrence of tunnel leak is reduced.

Further, according to the manufacturing method described in the first and second embodiments, the current leakage can be reduced and the short channel effect can be reduced by a simpler manufacturing method than the conventional manufacturing method in which the gate insulating film edge is formed thick. Reduction becomes possible. Furthermore, both the reduction of the current leakage and the suppression of the short-channel effect can be achieved simultaneously by the side etching of the gate insulating film. The number of steps can be reduced as compared with a manufacturing method in which an offset drain is formed in order to suppress the short channel effect by increasing the thickness of the film end.

After the space 23 is formed by the manufacturing method described with reference to FIGS.
It is also possible to embed the dielectric in the space 23 by the method described in (2) to (3) of FIG.

As described above, in the manufacturing method of forming the space 23 wider in the film thickness direction than the thickness of the gate insulating film 12 and then providing a dielectric in the space 23, the electric field strength of the region where the dielectric is provided is Is further reduced, so that the occurrence of tunnel leak is greatly reduced.

Next, an example in which the first and second embodiments of the manufacturing method are applied to a method of manufacturing a nonvolatile semiconductor memory device will be described with reference to FIG.
18, the same components as those in FIG. 14 are denoted by the same reference numerals.

As shown in FIG. 18A, a gate insulating film 12 formed on a semiconductor substrate 11 is used as the conductive film 51 as a conductive film for forming a floating gate.
Form on top. Next, the insulator film 6 is formed on the conductive film 51.
1 and then a conductive film 62 for forming a control gate is formed.

Next, as shown in FIG. 18B, the conductive film 62 for forming the control gate and the insulator are formed by a normal patterning method (for example, processing such as resist coating, baking, mask exposure, and development). Membrane 6
1. The conductive gate 51 for forming the floating gate is patterned to form the control gate 33, the insulator 32, and the floating gate 31.

Then, in the same manner as explained in FIG. 14 (3), as shown in FIG. 18 (3), the side portion of the gate insulating film 12 in the gate length direction is removed by etching. Floating gate 3 made of conductive film 51
A space 21 is formed between the semiconductor device 11 and the semiconductor substrate 11. In the case where a dielectric is buried in the space 21, the above-described FIG.
A dielectric (not shown) may be formed in the same manner as described in 7 (3).

As described above, the method of forming a space 23 wider than the thickness of the gate insulating film 12 or the method of forming a dielectric in the space 23 is described in the nonvolatile semiconductor memory described with reference to FIG. It is also possible to apply to the method of manufacturing the device.

In the above description, the structure in which a transistor is formed on a so-called bulk semiconductor substrate 11 and a structure in which a space is provided and a structure in which a dielectric is provided have been described.
The configuration of the present invention, that is, the configuration in which a space is provided or the configuration in which a dielectric is provided, is, for example, SOI (Silicon on Insulato).
r) It can be applied to a transistor formed in a silicon layer of a substrate or to a TFT (Thin Film Transistor). Further, the present invention can be applied to a transistor having a so-called double gate structure or a transistor having a double floating gate structure. In that case, the present invention can be applied to both the gate insulating film of the upper gate and the gate insulating film of the lower gate. Incidentally, the description of the present invention,
Although the structure and the manufacturing method thereof are shown taking the case of a silicon semiconductor as an example, the present invention is not limited to the case of a silicon semiconductor. That is, gallium arsenide (GaAs)
The same applies to compound semiconductors and the like.

[0098]

As described above, according to the semiconductor device of the present invention, since a space is formed on the side of the gate insulating film in the gate length direction below the gate electrode, the gate is formed in the region where the space is formed. The dielectric constant is lower than that of the insulating film. Therefore, the electric field intensity in that region is reduced, so that the occurrence of tunnel leak can be reduced. Also,
According to the configuration in which the space is formed wider in the thickness direction than the gate insulating film, the electric field intensity in the region where the space is provided is further reduced, so that the occurrence of tunnel leak can be significantly reduced. Further, since the space is formed in a region where the gate electrode and the diffusion layer overlap in a plan view, the electric field overlap region is reduced when the gate insulating film and the diffusion layer are formed apart from each other. Therefore, the short channel effect can be reduced.

Further, according to the semiconductor device of the present invention in which a dielectric having a dielectric constant lower than the dielectric constant of the gate insulating film is provided on the side of the gate insulating film below the gate electrode in the gate length direction, the dielectric is formed. In the region thus set, the dielectric constant is lower than that of the gate insulating film. Therefore, the electric field intensity in that region is reduced, so that the occurrence of tunnel leak can be reduced. According to the configuration in which the dielectric is formed thicker in the thickness direction than the gate insulating film, the electric field intensity in the region where the dielectric is provided is further reduced, so that the occurrence of tunnel leak can be greatly reduced. In addition, since the dielectric material is formed in a region where the gate electrode and the diffusion layer overlap in a plan view, an electric field overlap region is formed when the gate insulating film and the diffusion layer are formed apart from each other. Become smaller. Therefore, the short channel effect can be reduced.

According to a semiconductor device having a structure in which a gate electrode portion on a space provided between a gate electrode and a semiconductor substrate is separated from a gate electrode portion on a gate insulating film via an isolation space or an isolation insulating film. The space (dielectric) provided between the gate electrode and the semiconductor substrate can reduce the electric field intensity in that region. Thereby, the occurrence of tunnel leak can be reduced. At the same time, the short channel effect can be reduced. Further, irrespective of the voltage of the gate electrode on the gate insulating film, an arbitrary voltage can be applied to the gate electrode on the space (dielectric). As a result, the effect of alleviating the electric field can be further increased, and the element performance can be improved.

According to the semiconductor device in which the diffusion layer has a low concentration of the diffusion layer on the gate electrode side, the space (dielectric) provided between the gate electrode and the semiconductor substrate has a low electric field relaxation effect. An electric field relaxation effect is obtained by the concentration diffusion layer. That is, the electric field relaxation effect is further increased.
Further, even in a semiconductor device in which a diffusion layer having a lower concentration than the diffusion layer is formed on the semiconductor substrate below the space (dielectric) provided between the gate electrode and the semiconductor substrate, the semiconductor layer is connected to the diffusion layer. The same effect as described above can be obtained.

According to the method of manufacturing a semiconductor device of the present invention,
The gate insulating film is removed so as to be shorter in the gate length direction than the gate electrode, and a space formed between the gate electrode and the semiconductor substrate is formed on the side of the gate insulating film in the gate length direction. The formed region has a lower dielectric constant than the gate insulating film. Therefore, the electric field intensity in that region is reduced, and the semiconductor device manufactured by this manufacturing method has reduced tunnel leakage. According to the method of forming a space wider than the thickness of the gate insulating film, the electric field intensity in the region where the space is provided is further reduced, so that the occurrence of tunnel leak can be greatly reduced. Further, since the space is formed in a region where the gate electrode and the diffusion layer overlap in a plan view, when the gate insulating film and the diffusion layer are formed apart from each other, the electric field overlap region should be reduced. Becomes possible. Therefore, the semiconductor device manufactured by this manufacturing method has a reduced short channel effect.

According to the manufacturing method of the present invention in which a dielectric having a dielectric constant lower than that of the gate insulating film is buried in the space, the dielectric constant is lower in the region where the dielectric is provided than in the gate insulating film. Become. Therefore, the electric field intensity in that region is reduced, and the semiconductor device manufactured by this manufacturing method has reduced tunnel leakage. According to the method of forming a dielectric thicker than the thickness of the gate insulating film, the electric field intensity in the region where the dielectric is provided is further reduced, so that the occurrence of tunnel leak can be greatly reduced. Further, since the dielectric material is formed in a region where the gate electrode and the diffusion layer overlap in a plan view, when the gate insulating film and the diffusion layer are formed apart from each other, the electric field overlap region is reduced. It becomes possible to do. Therefore, the semiconductor device manufactured by this manufacturing method has a reduced short channel effect.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram of a first embodiment according to a semiconductor device of the present invention.

FIG. 2 is an explanatory diagram of a GIDL analysis model.

FIG. 3 is a relationship diagram between a drain current and a drain voltage.

FIG. 4 is an explanatory diagram of a modified example of the semiconductor device according to the first embodiment.

FIG. 5 is a schematic configuration diagram of an application example of the semiconductor device according to the first embodiment.

FIG. 6 is a schematic configuration diagram of a second embodiment according to the semiconductor device of the present invention.

FIG. 7 is a schematic configuration diagram of a third embodiment relating to a semiconductor device of the present invention.

FIG. 8 is a schematic configuration diagram of a fourth embodiment relating to a semiconductor device of the present invention.

FIG. 9 is a schematic configuration diagram of a fifth embodiment relating to a semiconductor device of the present invention.

FIG. 10 is a schematic configuration diagram of a sixth embodiment relating to a semiconductor device of the present invention.

FIG. 11 is a schematic configuration diagram of a seventh embodiment relating to a semiconductor device of the present invention.

FIG. 12 is a schematic configuration diagram of an application example of a semiconductor device according to a seventh embodiment.

FIG. 13 is a schematic configuration diagram of an eighth embodiment relating to a semiconductor device of the present invention.

FIG. 14 is a manufacturing process diagram of the first embodiment according to the manufacturing method of the present invention.

FIG. 15 is another manufacturing step diagram of the first embodiment related to the manufacturing method.

FIG. 16 is another manufacturing process diagram of the first embodiment relating to the manufacturing method.

FIG. 17 is a manufacturing process diagram of a second embodiment according to the manufacturing method of the present invention.

FIG. 18 is an explanatory diagram of one application example to a method for manufacturing a nonvolatile semiconductor memory device.

FIG. 19 is an explanatory diagram of a problem.

[Explanation of symbols]

Reference Signs List 1 semiconductor device 11 semiconductor substrate 12 gate insulating film 13 gate electrode 14, 15 diffusion layer 21 space

Claims (30)

[Claims] In a semiconductor device, a gate electrode is formed on a semiconductor substrate via a gate insulating film, and a diffusion layer is formed on the semiconductor substrate on both sides of the gate electrode. A semiconductor device formed to be shorter in a gate length direction than an electrode, wherein a space is formed in a region lateral to the gate insulating film in the gate length direction and between the gate electrode and the semiconductor substrate. . 2. The semiconductor device according to claim 1, wherein the space is formed to be wider in a thickness direction than a thickness of the gate insulating film. 3. The semiconductor device according to claim 1, wherein the space is formed at least in a region where the gate electrode and the diffusion layer overlap in a plan view. 4. The semiconductor device according to claim 2, wherein the space is formed at least in a region where the gate electrode and the diffusion layer overlap in a plan view. 5. The semiconductor device according to claim 3, wherein the gate electrode is a floating gate, and a control gate is formed on the floating gate electrode via an insulator film. Semiconductor device. 6. The semiconductor device according to claim 4, wherein the gate electrode is a floating gate, and a control gate is formed on the floating gate electrode via an insulator film. Semiconductor device. 7. The semiconductor device according to claim 1, wherein the gate electrode portion on the space is separated from the gate electrode portion on the gate insulating film via an isolation space or an isolation insulating film. Semiconductor device. 8. The semiconductor device according to claim 2, wherein the gate electrode portion on the space is separated from the gate electrode portion on the gate insulating film via an isolation space or an isolation insulating film. Semiconductor device. 9. The semiconductor device according to claim 1, wherein said diffusion layer is formed at a low concentration on said gate electrode side. 10. The semiconductor device according to claim 2, wherein the diffusion layer has a low concentration on the gate electrode side. 11. The semiconductor device according to claim 1, wherein a diffusion layer having a lower concentration than the diffusion layer is formed on the semiconductor substrate below the space so as to be connected to the diffusion layer. Semiconductor device. 12. The semiconductor device according to claim 2, wherein a diffusion layer having a lower concentration than the diffusion layer is formed on the semiconductor substrate below the space so as to be connected to the diffusion layer. Semiconductor device. 13. A semiconductor device in which a gate electrode is formed on a semiconductor substrate via a gate insulating film, and a diffusion layer is formed in the semiconductor substrate on both sides of the gate electrode, wherein the gate insulating film is formed by the gate A dielectric constant lower than a dielectric constant of the gate insulating film in a region formed between the gate electrode and the semiconductor substrate in a side of the gate insulating film in the gate length direction and shorter than an electrode; A semiconductor device, wherein a dielectric having: is formed. 14. The semiconductor device according to claim 13, wherein the dielectric is formed to be thicker in the thickness direction than the thickness of the gate insulating film. 15. The semiconductor device according to claim 13, wherein the dielectric is formed in a region where at least the gate electrode and the diffusion layer overlap in a plan view. 16. The semiconductor device according to claim 14, wherein the dielectric is formed in a region where at least the gate electrode and the diffusion layer overlap in a plan view. 17. The semiconductor device according to claim 15, wherein said gate electrode is a floating gate, and a control gate is formed on said floating gate electrode via an insulator film. Semiconductor device. 18. The semiconductor device according to claim 16, wherein the gate electrode is a floating gate, and a control gate is formed on the gate electrode serving as the floating gate via an insulator film. Semiconductor device. 19. The semiconductor device according to claim 13, wherein a gate electrode portion on said dielectric is separated from a gate electrode portion on said gate insulating film via an isolation space or an isolation insulating film. Semiconductor device. 20. The semiconductor device according to claim 14, wherein the gate electrode portion on the dielectric is separated from the gate electrode portion on the gate insulating film via an isolation space or an isolation insulating film. Semiconductor device. 21. The semiconductor device according to claim 13, wherein the gate electrode side of the diffusion layer is formed at a low concentration. 22. The semiconductor device according to claim 14, wherein the side of the gate electrode of the diffusion layer is formed at a low concentration. 23. The semiconductor device according to claim 13, wherein a diffusion layer having a lower concentration than the diffusion layer is formed on the semiconductor substrate below the dielectric so as to be connected to the diffusion layer. Semiconductor device. 24. The semiconductor device according to claim 14, wherein a diffusion layer having a lower concentration than the diffusion layer is formed on the semiconductor substrate under the dielectric so as to be connected to the diffusion layer. Semiconductor device. 25. A step of forming a gate insulating film on a semiconductor substrate, a step of forming a gate electrode on the gate insulating film, and a step of forming a diffusion layer on the semiconductor substrate on both sides of the gate electrode. In the method for manufacturing a semiconductor device provided, after forming the gate electrode, the gate insulating film is removed so as to be shorter in the gate length direction than the gate electrode, and the side of the gate insulating film in the gate length direction is removed. Forming a space in a region between the gate electrode and the semiconductor substrate, and at least in a region where the gate electrode and the diffusion layer overlap in plan view. Method. 26. The method of manufacturing a semiconductor device according to claim 25, wherein after forming the gate electrode and before forming the space, an end of the gate insulating film in a gate length direction is heated. A method for manufacturing a semiconductor device, comprising thickening a gate insulating film in a heated portion. 27. The method of manufacturing a semiconductor device according to claim 25, wherein after forming the space, oxidizing a surface of the gate electrode, removing the oxidized portion, and forming the gate insulating layer in a thickness direction. A method for manufacturing a semiconductor device, wherein a space wider than a thickness of a film is formed. 28. A step of forming a gate insulating film on a semiconductor substrate, a step of forming a gate electrode on the gate insulating film, and a step of forming a diffusion layer on the semiconductor substrate on both sides of the gate electrode. In the method for manufacturing a semiconductor device provided, after forming the gate electrode, the gate insulating film is removed so as to be shorter in the gate length direction than the gate electrode, and the side of the gate insulating film in the gate length direction is removed. After forming a space in a region sandwiched between the gate electrode and the semiconductor substrate and at least a region where the gate electrode and the diffusion layer overlap in plan view, the gate insulating film is formed in the space. A method of manufacturing a semiconductor device, comprising: burying a dielectric having a dielectric constant lower than that of the semiconductor device. 29. The method of manufacturing a semiconductor device according to claim 28, wherein after forming the gate electrode and before forming the space, an end of the gate insulating film in a gate length direction is substantially selectively heated. And increasing the thickness of the gate insulating film in the heated portion. 30. The method of manufacturing a semiconductor device according to claim 28, wherein after the space is formed and before the dielectric is buried, the surface of the gate electrode is oxidized and the oxidized portion is removed. Forming a space wider than a thickness of the gate insulating film in a thickness direction.