JPH11308301A - Serial interface circuit - Google Patents

Abstract

(57) [Summary] [PROBLEMS] To provide a serial interface circuit capable of processing a control system packet efficiently and at high speed. A link layer circuit has a CSR (106).
, The CSR FIFO 105, and the received packet
Whether the packet is addressed to a CSR to be stored in the FIFO 105 for control or a control command or the like to be stored in the FIFO 104 for reception is determined by the address indicated by the destination offset area of the third quadlet. From the first to the third quadlets of the packet, writing is performed to both the CSR FIFO 105 and the reception FIFO 104,
If it is determined that the packet is addressed to R, the reception FI
CS causing F104 to return write pointer to previous state
And a classification circuit 108 that outputs an R-abort signal S108.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital serial interface circuit, and more particularly to a hard disk drive (HDD).
Drive), DVD (Digital Video Disk) -ROM, CD
(Compact Disk)-ROM, Tape Streamer
amer) or the like for a serial interface circuit connected to a storage device.

[0002]

2. Description of the Related Art In recent years, as an interface for multimedia data transfer, the IEEE (The Institute of Elect) has realized high-speed data transfer and real-time transfer.
ricaland Electronic Engineers) 1394, High
Performance Serial Bus has been standardized.

In the data transfer of the IEEE 1394 serial interface, a transfer operation performed in a network is called a subaction, and two subactions are defined. One is conventional Request, Acknow
Asynchronous (Asynch) for requesting and confirming receipt of ledge
ronous) forwarding, and the other is 125
Isochronous (Isoch) where data is always sent once every μs
ronous) Transfer.

As described above, an I having two transfer modes
The data in the EEE1394 serial interface is
Although transfer is performed in packet units, in the IEEE 1394 standard, the minimum data unit handled is one quadlet (q
uadlet) (= 4 bytes = 32 bits).

[0005] In the IEEE 1394 standard, computer data is normally transmitted using asynchronous transfer as shown in FIG. Asynchronous transfer is shown in FIG.
As shown in (a), there are three transition states: arbitration (arb) for acquiring a bus, packet transmission for transferring data, and acknowledgment (ack).

The execution of packet transmission is performed in a format as shown in FIG. The first quadlet of the transfer packet includes a 16-bit destination ID (destination ID) area and a 6-bit transaction label tl (transaction label).
l) area, 2-bit retry code rt (retry cod
e) area, 4-bit transaction code tcod
An e (transanction code) area and a 4-bit priority pri (priority) area. The destination ID area indicates the bus number and node number of this node, and the priority area indicates the priority level.

[0007] The second and third quadlets have a 16-bit source ID area and a 48-bit destination offset (destina- tion).
tionoffset) region. The source ID area shows the ID of the node that sent this packet, and the destination offset area shows high (High) and low (L
ow), and indicates the address of the address space of the destination node.

[0008] The fourth quadlet is composed of a 16-bit data length area and a 16-bit extended transaction code (extended tcode) area. The data length field indicates the number of bytes of the received packet, and the extended tcode field is tc.
mode is a Lock transaction
If, the actual locking action performed by the data in this packet
(Lock Action).

[0009] A header CRC (header CRC) added to the quadlet before the data field area (data field)
The area is an error detection code of the packet header. Also,
A data CRC (data CRC) area added to the quadlet after the data area (data field) is an error detection code of the data field.

As described above, in the ordinary computer data transfer performed by the asynchronous transfer,
As the protocol, SBP-2 (Serial Bus Protocol)
ol-2) is used. According to this protocol,
Targets that are storage devices
When transferring data from the (Target) to the initiator (Initiator) which is the host computer, write data from the storage device to the memory of the host computer, and when transferring data from the host computer to the target. The transfer is performed in such a manner that the storage device reads the data in the memory of the host computer.

[0011]

In a serial interface circuit, for example, a core register for isochronous communication, a bus
ent) register, unit architecture (unit
itecture) CSR (Control and Status Registers), which is a control and status register consisting of registers, etc.
Is provided.

On the IEEE 1394 serial interface, access to CSR (read / write)
Generally it was done with software. This is the CSR
This is because the software itself has it. In such a case, since all processing is performed on the CPU side as a control circuit, a request packet for access (Request) is the same reception FIFO (Fir
(s-In First-Out), the CPU sequentially reads out and performs a predetermined process.

However, from the viewpoint of reducing the load on the CPU, it is desired to implement CSR by hardware. In this case, these packets have the same FIFO.
Is processed in a low efficiency, and there is no point in realizing with hardware for the purpose of high speed and efficiency.

The present invention has been made in view of such circumstances, and an object of the present invention is to provide a serial interface circuit capable of processing a control system packet efficiently and at high speed.

[0015]

To achieve the above object, the present invention relates to a serial interface circuit for receiving a packet transferred on a serial interface bus, comprising a control and status register and an access to the register. First storage means for storing a request packet for requesting, a second storage means for storing a control packet, and a control packet stored in the register or the second storage means. And a control circuit for performing the processing.

Further, the present invention is a serial interface circuit for receiving a packet added with supply destination information transferred through a serial interface bus, and requests a control and status register and access to the register. First storage means for storing request packets, second storage means for storing control packets,
When the received packet is received and it is determined from the destination information that the received packet is the request packet, the request packet is written to the first storage means, and when the received packet is determined to be the control packet, A classification circuit for writing the control packet into the second storage means,
A control circuit for performing processing in accordance with the content of the control packet stored in the register or the second storage means.

Further, in the present invention, the classification circuit causes the received packet to be written into the first and second storage means until the destination information of the received packet is determined. If it is a packet,
The writing of the packet in the second storage means is stopped.

Further, in the present invention, the sorting circuit stops writing in the second storage means and returns a write pointer to a state before the writing.

In the present invention, the received packet is an asynchronous packet, and the destination information is information set in a destination offset area.

Further, in the present invention, the second storage means, upon receiving the control signal, writes the packet regardless of the write stop instruction of the sorting circuit or the write pointer change instruction.

The control signal is a signal input from the outside.

Further, according to the present invention, there is provided an internal register in which control information can be set from a control circuit, and the second storage means writes the data in the classification circuit when the control information is set in the internal register. The packet is written regardless of the stop instruction or the write pointer change instruction.

According to the present invention, a packet transferred on the serial interface bus is input to, for example, a classification circuit. The discrimination circuit determines, for example, whether the packet is a request packet for requesting access to the control and status register or a control packet such as a command based on the destination information added to the received packet. At this time, if it is determined that the received packet is the request packet, the request packet is written to the first storage means. If it is determined that the received packet is a control packet, the control packet is stored in the second storage means. Written in the means. In the classification circuit,
For example, the received packet is written to both the first and second storage units until the supply destination information of the received packet is determined. If the result of the determination is that the received packet is a request packet, the writing of the packet in the second storage means is stopped, and the write pointer of the second storage means is returned to the state before the writing.

Further, according to the present invention, when the second storage means is given as an external control signal or as control information set in an internal register by the control circuit, the classification circuit of the classification circuit is provided. Packet writing is performed regardless of a write stop instruction or a write pointer change instruction. As a result, the control circuit can access the control and status registers by software.

[0025]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment FIG. 1 is a block diagram showing a first embodiment of the IEEE 1394 serial interface circuit according to the present invention. This serial interface circuit is configured to transfer computer data handled in asynchronous communication. Therefore, FIG.
1 does not show a specific configuration of the isochronous communication system circuit.

The serial interface circuit comprises a link / transaction layer integrated circuit 10, a physical layer circuit 20, a hard disk driver (HDD) controller 30 (not shown) as a storage device, and a local processor 40 as a host computer. I have.

The link / transaction layer integrated circuit 10 is formed by integrating the link layer circuit 100 and the transaction layer circuit 120, and controls the asynchronous transfer under the control of the local processor 40, as well as the physical layer circuit. 20.

As shown in FIG. 1, the link layer circuit 100 comprises a link core (Link Core) 101, a CPU interface circuit (Sub-CPU I / F) 102, and a transmission FIFO (AT-AT) used for asynchronous communication. FIFO) 103, receiving FIFO (AR-FIFO) 104, CSR FIFO 10
5, a CSR 106, an OR gate 107, a classification circuit (DeMux) 108 for determining a received packet, a resolver (Resolver) 109 for self ID, and a control register (Co
ntrol Registers (hereinafter referred to as CR) 110.

The link core 101 includes a transmission circuit and a reception circuit for asynchronous communication packets and isochronous communication packets to which commands and computer data are transferred, and a physical layer circuit 20 for directly driving these packets on the IEEE 1394 serial bus BS. It is composed of an interface circuit, a cycle timer reset every 125 μs, a cycle monitor and a CRC circuit. Further, it performs a transmission process of computer data read from a hard disk (not shown) and generated by the transaction layer circuit 120 as a predetermined transmission packet. For example, a transaction controller 1 of a transaction layer circuit 120 described later
Upon receiving a notification that there is data to be sent from 26, the 1394 serial bus is arbitrated via the physical layer circuit 20 to secure the bus. In FIG. 1, the FIFO and the like of the isochronous communication system are omitted as described above.

The CPU interface circuit 102 includes a local processor 40, a transmission FIFO 103, and a reception FIFO 103.
The arbitration of writing and reading of the asynchronous communication packet with the IFO 104 and the arbitration of transmission and reception of various data between the local processor 40 and the CSR 106 and the CR 110 are performed. For example, an IEEE 1394 interface bus BS is transmitted from a host computer as an initiator, and a command for controlling a hard disk as a storage device stored in a reception FIFO is transmitted to the local processor 40.
Data transmission between the CSR 106 of the set data of the R 106 and the local processor 40 is performed.

Data for activating the transaction layer circuit 120 for transmitting and receiving computer data is transmitted from the local processor 40 to the CPU.
It is set in the CR 110 via the interface circuit 102.

The transmission FIFO 103 includes IEEE13
Asynchronous communication packets to be transmitted to the N. 94 serial bus BS are stored.
Given to.

Further, the receiving FIFO 104 is an IEEE
Asynchronous communication packets transmitted through the 1394 serial bus BS, for example, commands for controlling a hard disk as a storage device and the like are stored by the classification circuit 108. Also, the classification circuit 108
The CSR-abort signal S108 from the OR gate 107
Actively received through the receiving device, for example, a received packet stored up to about 3 quadlets is transmitted to another receiving FIFO.
O, that is, the write pointer is returned to the original position to be stored in the CSR FIFO 105 (return to the pointer position before the start of storage of the packet). Also, OR
FIFO-cont signal F from outside via gate 107
When the CNT is actively received, even if the CSR-abort signal S108 from the classification circuit 108 is actively received via the OR gate 107, the storage of the received packet is not stopped and all are stored. Thus, control by software can be performed by the local processor 40 as in the related art.

The CSR FIFO 105 includes a CSR 10
6 is stored by the classification circuit 108. Access to the CSR 106 is performed by storing the packet in the CSR FIFO 105.

The classification circuit 108 determines whether the received packet is a CSR
A destination offset (destination offset) of the third quadlet shown in FIG. 4B indicates whether the packet is a packet addressed to a CSR to be stored in the FIFO 105 for control or a control command or the like to be stored in the FIFO 104 for reception. ) It can be determined by the address indicated by the area. Therefore, the separation circuit 1
08 is the CSR FIFO 105 and the reception FIFO 10 for the first to third quadlets of the received packet.
4 is written, and if it is determined that the packet is addressed to the CSR, a CSR-abort signal S108 is output as active. In addition, the receiving F
If it is determined that the packet is destined for the IFO 104, the CSR-abort signal S108 is not output. At this time, the pointer of the CSR-FIFO 105 is not determined.
In addition, the classification circuit 108 determines the transaction code tcode (Transaction code) in the first quadred of the asynchronous communication packet via the link core 101.
And transaction label tl (Transaction labe
l) is checked, the host computer as the initiator discriminates whether the packet is a response packet (Response Packet) or another packet from the target transaction layer circuit to the target transaction layer circuit, and only the response packet is determined in the transaction layer. Input to the circuit 120.

FIG. 2 is a timing chart showing an example of an operation of writing a packet to the CSR FIFO 105 and the reception FIFO 104 by the classification circuit 108 when a packet addressed to CSR is received.

The received data is stored in the receive FIFO by a write signal and a confirm signal. The write signal controls the write pointer and the confirm signal controls the confirmation pointer. Therefore, the data to the FIFO will be determined by the confirm signal.

In the example of FIG. 2, "He" shown in FIG.
Since the address of the access destination is determined at the writing time t1 of the ader 3rd ", if it is determined that this packet is addressed to CSR, at t2 before the checking time t3,
As shown in (d), the CSR-abort signal S108 is set to the active high level. FIFO1 for reception
In 04, upon receiving this CSR-abort signal S108,
Ignore the subsequent confirm signal and return the alternate write pointer to its previous state.

The resolver 109 is connected to the self-I which has been transmitted through the IEEE 1394 serial interface bus BS.
The D packet is analyzed and stored in the CR 110. It also has functions such as error checking and counting the number of nodes.

The transaction layer circuit 120
It has a function of automatically transmitting and receiving data from a computer peripheral device, for example, a hard disk as an asynchronous packet based on the SBP-2 (Serial Bus Protocol-2) standard. Further, the transaction layer circuit 120 has a retry function and a split timeout detection function. After sending the request packet, the retry function
When the busy ^* Ack code is returned, this function retransmits the corresponding request packet. When retransmitting a packet, the 2-bit rt area in the first quadred of the transmission packet is set from “00” to “01”, and the core link 101 is notified and transmitted. The split timeout detection function is a function for detecting a timeout until a response packet is returned.

This transaction layer circuit 120
Is a transport data interface circuit 121,
Request packet generation circuit (SBPreq) 122, response packet decode circuit (SBPRsp) 123, request FIFO (Request F
IFO: ADPTF) 124, Response FIFO (Response FIFO: ADP)
RF) 125, and the transaction controller 12
6. Then, the request packet generation circuit 122, the response packet decode circuit 123, the request F
A data processing circuit AD is provided by the I / O 124, the response FIFO 125, and the transaction controller 126.
P is configured.

The transport data interface circuit 121 arbitrates the transmission and reception of data between the HDD controller 30, the request packet generation circuit 122 and the response packet decode circuit 123.

The request packet generation circuit 122 has a link
Upon receiving an instruction to start data transfer from the CR 110 of the layer circuit 100, in the case of transmission (writing), the transport data interface circuit 1 according to the SBP-2 standard.
21 so that the computer data recorded on a hard disk (not shown) obtained through
Divided into at least data and the transaction label tl
(= A) is added to the request F
It is stored in the IFO 124. In the case of reception (reading), according to the SBP-2 standard, a 1394 block read request command (Block read Request Command) corresponding to the specified address and data length is stored in the request FIFO 124 as one or more packets. I do.

The response packet decode circuit 123 reads the data stored in the response FIFO 125 at the time of reception, removes the 1394 header, and transfers the data at a predetermined timing to the transport data interface circuit 12.
1 to the HDD controller 30.

The request FIFO 124 stores packetized transmission data when transmitting (writing), and stores a 1394 block read request command when receiving (reading).

In the case of reception (reading), the response FIFO 125 stores reception data transmitted from the host computer via the 1394 serial bus BS.

The transaction controller 126
The packetized transmission data stored in the request FIFO 124 at the time of transmission, and the request FIFO 12 at the time of reception.
4 controls the output of the 1394 block read request command (request packet) stored in No. 4 to the link core 101 of the link layer core circuit 100. Also, when sending,
Upon receiving a response packet from the classification circuit 108 of the link layer circuit 100, the retry code rcode is set to C
The data is written into R110, and at the time of reception, the response packet from the classification circuit 105 is stored in the response FIFO 125.

Next, the operation of the above configuration will be described focusing on the classification of the classification circuit 108 and the operation of storing the packet in the FIFO.

For example, when a 1394
The packet data based on the SBP-2 standard transferred through the serial bus BS is transmitted to the physical layer circuit 20,
The data is input to the classification circuit 108 via the link core 101 of the link layer circuit 100.

The classification circuit 108 receives the received packet and receives a response packet (Response) from the host computer to the target transaction layer circuit.
Packet) or the received packet is a FIFO1 for CSR.
It is determined whether the received packet is a packet addressed to a CSR to be stored in the receiving FIFO 05 or a packet such as a control command to be stored in the receiving FIFO 104. At this time, first, the transaction code tcode (Transaction (Transaction) in the first quadred of the asynchronous communication packet is used.
code) and transaction label tl (Transaction
label) is checked, and if it is determined that the received packet is not a response packet, the received packet is converted to the CSR FIFO 1 by the address indicated by the destination offset area of the third quadlet.
It is determined whether the received packet is a packet addressed to a CSR to be stored in the receiving FIFO 05 or a packet such as a control command to be stored in the receiving FIFO 104.

At the time of this sorting operation, the sorting circuit 108 converts the first to third quadlets of the received packet into the CSR FIFO 105 and the reception FIFO 10.
4 is written to both. If the classification circuit 108 determines that the data is addressed to the CSR, the CSR-
The abort signal S108 is active and output to the receiving FIFO 104 via the OR gate 107.

In the receiving FIFO 104, the classification circuit 10
The CSR-abort signal S108 from the OR gate 10
7, the received packet stored up to about 3 quadlets, for example, is received by another receiving FI.
As what is to be stored in the FO, that is, in the CSR FIFO 105, the write pointer is returned to the pointer position before the start of storing the packet.

The CSR FIFO 105 includes C
The packet to the SR is written continuously and automatically
, For example, writing is performed.

On the other hand, if the classification circuit 108 determines that the received packet is not addressed to the CSR but is a packet such as a control command to be stored in the reception FIFO 104, the classification circuit 108 outputs a CSR-abor
t signal S108 is not output, and at this time, CSR-FI
The pointer of the FO 105 is not fixed. And the receiving F
The received packet is continuously written in the IFO 104.

ORB stored in reception FIFO 104
The received data such as (Operation Request Block)
The data is input to the local processor 40 via the interface circuit 102. In the local processor 40, the CP
The register for the transaction layer circuit of the CR 110 is initialized through the U interface circuit 102 according to the contents of the ORB. As a result, the transaction layer circuit 120 is activated.

In the activated transaction layer circuit 120, the request packet generation circuit 122 sends the request to the HDD via the transport interface circuit 121.
A request for data from the controller 30 is started.
On request, the transport interface circuit 12
The transmission data transmitted through the request packet 1 is automatically stored in the request FIFO 124 with the 1394 header in which the transaction label tl (= a) or the like is specified in the request packet generation circuit 122 in accordance with the SBP-2 standard. You.

The read request command packet stored in the request FIFO 124 is sent by the transaction controller 126 to the link core 101 of the link layer circuit 100. The link core 101 arbitrates the 1394 serial bus BS via the physical layer circuit 20.
As a result, if the bus is acquired, a read request packet (Read Request Packet) is transmitted to the host computer via the physical layer circuit 20 and the 1394 serial bus BS.

After transmission, an Ack code for a read request packet from the host computer and a read response packet (Read R) including data of a designated data length.
esponse Packet) is sent to the physical layer circuit 20 and the link core 10 of the link layer circuit 100.
The signal is input to the classification circuit 108 through the line 1.

In the classification circuit 108, the transaction code tcode and the transaction label tl of the received packet are checked, and it is determined that the received packet is a response packet (Response Packet) from the host computer to the target transaction layer circuit. Then, the response packet is input to the transaction controller 126 of the transaction layer circuit 120.

In the transaction controller 126, the response packet from the classification circuit 108 is
It is stored in O125. The data stored in the response FIFO 125 is read by the response packet decoding circuit 123, the 1394 header is removed, and the data is output to the HDD controller 30 via the transport data interface circuit 121 at a predetermined timing.
By repeating the above operation, the operation of writing (receiving) the computer data to the storage device (hard disk) is performed.

As described above, according to the first embodiment, the CSR 106 is provided in the link layer circuit 100 of the link transaction integrated circuit 10, the CSR FIFO is provided, and the received packet is
Whether the packet is addressed to a CSR to be stored in the SR FIFO 105 or a control command packet to be stored in the reception FIFO 104 is determined by a destination offset (destinati) of the third quadlet.
on offset) area, the first to third quadlets of the received packet are
A discriminating circuit that writes data to both the CSR FIFO 105 and the reception FIFO 104 and outputs a CSR-abort signal S108 that causes the reception FIFO 104 to return the write pointer to the previous state when it is determined that the packet is addressed to the CSR. Because of the provision of 108, there is an advantage that a serial interface circuit that can process control packets efficiently and at high speed can be realized.

Further, an external FIFO-cont signal FC
When NT is actively received, C from the classification circuit 108 is received.
Even if the SR-abort signal S108 is actively received via the OR gate 107, the received packets are all stored without stopping the storage, so that the local processor 40 can perform software control by the local processor 40 in the conventional manner. is there.

In the classification circuit 108, the first packet of the asynchronous communication packet via the link core 101 is transmitted.
Transaction code tcode in Quadred
(Transaction code) and transaction label tl
Check the (Transaction label) and send a response packet (Response) from the host computer as the initiator to the target transaction layer circuit.
Packet) or another packet, and only the response packet is input to the transaction layer circuit 120. For example, a fatal error occurs on the transaction layer circuit 120 side and the data Even if the read / write operation is stopped, it is not possible to read the next input command of the data, and the command can be smoothly received regardless of the data read / write state. There are advantages.

Second Embodiment FIG. 3 is a block diagram showing a second embodiment of the IEEE 1394 serial interface circuit according to the present invention.

In the second embodiment, instead of receiving the FIFO-cont signal FCNT from the outside, the local processor 40 sets the control information in the CR 110 via the CPU interface circuit 102 as the control information, and sets this as the FIFO information.
The O-cont signal FCNT is provided to the control system of the receiving FIFO 104.

According to the second embodiment, the first
The same effect as that of the embodiment can be obtained.

[0067]

As described above, according to the present invention,
There is an advantage that control system packets can be processed efficiently and at high speed.

Further, according to the present invention, by providing the second storage means as a control signal from the outside or as control information set in an internal register by the control circuit, control and status by the control circuit are performed. Access to the register can be processed by software.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of an IEEE 1394 serial interface circuit according to the present invention.

FIG. 2 is a timing chart illustrating an example of an operation of writing a packet to a CSR FIFO and a reception FIFO by a classification circuit when a packet addressed to a CSR is received;

FIG. 3 is a block diagram showing a second embodiment of the IEEE 1394 serial interface circuit according to the present invention.

FIG. 4 is a diagram for explaining asynchronous transfer of the IEEE 1394 standard.

[Explanation of symbols]

10 link / transaction layer integrated circuit, 20
... Physical layer circuit, 30 ... HDD controller, 40 ... Local processor, 100, 100a ... Link layer circuit, 101 ... Link core, 102 ... CP
U interface circuit, 103: Asynchronous transmission FIFO, 104: Asynchronous reception FIFO, 1
05 ... CSR FIFO, 106 ... CSR, 107 ... O
R gate, 108: classification circuit, 109: resolver, 11
0: control register, 120: transaction layer circuit, 121: transport data interface circuit, 121: request packet generation circuit, 123:
Response packet decoding circuit, 124 ... FIFO for request,
125 ... Response FIFO, 126 ... Transaction controller.

Claims (12)

[Claims] 1. A serial interface circuit for receiving a packet transferred on a serial interface bus, comprising: a control and status register; and first storage means for storing a request packet for requesting access to the register. A serial interface circuit comprising: a second storage unit in which a control packet is stored; and a control circuit that performs a process according to the content of the control packet stored in the register or the second storage unit. 2. A serial interface circuit for receiving a packet added with supply destination information transferred through a serial interface bus, wherein a control and status register and a request packet for requesting access to the register are stored. A first storage unit for storing the control packet, a second storage unit for storing the control packet, and a request when the received packet is determined to be the request packet from the supply destination information. A classification circuit for writing a packet to the first storage means and writing the control packet to the second storage means when it is determined that the control packet is the control packet; and the register or the second storage means Serial interface circuit having a control circuit for performing processing according to the contents of the control packet stored in the means 3. The discriminating circuit causes the received packet to be written into the first and second storage means until the destination information of the received packet is determined, and as a result of the determination, the received packet is the request packet. 3. The serial interface circuit according to claim 2, wherein writing of the packet in said second storage means is stopped. 4. The serial interface circuit according to claim 3, wherein said sorting circuit stops writing in said second storage means and returns a write pointer to a state before said writing. 5. The receiving packet is an asynchronous packet, and the destination information is a destination packet.
3. The serial interface circuit according to claim 2, wherein the information is information set in a destination offset area. 6. The received packet is an asynchronous packet, and the destination information is a destination packet.
5. The serial interface circuit according to claim 4, wherein the information is information set in an offset area. 7. The serial interface circuit according to claim 3, wherein said second storage means, upon receiving a control signal, writes a packet regardless of a write stop instruction of said sorting circuit. 8. The serial interface circuit according to claim 4, wherein said second storage means, upon receiving a control signal, writes a packet irrespective of an instruction to change a write pointer of said sorting circuit. 9. The serial interface circuit according to claim 7, wherein said control signal is a signal input from the outside. 10. The serial interface circuit according to claim 8, wherein said control signal is a signal inputted from outside. 11. An internal register capable of setting control information from a control circuit, wherein the second storage means, when the control information is set in the internal register, in response to a write stop instruction of the sorting circuit. 8. The serial interface circuit according to claim 7, wherein packet writing is performed. 12. An internal register capable of setting control information from a control circuit, wherein the second storage means instructs a change of a write pointer of the classification circuit when the control information is set in the internal register. 9. The serial interface circuit according to claim 8, wherein packet writing is performed irrespective of the condition.