JP2002244991A - Multi-initiator control device and method - Google Patents

Abstract

(57) [Problem] To provide a multi-initiator control device capable of executing a command processing sequence for two or more devices. A multi-initiator control device for communicating with each of a plurality of devices connected via a transmission line in units of packets, wherein the packet filter analyzes a received packet and outputs a result of the analysis. A plurality of command control circuits each for controlling a command processing sequence between the corresponding device, a multi-control circuit for granting sequence execution permission to one of the plurality of command control circuits, A packet processing circuit that generates and transmits a packet having information output by the command control circuit, and outputs a received packet in accordance with an analysis result output by the packet filter.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sequence processing technique for a protocol used when a command or data is transmitted between a computer and a peripheral device via a transmission line.

[0002]

2. Description of the Related Art As a next-generation interface for connecting AV (audio-visual) devices, computer devices, and the like, I.
The EEE1394 system has attracted attention. This is IEEE
This is because asynchronous communication and isochronous communication are defined in the E1394 system. Asynchronous communication is used for communication that requires more reliability than real-time operation, such as data transfer between a computer and a recording medium. Isochronous communication is used for communication that requires real-time performance rather than reliability, such as AV data of moving images. Therefore, for example, computer data can be transferred to a DVD-RAM (digital versatile disc-
When data is stored in a random access memory (drive) or the like, or computer data that has been recorded is read from a DVD-RAM drive, data is generally transmitted by asynchronous communication.

[0003] Devices such as computers (initiators (in
An SBP-2 (serial bus protocol-) is used as a protocol for performing IEEE 1394 asynchronous communication between a peripheral device (target) and a peripheral device (target).
2) There is. Hereinafter, a command processing sequence when a computer reads data from a target such as a DVD-RAM drive in accordance with SBP-2 will be described.

[0004] SBP-2 commands are READ, WR
Command type commands such as ITE, LOGIN, QU
ERY LOGIN, ABORT TASK, ABOR
It can be divided into a management (task management) command such as TTASK SET.

FIG. 9 is an explanatory diagram showing a command processing sequence for executing a LOGIN command which is a management command. Referring to FIG.
The command processing sequence of the IN command will be described.

(1) The initiator is a QRRQ (quadle
t read request) to obtain target specific information (e.g., device information) by issuing a packet. Generally, this entire unique information is stored in the configuration ROM (conf
igROM), and the unique information includes the address of the target MANAGEMENT_AGENT register.

(2) In response to the QRRQ packet from the initiator, the target transmits the configROM data to the
This is returned to the initiator as an RRS (quadlet read response) packet. These processes (1) and (2) in which the QRRQ packet and the QRRS packet are transmitted continue until the initiator acquires all the data in the configROM.

[0008] (3) The initiator uses BWRQ (block
A write request) packet is issued, and the ORB (operati
on request block)
Write to MANAGEMENT_AGENT register. The ORB is prepared in advance by the initiator, and MANAGEMENT_
The AGENT register stores the target CSR (control andst
atus register) space.

(4) In response to the BWRQ packet from the initiator, the target responds to the WRS (write response
e) Return the packet to the initiator.

(5) The target issues a BRRQ (block read request) packet to the initiator to request that the initiator transmit the ORB to the target. The ORB is located at the address stored in the MANAGEMENT_AGENT register.

(6) In response to the BRRQ packet from the target, the initiator responds to a BRRS (block read r
esponse) Return the packet to the target. The ORB is stored in the data field of the BRRS packet. In this way, the ORB is transmitted from the initiator to the target.

(7) The target receives an O signal from the initiator.
The RB is received, and the contents of the received ORB are analyzed.

(8) If the received ORB is L
When the LOGIN command is found, the LOGIN command is executed. Login Response at command execution
Shows the base address of the COMMAND_AGENT register.

(9) After the execution of the LOGIN command is completed, the target creates status information indicating the execution result of the LOGIN command.

(10) The target transmits status information to the initiator by issuing a BWRQ packet. The status information is stored at a predetermined address specified by the ORB (Status_FIFO address of the initiator).

(11) In response to the BWRQ packet from the target, the initiator returns a WRS packet to the target.

(12) The target determines whether or not the rCode of the WRS packet from the initiator is resp_complete. RC of WRS packet from initiator
When ode is resp_complete, a series of command processing sequences related to the LOGIN command is completed.

FIG. 10 is an explanatory diagram showing a command processing sequence for executing a command-based READ command. The sequence in FIG. 10 is executed after the processing sequence of the LOGIN command described with reference to FIG. 9 ends. The command processing sequence of the READ command will be described with reference to FIG.

(21) The initiator creates an ORB indicating a READ command. O for READ command
The RB defines information necessary for executing the READ command, such as the number of data, the maximum packet length, the transfer direction, and the transfer method.

(22) The initiator sets the QWRQ (quad
let write request) packet to target AGENT_RE
Write to the SET register and initialize it. AGENT_
The RESET register is defined in the target CSR space.

(23) The target returns a WRS packet to the initiator in response to the QWRQ packet from the initiator.

(24) The initiator issues a BWRQ packet to write the address of the memory storing the ORB into the ORB_POINTER register. In addition,
The ORB_POINTER register is defined in the target CSR space.

(25) The target returns the WRS to the initiator in response to the BWRQ from the initiator.

(26) The target issues a BRRQ packet to request that the initiator send an ORB to the target. The ORB is located at the address stored in the ORB_POINTER register, that is, at its memory address in the initiator.

(27) In response to the BRRQ packet from the target, the initiator returns a BRRS packet to the target. The ORB is stored in the data field of the BRRS packet. In this way, ORB
Is sent from the initiator to the target.

(28) The target receives the ORB from the initiator and analyzes the contents of the received ORB.

(29) When the target knows that the received ORB indicates a READ command, the target executes the READ command. By executing the READ command, the following (30) and (31) are repeated. This is because when the size of the data to be transferred is large, the data is divided into a plurality of packets and transferred. The data to be transferred is prepared by the target.

(30) The target issues a BWRQ packet and stores the data at the address specified by the ORB.

(31) In response to the BWRQ packet from the target, the initiator returns a WRS packet to the target. The processes (30) and (31) constitute one transaction. After it is confirmed that one transaction has been completed normally, the next transaction is executed.

(32) After the data transfer processing sequence ends normally, the target creates status information indicating the execution result of the READ command.

(33) The target transmits status information to the initiator by issuing a BWRQ packet. The status information is stored at a predetermined address specified by the ORB.

(34) In response to the BWRQ packet from the target, the initiator returns a WRS packet to the target.

(35) The target determines whether or not the rCode of the WRS packet from the initiator is resp_complete. RC of WRS packet from initiator
If ode is resp_complete, a series of command processing sequences for the READ command is completed.

Although not shown in the figure, FIGS.
At 0, upon receiving a packet from the initiator, the target returns an ACK (Acknowledge) packet to the initiator. Similarly, upon receiving a packet from the target, the initiator returns an ACK packet to the target.

When the initiator and the target have successfully received a write request packet (for example, a BWRQ packet or a QWRQ packet), the initiator and the target return an ACK packet having a code "Ack_complete" indicating that the packet has been successfully received. In this case, the process proceeds to the next process without returning the WRS packet. Initiator and target have an ACK with a code of “Ack_pending”
When returning a packet, a WRS packet is returned. If the initiator and the target cannot receive the packet, the “Ack_bus” indicates that the packet cannot be received.
ACK packet having the code "y". In the data transfer sequence, the BWRQ from the target is returned.
If the initiator returns an ACK packet having the code "Ack_busy" to the target for the packet, the target retransmits the BWRQ packet to the initiator.

As described above, data transfer processing can be performed between the initiator and the target. SB
In P-2, a maximum of 63 initiators can be connected to one target on one bus.

FIG. 11 is a block diagram showing a configuration of a conventional sequence processing device 90 for processing SBP-2. The physical layer controller 91 has functions such as initialization of the IEEE 1394 bus 20, arbitration, control of bias voltage, and the like. The link core circuit 92 receives a packet on the bus 20 via the physical layer controller 91. The link core circuit 92 performs generation / detection of an error detection code for a packet, addition of a code to the packet, detection of a code (for example, code detection of an ACK packet), and the like. Further, the link core circuit 92 includes the physical layer controller 9.
1 to output the packet to the bus 20. Further, the link core circuit 92 has a retry function of retrying the transfer of the packet when the transfer of the packet fails.

The packet filter 93 receives the packet output from the link core circuit 92 and analyzes the contents of the header field of the packet. Packet filter 9
3 is a sequence control circuit 99 according to the analysis result.
Alternatively, it supplies a control signal to the transfer control circuit 96 and outputs a received packet to the packet processing circuit 95. The packet processing circuit 95 is controlled by the sequence control circuit 99 or the transfer control circuit 96, processes the input packet, outputs a command to the command reception buffer 97, or receives the command via the DMA (direct memory access) bus 6. Output data to the outside. Sequence control circuit 99
Performs execution and control of a command processing sequence for one connected initiator.

As described above, the conventional sequence processing apparatus shown in FIG. 11 performs a command processing sequence with one initiator.

[0040]

In order to perform the sequence processing of two or more initiators in the conventional sequence processing apparatus, the sequence processing for the second and subsequent initiators and the management of each initiator are all performed by firmware. Needed. In this case, the CPU
(Central processing unit) becomes extremely heavy.

In particular, when a large amount of data handled by an optical disk device such as a DVD-RAM needs to be transferred, the load on the CPU increases dramatically. As a result, the overhead of the firmware executed by the CPU increases, and it is extremely difficult to realize a high effective transfer rate as a high-speed serial bus interface, which should be originally realized by adopting the IEEE 1394 system. Further, if the firmware performs all such processing, the load on the CPU increases, and it has not been possible to incorporate the sequence processing device into another system such as an optical disk device.

As described above, the conventional sequence processing apparatus can actually cope only with a single initiator. For this reason, the scalability is low, and it cannot be used very effectively in a network environment in which a plurality of initiators are connected.

An object of the present invention is to provide a multi-initiator control device capable of executing a command processing sequence for two or more devices.

[0044]

Means for Solving the Problems In order to solve the above-mentioned problems, the means according to the first aspect of the present invention communicates with each of a plurality of devices connected via a transmission line in units of packets. A multi-initiator control device for transmitting a packet to be transmitted to the transmission line, receiving a packet from the transmission line, performing error detection and outputting, and a link core circuit that receives the packet. A packet filter for analyzing a packet and outputting a result thereof; a plurality of command control circuits each for controlling a command processing sequence between the corresponding device; and executing a sequence to one of the plurality of command control circuits. A multi-control circuit for giving permission and a packet having information output from the command control circuit for which permission is given are generated as the packet to be transmitted. A packet processing circuit that outputs a packet received and output by the link core circuit according to an analysis result output by the packet filter, and a packet output by the packet processing circuit. And a CPU (central processing unit) for executing the commands included in.

According to the first aspect of the present invention, a packet is transmitted from the multi-initiator control device, and the multi-initiator control device can execute a command included in the packet transmitted by the device in response to the packet. Since the execution of such a command processing sequence is performed by the command control circuit, the CPU does not participate in the execution of the command processing sequence. Further, the multi-control circuit controls which device the multi-initiator control device performs a command processing sequence with. Thus, the load on the CPU can be reduced.

According to a second aspect of the present invention, in the multi-initiator control apparatus according to the first aspect, each of the plurality of command control circuits outputs a command from a corresponding device and outputs a command between the corresponding device. The multi-control circuit stores information necessary for a processing sequence and outputs the information when the sequence execution permission is given. The multi-control circuit includes a packet included in a packet received and output by the link core circuit. The information required for the command processing sequence between the device and the device that transmitted the, according to the output of the packet filter, to output and store the command control circuit among the plurality of command control circuits corresponding to the device, The packet processing circuit generates a packet having information output from the command control circuit to which the sequence execution permission has been given. Outputs Te, a packet device has output corresponding to the command control circuit in response thereto,
It receives and outputs.

According to the second aspect of the present invention, it is possible to efficiently control a plurality of command control circuits and process a series of transactions in a command processing sequence.

According to a third aspect of the present invention, in the multi-initiator control device according to the first aspect, each of the plurality of command control circuits stores information of a command fetch request packet transmitted from a corresponding device. ,
When the sequence execution permission is given from the multi control circuit, a command fetch operation is performed on the device.

According to the third aspect of the present invention, the command control circuit holds the information of the command fetch request packet received from each device, so that the sequence shifts to the command fetch operation as soon as the sequence execution permission is given. it can. Therefore, an efficient and high-speed operation can be performed.

According to a fourth aspect of the present invention, in the multi-initiator control apparatus according to the third aspect, each of the plurality of command control circuits is controlled by a corresponding device even during execution of a data transfer processing sequence. Is received.

According to the fourth aspect of the present invention, even when a certain device is executing a command, a command fetch request from another device can be processed. Therefore, it is possible to cope with access from each device regardless of the state of the command processing.

According to a fifth aspect of the present invention, in the multi-initiator control apparatus according to the first aspect, each of the plurality of command control circuits has a register for storing an address for performing a command processing sequence. The address of the register may be, in accordance with a node number of a device corresponding to a command control circuit to which the register belongs, an address of a register of a reference of the plurality of command control circuits in units of a predetermined value. It is obtained by address extension.

According to the fifth aspect of the present invention, the address of the reference register of the command control circuit is extended,
Since the register address is obtained, even when a plurality of devices are connected, the CPU does not need to manage the address of the register accessed by each device. For this reason, the load on the CPU is reduced, and high-speed operation can be performed as in the case of a single device.

According to a sixth aspect of the present invention, in the multi-initiator control device according to the first aspect, the multi-control circuit sends one from the plurality of devices in a predetermined order each time a command processing sequence is completed. The sequence execution permission is given to one of the plurality of command control circuits corresponding to the selected device.

According to the sixth aspect of the present invention, it is determined whether or not command execution permission is given to each connected device in order, so that a variation in command execution frequency among devices is reduced, and an opportunity to execute a command is provided. It is possible to avoid bias to some devices.

According to a seventh aspect of the present invention, in the multi-initiator control device according to the first aspect, the transfer control circuit controls the data transfer performed by the packet processing circuit with the outside of the multi-initiator control device. The packet processing circuit further extracts data to be transferred from the packet output by the packet filter, outputs the data to the transfer control circuit, and generates a packet from the data transferred to the transfer control circuit. Output to the link core circuit.

According to the seventh aspect of the present invention, the data transfer processing sequence is controlled by the transfer control circuit.
The PU does not participate in the execution of the data transfer processing sequence. Therefore, the load on the CPU during the execution of the data transfer processing sequence can be reduced, and the data transfer can be performed at high speed.

According to an eighth aspect of the present invention, in the multi-initiator control device according to the first aspect, the CPU is capable of giving sequence execution permission to the plurality of command control circuits. is there.

According to the present invention, since the CPU can control the operation timing of the command fetch, the degree of freedom for the sequence control from the firmware is increased, and the sequence processing is performed in synchronization with the firmware specification. It becomes possible.

According to a ninth aspect of the present invention, in the multi-initiator control device according to the first aspect, each of the node numbers of the plurality of devices corresponds to a bit position in a field for identifying the node number. And each of the devices is configured to be identified by a bit position in the field.

According to the ninth aspect of the present invention, since the node number of each device is simply represented by one bit, even if more devices are connected, the management of the devices is performed by a small-scale circuit. It becomes possible.

A tenth aspect of the present invention is a multi-initiator control method for performing communication on a packet basis with each of a plurality of devices connected via a transmission line, wherein Determining whether a command fetch request has been received from one of the devices; and, when determining that the command fetch request has been received, fetching a command from the device. Executing the step of repeatedly selecting one of the plurality of devices in a predetermined order, and performing the step of performing the determination on the selected device and the step of executing the command.

According to the tenth aspect of the present invention, it is determined whether or not command execution permission is given to each connected device in order, so that a chance of executing a command is not biased to some devices. it can.

[0064]

Embodiments of the present invention will be described below with reference to the drawings. The technical scope of the present invention is not limited by the embodiment described here.

FIG. 1 is a block diagram of a data transfer system using a multi-initiator control device according to an embodiment of the present invention. The data transfer system shown in FIG. 1 includes an optical disk drive 1 and initiators 11, 12, and 13 connected to the optical disk drive 1 as devices. The initiators 11 to 13 are, for example, personal computers (PCs). Optical disk drive 1
Is a multi-initiator control device 2 as a target
, DVD-RAM controller 3, head 4, D
And a VD-RAM disk 5.

Each of the initiators 11, 12, 13 and the multi-initiator control device 2 are connected via an IEEE 1394 serial bus (hereinafter simply referred to as a bus) 21, 22, 23 as a transmission path.
The multi-initiator control device 2 is connected to the DVD-RAM controller 3 via the DMA bus 6. D
The VD-RAM controller 3 controls the DV
The data read from the D-RAM disk 5 is subjected to signal processing such as demodulation, and is transferred to the multi-initiator control device 2. Further, the data transferred from the multi-initiator control device 2 is subjected to signal processing such as modulation. Then, the data is written to the DVD-RAM disk 5 via the head 4.

FIG. 2 is a block diagram of the multi-initiator control device of FIG. 1 according to the embodiment of the present invention. 2, the multi-initiator control device 2 includes a CPU 31
A physical layer controller (PHY) 41, a link core circuit (LINK) 42, a packet filter 43, a multi-control circuit 44, a packet processing circuit 45, a transfer control circuit 46, a command reception buffer 47, A register 48 and command control circuits 51, 52, 53 are provided.

In FIG. 2, the CPU 31, the link core circuit 42, the multi-control circuit 44, the transfer control circuit 46, and the command control circuits 51 to 53 can write and read data to and from the control register 48. The packet filter 43 can read the contents of the control register 48. In the following, as an example, SB
Description will be made on the assumption that data transfer is performed between an initiator and a target using P-2 (serial bus protocol-2) as a protocol.

The physical layer controller 41 includes buses 21 to 2
3 has functions such as initialization, arbitration, and control of bias voltage. The physical layer controller 41 converts an electric signal on the buses 21 to 23 into a packet and outputs the packet to the link core circuit 42, or converts a packet received from the link core circuit 42 into an electric signal and converts the packet into an electric signal.
Output to

The link core circuit 42 receives a packet from the physical layer controller 41. Link core circuit 42
Performs error detection code detection, code detection (for example, code detection of an ACK packet) on the received packet, and outputs the packet to the packet filter 43 and the packet processing circuit 45. Further, the link core circuit 42 creates and adds an error detection code to the packet to be transmitted, which is received from the packet processing circuit 45, and transmits it to the physical layer controller 41. Further, the link core circuit 42
Has a retry function for retrying the transfer of a packet when the transfer of the packet fails.

The packet filter 43 receives a packet from the link core circuit 42 and analyzes the contents of the header field of the packet. The packet filter 43
According to the analysis result, it is determined whether or not this packet should be stored in the command receiving buffer 47, and the packet processing circuit 45 is notified. Also, the packet filter 43
Encodes the node number of the initiator of the transmission source of the received packet, and outputs it to the multi-control circuit 44 and the transfer control circuit 46 as a control signal. Further, the packet filter 43 outputs information included in the received packet to the multi control circuit 44 and the transfer control circuit 46.

The multi-control circuit 44 includes the link core circuit 4
2 receives the information included in the received packet from the packet filter 43 and stores it in the command control circuits 51 to 53 according to the control signal output from the packet filter 43. The multi-control circuit 44 gives sequence execution permission to one of the command control circuits 51 to 53, and outputs information output from the command control circuit to which the permission is given to the packet processing circuit 45.

The packet processing circuit 45 operates under the control of the multi-control circuit 44 and causes the packet received by the packet filter 43 to be stored in the command reception buffer 47 to be stored in the command reception buffer 47. The packet stored in the command reception buffer 47 is
It becomes a state in which reading is possible from U31. Further, the packet processing circuit 45 generates a packet including the information received from the multi control circuit 44 and outputs the packet to the link core circuit 42 as a packet to be transmitted.

The transfer control circuit 46 receives a transfer command execution request such as READ / WRITE output from the CPU 31
The packet is received via the control register 48 and is transferred between the packet processing circuit 45 and the DVD-RAM controller 3.

For example, when executing a READ command, the transfer control circuit 46 transfers the data recorded on the DVD-RAM disk 5 to the DVD-RAM controller 3 and the DMA bus 6 based on an execution request from the CPU 31.
And outputs it to the packet processing circuit 45.
The packet processing circuit 45 divides the data received from the transfer control circuit 46 and stores it in a plurality of packets, and outputs these packets to the buses 21 to 23 via the link core circuit 42 and the physical layer controller 41.

When executing the WRITE command, the packet processing circuit 45 receives the packet from the buses 21 to 23 via the physical layer controller 41 and the link core circuit 42, extracts data from the packet, and transfers the data to the transfer control circuit. Output to 46. The transfer control circuit 46 transfers the received data to the DVD-RAM
The data is output to the controller 3 and recorded on the DVD-RAM disk 5. Such packet generation processing and packet transfer processing are controlled by the transfer control circuit 46.

As described above, since the transfer control circuit 46 performs the data transfer processing sequence, the CPU 31 does not participate in the execution of the data transfer processing sequence. Therefore, the load on the CPU 31 in the data transfer processing sequence can be reduced, and high-speed data transfer conforming to IEEE1394 can be realized.

In IEEE 1394, the data length (maximum payload size) that can be transferred in one packet is defined according to the transfer speed. In the present embodiment, the transfer speed is S
400 (transfer speed about 400 Mbit / sec). In this case, the data length that can be transferred in one packet is 2048 bytes.

The command control circuits 51, 52, and 53 correspond to the initiators 11, 12, and 13, respectively.
A command fetch request is received from a corresponding initiator, and a command processing sequence with the initiator is controlled. The multi control circuit 44 manages the sequence execution of the command control circuits 51 to 53. The multi control circuit 44 and the command control circuits 51 to 53
It has an agent register (AGENT_REGISTER) required for the command processing sequence in BP-2.

FIG. 3 is an explanatory diagram of registers of the multi control circuit 44 and the command control circuit 51 of FIG. The configuration of the registers of the command control circuits 52 and 53 is as follows.
The illustration is omitted because it is the same as the command control circuit 51.

The multi control circuit 44 has a MANAGEMENT_AGENT register R10 as an agent register. MANAGEMENT_AGENT register R10 is LOG
Stores an address for fetching a management command such as IN. The command control circuit 51 includes an AGENT_STATE register R1 as an agent register.
1, AGENT_RESET register R12, ORB_POINTER register R13, DOORBELL register R14 and UNSOLICITED_S
It has a TATUS register R15. The command control circuits 52 and 53 have similar registers. The registers of the command control circuits 51 to 53 store addresses and the like for fetching command commands.

The command control circuits 51 to 53 store information required for a command processing sequence with the corresponding initiators 11 to 13, respectively. Such information includes information of a command fetch request packet output by a corresponding one of the initiators 11 to 13 and DOOR
Information indicating that the BELL register has been accessed.

Command control circuits 51 to 53 receive and hold information of command fetch request packets from corresponding initiators 11 to 13, and store information of packets for which sequence execution permission has not been obtained from multi control circuit 44. Queuing, ie, unprocessed commands can be queued. The command fetch request packet is, for example, a BWRQ packet or QWRQ packet. In the case of a BWRQ packet, the command fetch request packet includes an address of a command fetch target.

There are the following two types of access methods when the initiators 11 to 13 issue command fetch requests to the command control circuits 51 to 53, respectively. That is, the command fetch target address (ORB (operation request block
Access to the ORB_POINTER register to write the address of the storage destination of k), and DOORBE using the QWRQ packet
Access to the LL register. Command control circuit 5
1 indicates the address of the command fetch target as ORB_POINTER
When the access is made to the DOORBELL register R14, the fact that the access has been made is stored, that is, information indicating that this access has been made is stored. The same applies to the command control circuits 52 and 53.

FIG. 4 is an explanatory diagram of the address extension. The address of each agent register of the command control circuit 51 is set to an address obtained by adding a predetermined value to the base address (Base Address). The base address is stored in the command control circuit 51.
Of the AGENT_STATE register R11. The address of each agent register of the command control circuit 52 is an address obtained by adding 20h (h represents hexadecimal notation) to the address of the same type of register of the command control circuit 51, and the address of each agent register of the command control circuit 53. Is an address obtained by adding 40h to the address of the same type of register of the command control circuit 51. That is, the command control circuits 51 and 5
The address areas of the registers 2 and 53 are a base address, a base address + 20h, and a base address +
It starts from 40h.

The packet filter 43 analyzes the packets received from the initiators 11 to 13 in the command processing sequence, compares the address accessed by the initiator of the packet source with the address of the agent register, Notify.

The packet filter 43 is LOGI
The received packet is analyzed by extending the address at intervals of, for example, 20 h, in association with the node number of the initiator that is N, and the result is output to the multi-control circuit 44 as a control signal. The base address and the node numbers of the initiators 11 to 13 are preset in the packet filter 43 from the CPU 31.

When the packet transmission source is the initiator 11, the packet filter 43 does not extend the address based on the node number. In this case, the packet filter 43 compares the address of the agent register determined from the base address with the received address, generates a control signal indicating the register to be accessed, and outputs the control signal to the multi-control circuit 44. Further, when the transmission source of the packet is the initiator 12, the packet filter 43 determines the initiator 1 based on the node number.
The address of the agent register determined from the address obtained by adding 20h to the base address of 1 is compared with the received address, a control signal indicating the register to be accessed is generated, and the control signal is output to the multi-control circuit 44. Further, when the packet transmission source is the initiator 13, the packet filter 43 determines, based on the node number,
The address of the agent register determined from the address obtained by adding 40h to the base address of the initiator 11 is compared with the received address, and a control signal indicating the register to be accessed is generated and output to the multi control circuit 44.

The multi-control circuit 44 accesses one of the registers of the command control circuits 51 to 53 indicated by the control signal output from the packet filter 43 and stores the information of the command fetch request packet as necessary. .

By managing the address of the agent register in this way, the address management from the CPU 31 is simplified. Since the address is obtained from the node number of the initiator of the source of the received packet, the IEEE
Even when an initiator of 63 nodes, which is the maximum number of nodes connectable to one local bus in the 1394 standard, is connected, it is not necessary to increase the circuit scale for managing the address of the agent register. In addition,
Although the case where the address extension from the base address is performed in units of 20 h has been described, the unit of the address extension may be another value.

FIG. 5 is an explanatory diagram showing a method of managing the node number of the initiator. In the present embodiment, since the number of initiators connected to the multi-initiator control device 2 is three, these are identified by a 3-bit field. That is, when the bit N1 is "1", it indicates the initiator 11, and similarly, when the bit N2 or N3 is "1", it indicates the initiator 12 or 13, respectively.

For example, the node numbers of the initiators 11, 12, and 13 are ffc0h, ffc1h, and ffc, respectively.
2h, and the received packet has the node number ffc
It is assumed that 0h is specified. In this case, the packet filter 43 outputs “001” to the multi control circuit 44 to notify that the packet has been sent from the initiator 11.

The packet processing circuit 45 converts the node number represented in the 3-bit field of the data output from the multi-control circuit 44 into a 16-bit node number such as ffc0h and incorporates it into the packet.

As described above, the 16-bit node number is set to 1
Since the bits are expressed and managed, the circuits such as the multi-control circuit 44 that handles node numbers can be simplified. Here, the correspondence between the node numbers of the initiators 11 to 13 and the positions of the bits N1, N2, and N3 is 1
Any relationship may be used as long as the relationship is one-to-one. Of course, in the multi control circuit 44 or the like, each node number may be used as it is.

FIG. 6 is a flowchart showing a sequence of a command execution process in the multi control circuit 44 of FIG. Here, description will be made assuming that the node numbers of the initiators 11, 12, and 13 are Node1, Node2, and Node3, respectively. In addition, the description will be made assuming that the initiators 11 to 13 access the ORB_POINTER register when a command fetch request is issued to each of the command control circuits 51 to 53.

First, the multi-control circuit 44 executes step S
At 11, it is determined whether or not the command processing sequence of the initiator 11 of Node 1 is not completed. That is, the multi-control circuit 44 determines whether or not the command control circuit 51 receives the command fetch request and queues the unprocessed command. If the command has been queued, the process proceeds to step S12, where the command is queued. If not, the process proceeds to step S13.

In step S12, the multi control circuit 44
Gives the command control circuit 51 permission to execute a sequence. The command control circuit 51 uses the stored address of the command fetch target and stores the initiator 1
Fetch commands from 1. That is, the command control circuit 51 notifies the packet processing circuit 45 of the address of the command fetch target, and the packet processing circuit 45 generates a packet including this address, and transmits the packet via the link core circuit 42 and the bus 21 to the initiator. Send to 11. In response to this, the initiator 11 transmits a packet including a command, and the packet is stored in the command receiving buffer 47 via the bus 21, the link core circuit 42, and the packet processing circuit 45. The CPU 31
Executes the command contained in this packet. In this manner, a series of transactions for fetching and executing a command can be performed. Upon completion of the execution of the command, the process proceeds to step S13.

In step S13, the multi control circuit 44
Determines whether the command processing sequence of the initiator 12 of Node 2 is incomplete. That is, the multi-control circuit 44 determines whether or not the command control circuit 52 receives the command fetch request and queues the unprocessed command. If not, the process proceeds to step S15.

In step S14, the multi control circuit 44
Gives sequence execution permission to the command control circuit 52. As in step S12, the command control circuit 52 fetches a command from the initiator 12 of Node2, causes the CPU 31 to execute the command, and when the execution of the command is completed, proceeds to step S15.

In step S15, the multi control circuit 44
Determines whether the command processing sequence of the initiator 13 of the Node 3 is incomplete. That is, the multi-control circuit 44 determines whether or not the command control circuit 53 receives the command fetch request and queues an unprocessed command. If the command has been queued, the process proceeds to step S16, where the queue is queued. If not, the process returns to step S11.

In step S16, the multi control circuit 44
Gives sequence execution permission to the command control circuit 53. The command control circuit 53 fetches a command from the initiator 13 of Node 3 as in step S12, causes the CPU 31 to execute the command, and returns to step S11 when the execution of the command is completed. After that,
A similar sequence is repeated.

As described above, the multi-control circuit 44 constantly manages the state of command execution by the connected initiators, and determines whether to give command execution permission equally to each initiator in order. In addition, it is possible to prevent a variation in the frequency of executing a command from occurring between initiators.

Note that, also when the initiators 11 to 13 access the DOORBELL register at the time of a command fetch request, the operation when fetching commands from the initiators 11 to 13 is complicated. ,
The same is true. In this case, the following operation is performed for the initiator 11 instead of step S12.

That is, the command control circuit 51
The address stored in the _POINTER register R13 is transmitted to the initiator 11, and in response, the initiator 11 transmits a packet including a pointer indicating the ORB to be referred next. The command control circuit 51 notifies the packet processing circuit 45 of the pointer, and the packet processing circuit 45 generates a packet including the pointer and transmits the packet to the initiator 11. In response, the initiator 11 transmits a packet including the command. The CPU 31 executes the command of this packet. The same operation may be performed for the initiators 12 and 13 instead of steps S14 and S16, respectively.

Further, the case where the number of initiators is three has been described, but the number of initiators is not limited to this. That is, when the number of initiators is up to the maximum number (63) that can be connected to one local bus defined by the IEEE 1394 standard, by providing a command control circuit corresponding to each initiator, The same processing can be performed.

FIGS. 7A to 7E are explanatory diagrams showing the format of a packet used inside the multi-initiator control device 2 of FIG. 7A to 7E, a hatched area indicates a reserve area. More specifically, FIG.
Indicates the format of a BWRQ (block write request) packet. FIG. 7B shows a QWRQ (quadlet write
request) Indicates the format of the packet. FIG. 7C
5 shows a format of a WRS (write response) packet. FIG. 7D shows a format of a BRRQ (block read request) packet. FIG. 7E shows BRRS (block
read response) Indicates the format of the packet.

FIGS. 8A to 8E show IEEE 1394 bus 2
It is explanatory drawing which shows the format of the packet on 1-23. 8A to 8E correspond to the formats shown in FIGS. 7A to 7E, respectively.

The link core circuit 42 transmits the packet to the bus 2
1 to 23, packets of the formats of FIGS. 7A to 7E are received, and header_CR
CRC (cyclic redundancy check) such as C and data_CRC
Ask for the code. The link core circuit 42 adds these CRC code fields to the received packet,
The obtained packets in the formats of FIGS. 8A to 8E are output to the physical layer controller 41.

When receiving a packet from the buses 21 to 23, the link core circuit 42 receives the packet in the format shown in FIGS. 8A to 8E and refers to the header_CRC area and the data_CRC area included in the packet, CR
Error detection by C is performed. The link core circuit 42 outputs the packet after the error detection to the packet filter 43 and the packet processing circuit 45 in the format of FIGS. 7A to 7E.

The operation of the multi-initiator control device 2 shown in FIG. 2 will be described below. First, execution of the LOGIN command will be described. Multi-initiator control device 2
Executes the command processing sequence of FIG. 9 with the initiator 11. LOGI between the initiator 11
When the command processing sequence of the N command ends, C
The PU 31 enables one bit in the control register 48 corresponding to the node number of the initiator 11 that has logged. Similarly, LOGIN processing is performed with the initiators 12 and 13. This series of LOGIN
Through the processing, the command control circuits 51, 52, and 53 are assigned to the initiators 11, 12, and 13, respectively.

Next, execution of the READ command will be described. The command processing sequence between the multi-initiator control device 2 and the initiators 11 to 13 is the same as that in FIG. 10 except that the command control circuits 51 to 53 can queue commands. .

Initiator 11 sets QWRQ in AGENT_RESET register R12 to execute the READ command.
Send a packet. Next, the initiator 11
The RQ packet is transmitted to the command control circuit 51 corresponding to the initiator 11, and the address of the ORB to be accessed by the command control circuit 51 is written to the ORB_POINTER register R13. The multi-control circuit 44 manages the states of the command control circuits 51 to 53, for example, the command control circuit 5
When sequence execution permission is given to 1, the command control circuit 51 executes command fetch.

The command receiving buffer 47 stores a packet containing a command received from the initiator 11. The CPU 31 reads a command from the command reception buffer 47 and activates the transfer control circuit 46 to execute a READ command. The transfer control circuit 46
D from the DVD-RAM controller 3 via the A bus 6
The data on the VD-RAM disk 5 is read and output to the packet processing circuit 45. The packet processing circuit 45 converts the input data into a packet,
Output to

Also, during the execution of the data transfer sequence for the initiator 11, the WRI
It is assumed that a command fetch request packet of a READ command has been received from the initiator 13 of the TE command. In this case, the command control circuit 52 corresponding to the initiator 12 receives the command fetch request from the initiator 12 even during the execution of the data transfer sequence. That is, the command control circuit 52 stores an address to be accessed for command fetch according to the control signal from the multi-control circuit 44, and waits for sequence execution permission. Similarly, the command control circuit 53 corresponding to the initiator 13 receives the command fetch request from the initiator 13 even during the execution of the data transfer sequence, and waits for the sequence execution permission.

The multi-control circuit 44 includes the initiator 11
When the data transfer processing sequence for the command is completed, the queuing state of the command in the command control circuit 52, that is, whether or not the command control circuit 52 has received a command fetch request is checked. When recognizing that the queue has been queued, the multi control circuit 44 gives the command control circuit 52 a sequence execution permission. When receiving the sequence execution permission from the multi-control circuit 44, the command control circuit 52 executes a command processing sequence for the initiator 12. The packet processing circuit 45 stores the received packet in the command reception buffer 47.

The CPU 31 reads out the command from the command receiving buffer 47 and activates the transfer control circuit 46 to execute the WRITE command. Transfer control circuit 4
6 is for reading data from the initiator 12
The packet is transferred to the link core circuit 42. The transfer control circuit 46 reads the data received from the initiator 12 via the link core circuit 42,
DVD-RAM via VD-RAM controller 3
Write to disk 5. After the specified amount of transfer data has been written to the DVD-RAM disk 5, the transfer control circuit 46 transmits status information to the initiator 12, and the data transfer processing sequence ends.

The multi-control circuit 44 includes the initiator 12
When the command processing sequence for is completed, the queuing state of the command in the command control circuit 53 is checked, and if it is recognized that the command is queued, sequence execution permission is given to the command control circuit 53. Upon receiving the sequence execution permission from the multi-control circuit 44, the command control circuit 53 fetches a command to the initiator 13 and
7 stores the received packet. Then, similarly, CPU
31 activates the transfer control circuit 46 and executes the READ command.

As described above, in the multi-initiator control device 2 of the present embodiment, the command control circuits 51, 52,
53 performs a command processing sequence for the corresponding initiator, and the multi-control circuit 44 controls the command control circuits 51, 52, 53 to enable a sequence with a plurality of initiators. Therefore, the CPU 31 does not need to perform a command processing sequence such as a command fetch. The CPU 31 executes the command stored in the command receiving buffer 47. The data transfer processing sequence is performed by the transfer control circuit 46.
Done by Therefore, efficient sequence control and data transfer control are possible, and a plurality of initiators can be managed without increasing the load on the CPU 31.

(Modification) In this modification, the CPU 31 replaces the multi-control circuit 44 with the control register 48.
An example will be described in which sequence execution permission is given to the command control circuits 51 to 53 via, and the command fetch timing is controlled.

For example, the data transfer processing sequence performed by the transfer control circuit 46 can be basically performed only by hardware. However, processing of a command received from an initiator cannot be processed by hardware alone, and may require processing by firmware. Further, even when the data transfer processing sequence is being performed, an error may occur in the transfer data, and processing by firmware to deal with the error may be required.

In such a case, the processing by the firmware executed by the CPU 31 may not be able to catch up with the processing by the hardware, so that the CPU 31 needs to control the command processing sequence.

This will be described with reference to FIGS. It is assumed that the processing of the LOGIN command of the initiators 11 and 12 has been completed. The initiator 11 sends a BWRQ to the ORB_POINTER register R13 of the command control circuit 51.
Send a packet. When the multi control circuit 44 gives sequence execution permission to the command control circuit 51 corresponding to the initiator 11, the command control circuit 51 performs a command fetch for the initiator 11. The packet processing circuit 45 stores the received packet from the initiator 11 at this time in the command receiving buffer 47. C
The PU 31 reads out the command from the command receiving buffer 47 and executes it. This command is required to be processed by firmware.

At this time, the CPU 31
, The command control circuit 52 waits for sequence execution permission. While the CPU 31 is executing the command of the initiator 11, the command fetch target address of, for example, a READ command input from the initiator 12 is stored in the command control circuit 52.

When the command processing of the initiator 11 is completed, the CPU 31 gives a sequence execution permission to the multi control circuit 44, and the multi control circuit 44 gives a sequence execution permission to the command control circuit 52.
The command control circuit 52 having received the sequence execution permission fetches the command of the initiator 12. The packet processing circuit 45 stores the packet received from the initiator 12 in the command receiving buffer 47. The CPU 31 reads the command in the command receiving buffer 47 and executes the command of the initiator 12.

As described above, according to the present modification, the activation timing of the command processing sequence can be arbitrarily controlled by the CPU 31, so that the command processing sequence and the operation of the CPU 31 can be synchronized.
The sequence management from the CPU 31 is facilitated.

In the above embodiment, the initiator is the DV
Although the example of transferring data to and from the D-RAM disk has been described, the same applies to the case of transferring data to and from a data recording medium such as an optical disk or a magnetic disk of another format.

[0127]

As described above, according to the present invention, even when a plurality of initiators are connected, the load on the CPU is not increased, so that a plurality of initiators are connected and data transfer is performed at high speed. And a multi-initiator control device and method capable of performing the above-described operations.

[Brief description of the drawings]

FIG. 1 is a block diagram of a data transfer system using a multi-initiator control device according to an embodiment of the present invention.

FIG. 2 is a block diagram of the multi-initiator control device of FIG. 1 according to an embodiment of the present invention.

FIG. 3 is an explanatory diagram of registers of a multi control circuit and a command control circuit of FIG. 2;

FIG. 4 is an explanatory diagram of an address extension.

FIG. 5 is an explanatory diagram showing a method for managing an initiator node number;

FIG. 6 is a flowchart illustrating a sequence of a command execution process in the multi-control circuit of FIG. 2;

FIG. 7A is an explanatory diagram showing a format of a BWRQ packet used inside the multi-initiator control device of FIG. 2;

FIG. 7B is an explanatory diagram showing a format of a QWRQ packet used inside the multi-initiator control device of FIG. 2;

FIG. 7C is an explanatory diagram showing a format of a WRS packet used inside the multi-initiator control device of FIG. 2;

FIG. 7D is an explanatory diagram showing a format of a BRRQ packet used inside the multi-initiator control device of FIG. 2;

7E is an explanatory diagram showing a format of a BRRS packet used inside the multi-initiator control device of FIG. 2;

FIG. 8A is an explanatory diagram showing a format of a BWRQ packet on an IEEE 1394 bus.

FIG. 8B is an explanatory diagram showing a format of a QWRQ packet on an IEEE 1394 bus.

FIG. 8C is an explanatory diagram showing a format of a WRS packet on an IEEE 1394 bus.

FIG. 8D is an explanatory diagram showing a format of a BRRQ packet on an IEEE 1394 bus.

FIG. 8E is an explanatory diagram showing a format of a BRRS packet on an IEEE 1394 bus.

FIG. 9 is an explanatory diagram showing a command processing sequence for executing a LOGIN command.

FIG. 10 is an explanatory diagram showing a command processing sequence for executing a READ command.

FIG. 11 is a block diagram illustrating a configuration of a conventional sequence processing device.

[Explanation of symbols]

Reference Signs List 1 optical disk drive 2 multi-initiator control device 3 DVD-RAM controller 4 head 5 DVD-RAM disk 6 DMA bus 11, 12, 13 initiator (device) 21, 22, 23 IEEE 1394 serial bus (transmission path) 31 CPU 41 physical layer controller 42 link core circuit 43 packet filter 44 multi-control circuit 45 packet processing circuit 46 transfer control circuit 47 command receiving buffer 48 control register 51, 52, 53 command control circuit

Continued on the front page F term (reference) 5B014 EB01 GD05 GD12 GD22 GD32 GE05 HA07 HA14 5K034 AA02 AA07 DD03 EE11 FF01 MM18

Claims (10)

[Claims] 1. A multi-initiator control device for communicating with each of a plurality of devices connected via a transmission line in units of packets, wherein the multi-initiator control device transmits a packet to be transmitted to the transmission line. A link core circuit that receives a packet from the transmission path, performs error detection, and outputs the packet; a packet filter that analyzes the packet received by the link core circuit and outputs a result thereof; A plurality of command control circuits for controlling the command processing sequence, a multi-control circuit for granting sequence execution permission to one of the plurality of command control circuits, and information output by the permitted command control circuit. While generating a packet to be transmitted as the packet to be transmitted and outputting the packet to the link core circuit for transmission. CPU but to execute the packet processing circuit for outputting according to the analysis result of the packet filter and output by the received packet is output, a command to the packet processing circuit is included in a packet to be output (central processing unit)
A multi-initiator control device comprising: 2. The multi-initiator control device according to claim 1, wherein each of the plurality of command control circuits outputs information necessary for a command processing sequence between the corresponding device and the corresponding device. The multi-control circuit stores and outputs the sequence execution permission when the sequence execution permission is given. The multi-control circuit is included in a packet received and output by the link core circuit, between the device and the device that transmitted the packet. Information necessary for the command processing sequence of the plurality of command control circuits corresponding to the device in accordance with the output of the packet filter, and stored therein. Generates and outputs a packet having information output by the command control circuit to which the sequence execution permission has been given, and responds to the packet. A multi-initiator control device for receiving and outputting a packet output by a device corresponding to the command control circuit. 3. The multi-initiator control device according to claim 1, wherein each of said plurality of command control circuits stores information of a command fetch request packet transmitted from a corresponding device, and A multi-initiator control device for performing a command fetch operation on a device when a sequence execution permission is given. 4. The multi-initiator control device according to claim 3, wherein each of the plurality of command control circuits receives a command fetch request from a corresponding device even during execution of a data transfer processing sequence. A multi-initiator control device characterized by the following. 5. The multi-initiator control device according to claim 1, wherein each of the plurality of command control circuits has a register for storing an address for performing a command processing sequence, and the address of the register is According to the node number of the device corresponding to the command control circuit to which the register belongs, the address of the register of the plurality of command control circuits as a reference is obtained by expanding the address in units of a predetermined value. A multi-initiator control device characterized in that: 6. The multi-initiator control device according to claim 1, wherein the multi-control circuit selects one from the plurality of devices in a predetermined order each time a command processing sequence ends, and A multi-initiator control device which gives the sequence execution permission to a command control circuit corresponding to a selected device. 7. The multi-initiator control device according to claim 1, further comprising: a transfer control circuit that controls data transfer performed by the packet processing circuit with the outside of the multi-initiator control device. The circuit extracts data to be transferred from the packet output by the packet filter and outputs the data to the transfer control circuit, while generating a packet from the data transferred to the transfer control circuit and outputs the packet to the link core circuit. A multi-initiator control device. 8. The multi-initiator control device according to claim 1, wherein the CPU is capable of giving sequence execution permission to the plurality of command control circuits. . 9. The multi-initiator control device according to claim 1, wherein a node number of each of the plurality of devices is associated with a bit position in a field for identifying a node number, and , Each of which is configured to be identified by a position of a bit in the field. 10. A multi-initiator control method for performing communication on a packet basis with each of a plurality of devices connected via a transmission path, wherein a command fetch request is issued from one of the plurality of devices. Determining whether or not the device has received the command fetch request; and, when determining that the command fetch request has been stored, fetching and executing the command from the device. A multi-initiator control method that repeats selecting one of the plurality of devices in a predetermined order, and performing the determination on the selected device and the step of executing the command.